SP605 Standalone Applications

Transcription

1 SP605 Standalone Applications July 2011 Copyright 2011 Xilinx XTP064

2 Revision History Date Version Description 07/06/ Up-rev 13.1 GPIO_HDR Design to /01/ Up-Rev 12.4 GPIO_HDR Design to /21/ Up-Rev 12.3 GPIO_HDR Design to Added SDK flow. 10/05/ Up-Rev 12.2 GPIO_HDR Design to /23/ Up-Rev 12.1 GPIO_HDR Design to Set RZQ and ZIO pins in MPMC core GUI. See MPMC 6.01.a Product Specification for more details. Updated SI Labs USB UART Drivers URL Copyright 2011 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

3 Note: This presentation applies to the SP605 Overview Xilinx SP605 Board Software Requirements SP605 Setup Multi-pin Wake-up GPIO Header References

4 Xilinx SP605 Board Note: Presentation applies to the SP605

5 Note: Presentation applies to the SP605 ISE Software Requirement Xilinx ISE 13.2 software

6 Note: Presentation applies to the SP605 EDK Software Requirement Xilinx EDK 13.2 software

7 Note: Presentation applies to the SP605 EDK Software Requirement Xilinx SDK 13.2 software

8 SP605 Setup Power on the SP605 board for UART Drivers Installation Connect a USB Type-A to Mini-B cable to the USB UART connector on the SP605 board Connect this cable to your PC

9 Note: Presentation applies to the SP605 SP605 Setup Install USB UART Drivers CP210x_VCP_Win_XP_S2K3_Vista_7.exe

10 Note: Presentation applies to the SP605 SP605 Setup Reboot your PC if necessary Right-click on My Computer and select Properties Select the Hardware tab Click on Device Manager

11 Note: Presentation applies to the SP605 SP605 Setup Expand the Ports Hardware Right-click on Silicon Labs CP210x USB to UART Bridge and select Properties

12 Note: Presentation applies to the SP605 SP605 Setup Under Port Settings tab Click Advanced Set the COM Port to an open Com Port setting from COM1 to COM4

13 Note: Presentation applies to the SP605 SP605 Setup Unzip the rdf0034.zip file Available through Includes AR32713 Recommended constraints for the XPS_LL_TEMAC systems

14 Multi-pin Wake-up

15 SP605 Setup Connect a USB Type-A to Mini-B cable to the USB JTAG connector on the SP605 board Connect this cable to your PC

16 Multi-pin Wake-up This test will involve removing and replacing the Suspend Jumper, J47, seen here In this design, when an internal FPGA condition occurs and the suspend jumper is in place, suspend is initiated The FPGA condition is when the two bit counter reaches 11

17 Note: Suspend jumper can be on or off during programming Multi-pin Wake-up Open an ISE Design Suite Command Prompt Run xmd to download the Bitstream file The xmd.ini file will enter the required download commands cd C:\sp605_standalone_apps\multi_pin_wake_up xmd

18 Multi-pin Wake-up The design shows a two bit counter on LEDs DS3 & 4 The Awake LED (DS7) is on

19 Multi-pin Wake-up Install a jumper on J47 The Counter LEDs continues to 11 and then stops counting The Awake LED goes out

20 Multi-pin Wake-up Remove the jumper on J47 The Counter LEDs resume counting at 11 The Awake LED comes on

21 GPIO Header Loopback Test

22 Note: Presentation applies to the SP605 Embedded Processor Design The provided embedded reference design is supported as is Please refer to the click through license agreement Embedded reference design has been verified on the SP605 Evaluation Kit Design consists of Early Access IP Design may change in subsequent releases The reference design will allow users to: Re-build and verify functionality on the SP605 evaluation kit

23 Note: Presentation applies to the SP605 SP605 MicroBlaze Hardware The SP605 MicroBlaze Design Hardware includes: DDR3 Interface (128 MB) BRAM External Memory Controller (EMC) Flash Memory Networking UART Interrupt Controller GPIO (HDR Pins, IIC, LEDs) Timer System ACE PLB v46 Bus

24 GPIO Header Loopback Test Connect two USB Type-A to Mini-B cables to the USB JTAG and UART connectors on the SP605 board Connect these cables to your PC

25 GPIO Header Loopback Test Locate Jumper J55

26 GPIO Header Loopback Test Connect two jumpers across J55 Connect pins 1 & 2 Connect pins 3 & 4

27 Note: Presentation applies to the SP605 GPIO Header Loopback Test Do not connect any jumpers across pins 5 or 6 These pins are connected to power and ground

28 Note: Tera Term may need to be restarted if board power is cycled GPIO Header Loopback Test Board Power must be on before starting Tera Term Start the Terminal Program Select your USB Com Port Set the baud to 9600

29 Note: Presentation applies to the SP605 GPIO Header Loopback Test Open an ISE Design Suite Command Prompt Run xmd to download the Bitstream and ELF file The xmd.ini file will enter the required download commands cd C:\sp605_standalone_apps\gpio_hdr\ready_for_download xmd

30 Note: Presentation applies to the SP605 GPIO Header Loopback Test The test results will appear in the terminal window

31 Compile SP605 GPIO Header Loopback Design

32 Compile SP605 GPIO Header Loopback Design If desired, FPGA compile can be skipped by opening SDK directly: Start All Programs Xilinx ISE Design Suite 13.2 EDK Xilinx Software Development Kit Select the workspace: <design files>\sdk\sdk_workspace_35 Go to SDK Software Compile

33 Note: Presentation applies to the SP605 Compile SP605 GPIO Header Loopback Design Open XPS project <project directory>\ system.xmp Create the hardware design, system.bit, located in <project directory> /implementation Select Hardware Generate Bitstream (1) 1

34 Note: Presentation applies to the SP605 Compile SP605 GPIO Header Loopback Design Open SDK Select Project Export Hardware Design to SDK (1) Click Export & Launch SDK (2) 1 2

35 Compile SP605 GPIO Header Loopback Design SDK Software Compile - Build ELF files in SDK Select Project Build All (1) Note: If by-passing the FPGA compile, the ELF files are already built; if desired, the ELF files can be re-built by selecting Clean followed by Build All 1

36 Download SP605 GPIO Header Loopback Design

37 Download SP605 GPIO Header Loopback Design Init memory with the Bootloop ELF Update the bitstream (download.bit) with the Bootloop ELF Select Xilinx Tools Program FPGA (1) 1

38 Note: Verify the Bitstream and BMM File paths match your design path Download SP605 GPIO Header Loopback Design Init memory with the Bootloader Application ELF Select bootloop (1) Click Program 1

39 Download SP605 GPIO Header Loopback Design Launch XMD Select Xilinx Tools XMD Console (1) 1

40 Download SP605 GPIO Header Loopback Design Connect XMD to the MicroBlaze: cd C:/sp605_standalone_apps/gpio_hdr/SDK/SDK_Workspace_35 connect mb mdm

41 Download SP605 GPIO Header Loopback Design To execute a memory read, type mrd 0x This will read the memory address at the reset vector; the value should be 0xB as shown below

42 Download SP605 GPIO Header Loopback Design Download and run the System Monitor ELF file: dow hello_gpio_hdr/debug/hello_gpio_hdr.elf

43 Download SP605 GPIO Header Loopback Design Download and run the System Monitor ELF file: con

44 Note: Presentation applies to the SP605 Download SP605 GPIO Header Loopback Design The test results will appear in the terminal window

45 Download SP605 GPIO Header Loopback Design Init memory with the GPIO Header ELF Update the bitstream (download.bit) with the Bootloader ELF Select Xilinx Tools Program FPGA (1) 1

46 Note: Always reselect the desired ELF file at this step Download SP605 GPIO Header Loopback Design Init memory with the GPIO Header ELF Select <Design Files>\gpio_hdr\SDK\SDK_Workspace_35 \hello_gpio_hdr\debug\hello_gpio_hdr.elf (1) Click Program 1

47 Note: Presentation applies to the SP605 Download SP605 GPIO Header Loopback Design Hello GPIO Header ELF runs in the terminal window

48 Generate GPIO Header ACE File (Optional) Generate ACE file Select Xilinx Tools Launch Shell (1) 1

49 Note: Presentation applies to the SP605 Generate GPIO Header ACE File (Optional) Generate ACE file cd..\..\ready_for_download make_download_files.bat Copy the contents of ready_for_download/cf_image to your CompactFlash

50 References

51 References EDK Documentation Embedded System Tools Reference Guide System ACE CF System ACE CompactFlash Solution Spartan-6 Configuration Spartan-6 FPGA Configuration User Guide

52 Documentation

53 Documentation Spartan-6 Spartan-6 FPGA Family SP605 Documentation Spartan-6 FPGA SP605 Evaluation Kit SP605 Getting Started Guide SP605 Hardware User Guide SP605 Reference Design User Guide