ELAN RII CPU Macro Assembler

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ELAN RII CPU Macro Assembler 1. Source Files Assembly source file (*.asm) should be written with this assembly language and can include files written in the same language.

1 ELAN RII CPU Macro Assembler 1. Source Files Assembly source file (*.asm) should be written with this assembly language and can include files written in the same language. Each statement line in the source file should adhere to the following format: [Label [:]] Mnemonics [Operands] [;Comments] Blank lines are treated as comments. Blanks or tabs separate elements of the statement line. All symbols are case insensitive. 1.1 Label Label name must start from column 1 of the line and may be terminated by a colon (:). The label and the colon can be seperated by blanks. Labels must begin with an alphabetic character or an underscore (_) or (@) and followed by alphanumeric characters or underscore(_) or (@). The max label length is 32 characters including :. If the label field has a colon sign, then the mnemonic can follow immediately without space to seperate characters. Assembler directives INCLUDE, DEFINE, UNDEF, PUBLIC, EXTERN can start from column Mnemonic Assembler instructions, directives, and macro calls must begin after column Operands Instruction operands or macro parameters: Multiple operands must be separated by commas(,). Operands start with a pound sign #, which means immediate addressing. 1.4 Comments Comments must start with a semicolon (;) in a line or in a block enclosed within /* and */. 1

2 2. Output Files The output files after assembly become List file (*.lst) and Object file (*.obj) from the source file. 2.1 List File The List file is generated after a source file is assembled successfully. The starting address shown on the List file begins at 0x00 no matter how user sets the absolute address, i.e., by CSEG directive or otherwise. For the instructions with labels (ex: jmp, call), the operand part of the object code will always be 0 due to the linker relocated property. The final result of a project after a link process will show in MAP file. The MAP file is generated after linking and it will show the absolute code location and the object code with absolute operand in opcode. Format: Line1:Version information (ELAN RII8000 CPU Assembler version X.XX List file) Line2: Filename (C:\program files\project\test.asm) Line3: Assemble date and time (Mon Apr 24 12:00: ) Line4: Space Line5: Indication title (Line No Loc ObjCode Source) Line6: Space Line7+: The contents LineN-1: Space LineN: The final line shows the result of assembly Description: The numbers in decimal under Line No show the line numbers of the corresponding line. The number of the line from Include file is followed by an I and the number of macro expansion line is followed by an M. The numbers under Loc shows the address of the corresponding line in code segment. The Loc number starts from 0x0000 from every CSEG regardless of whether user writes the absolute address or not. The numbers in hexadecimal under ObjCode shows the object code of the corresponding statement. If the source is an EQU definition, the value would be shown with a = prefix. Because of relocation, the instruction with label will show the label value as 0. The texts under Source show the corresponding original text line in the source file. 2

3 List file format example: ELAN RII8000 CPU Assembler version 0.00 List file C:\Progeam Files\project\test.asm Mon Apr 24 12:00: Line No Loc ObjCode Source 1 INCLUDE <xxx.def> 1I ;Include line 1 2I ;Include line =0002 A1 equ A501 MOV A,#1 5 MACROCALL ; macro, defined anywhere 5M NOP ;content of macro 5M NOP ;content of macro A502 MOV A,#2 7 MOC A,#3 : Xxx Error(s), xxx Warning(s) 3. Numeric Presentation Decimal Hexadecimal Octal Binary 0d(D)<digits> or <digits>d(d) or <digits> 0x(X)<digits> or <digits>h(h) if started with A~F, must add 0 first, ex: 0fH for fh. 0o(O)<digits> or <digits>o(o) 0b(B)<digits> or <digits>b(b) 3

4 4. Arithmetic Operators and Precedence in Expression ( Left parenthesis ) Right parenthesis! Logical NOT - Unary Minus (Negative) ~ Complement * Multiplication / Division % Modulo << Left shift >> Right shift + Add - Subtraction > Great than < Less than >= Great than or equal to <= Less than or equal to == Equality!= Not equal to & Bitwise AND ^ Bitwise XOR Bitwise OR && Logical AND Logical OR 5. Assembler Directive 5.1 END: End of program, all codes after END directive will be discarded. Syntax: END 5.2 EQU: Define a constant Syntax: <label> EQU <expression> 4

5 5.3 DEFINE: Define a label Syntax: DEFINE <label> [<expression>] Description: Label is used for IFDEF/IFNDEF directive. If no expression is used, the label is set to UNDEF: Undefine a label Syntax: UNDEF <label> 5.5 INCLUDE: Include additional source files Syntax: INCLUDE <filename> or INCLUDE filename Description: Used to Include files containing symbol definition, macro or procedure definition, etc. An Include file can include other Include files and the maximum include depth should not exceed 8 levels. Filename within <> are searched in the path set by include path option or by the assembler executing path. Filename within are searched in the path where the source file is located. 5.6 PUBLIC: Specifies the label as a global label that may be referenced by other program. Syntax: PUBLIC <label> [,<label>] 5.7 EXTERN: Imports external symbols from other files. Syntax: EXTERN <label> [,<label>] 5

6 5.8 CSEG: Begin a code segment Syntax: [<name>] CSEG [<start address> ] Note: If name or start address are used, they must be in the same line as CSEG. Description: The CSEG sets the next statements in the designated segment of program ROM until another CSEG or DSEG is encountered. A segment may be broken into pieces within a single source file or in different files. The broken pieces will be grouped together in memory according to the sequence as they appear. Segments with no name specified are designated as defaultcode. The start address is used in setting absolute address of this segment. If no start address is set, linker will assign an address during linker execution. Linker links the segments under following rules: 1. Linker links files according to the sequence given by IDE. 2. If there are more than two segments with the same segment name, only the first code segment definition can be set with a start address. The remaining segments will be grouped together one at a time according to the sequence they were defined. Otherwise, error is generated. 3. After the segments with start address are allocated, the free program ROM may be broken into several fragments. If no fragment is large enough for allocation, the other re-locatable segment will generate errors. User needs to rearrange the segments. 6

7 5.9 DSEG: Begin a data segment Syntax: [<name>] DSEG [<bank>, <offset>] Note: if name or start address are used, they must be in the same line as CSEG. Description: The DSEG assigns memory for the designated segment in RAM until another CSEG or DSEG is encountered. The bank and offset set the address of this segment. The Data segment is not re-locatable by linker, that is, programmer must manage RAM allocation himself. A segment without the bank & offset specified will have the bank & offset assigned (by the assembler) from the previous data segment or start of RAM. The assembler treat the RAM as a linear area, thus the location after the end of one bank will be set to the start (0x80) of next bank. If unbank and stack bank are used, a warning message will occur. Only RES directive can be used in DSEG DB: Declare one byte data Syntax: [<label>[:]] DB <expr> [,<expr>,,<expr>] Description: Define byte in code segment only. Because of the 16-bit PROM word used, the byte data are placed in the Low Byte, High Byte order in PROM. If odd number of byte is used, the final data are placed in Low Byte and the High Byte would be 0x00 if the next line is not DB line nor the first byte in the next DB line DW: Declare one word data Syntax: [<label>[:]] DW <expr> [,<expr>,,<expr>] Description: Used in code segment only TEXT: Declare multiple byte of continuous data Syntax: [<label>[:]] TEXT < characters > [,< characters >,, < characters >] Description: Used in code segment only. The quoted characters are written in continues format. The TEXT maximum length is 128 characters. 7

8 5.13 RES: Reserve number of bytes memory in DSEG Syntax: [<label>[:]] RES <number> Description: Used in data segment only. Number is the value of bytes to reserve. The label does not record bank information when used in programming. User must set the correct bank himself while programming REPEAT, ENDR: repeat a block of statements Syntax: REPEAT <constant number expression> [statements] ENDR 6. Macro Directive MACRO, ENDM: Macro definition statement Syntax: <label> MACRO [<param1>,,<paramn>] <statements> ENDM Description: Macro must be defined before use. Calling other macro in a macro definition is allowed. However, it is not allowed to define a new macro in a macro definition block or call the macro itself (recursive). The max levels of macro call is 8. Local labels in macro must started with $ and will be followed by a 3-digit sequencial number after expansion. Ex: MAC1 MACRO XXX $LOCAL: XXX ENDM $LOCAL will be $LOCAL001 in the first macro expansion and $LOCAL002 in the second. 8

9 7. Conditional Directives 7.1 IF, ELSEIF, ELSE, ENDIF: IF conditional directives Syntax: IF <expression> <statements> [ELSEIF <expression> <statements>] [ELSE <statements>] ENDIF Description: The IF-ELSE-ELSEIF-ENDIF series directives cannot be used in MACRO body. 7.2 IFDEF, ELSEIFDEF, ELSE, ENDIF :IFDEF conditional directives Syntax: IFDEF <label> <statements> [ELSEIFDEF <label> <statements>] [ELSE <statements>] ENDIF Description: IFDEF is TRUE if the label value is non-zero, else FALSE. 7.3 IFNDEF, ELSEIFNDEF, ELSE, ENDIF: IFNDEF conditional directives Syntax: IFNDEF <label> <statements> [ELSEIFNDEF <label> <statements>] [ELSE <statement>] ENDIF Description: IFNDEF is TRUE if the label is zero, else FALSE. 9

10 8. Branch 8.1 JMP: Jump to address Syntax: JMP <label> Description: JMP is used to indicate a branch and assembler will calculate the label address to decide which jump command should be used. 8.2 CALL: Jump to subroutine Syntax: CALL <label> Description: CALL is used to indicate a function call and assembler will calculate the address to decide which call command should be used. 9. Programming Note The final 32word address space in program ROM of each chip is reserved for test program and code option. Be sure not to make code length extends to this area. For EPG3230, EPD3310; the first 32 word address space in program ROM have a special application. Address Usage 0000 Reset vector 0002~000B 5 level interrupt vectors 000C-001F Reserved area (not for user use) 0020 User program The instruction RPT r will repeat the next instruction content of register r times, but it cannot be followed by itself. All branch instructions are as follows: RPT, JBC, JBS, JDNZ, JINZ, JGE, JLE, JE, SJMP, LJMP, SCALL, S0CALL, and LCALL. The directives are JMP and CALL. 10

11 10. Reserved Word A CSEG DB DEFINE DSEG DW ELSE ELSEIF ELSEIFDEF ELSEIFNDEF END ENDIF ENDM ENDR EQU EXTERN IF IFDEF IFNDEF INCLUDE MACRO UNDEF PUBLIC REPEAT RES TEXT JMP CALL ( ) + - * / %! ~ ==!= << >> < > <= >= & ^ && $ # 11. Instruction Set Remark: k : constant r : File Register addr : address b : bit p : special file register(00h~1fh) i : Table pointer control Type Instruction Binary Mnemonic Operation Status System Control Table Look Up Cycles Affected NOP No Operation None WDTC WDT<-0 None 1 /TO<-1, /PD< RET PC<-(Top of stack) None RETI PC<-(Top of stack) None 1 Enable interrupt P Enter IDEL MODE if MS1=1 Enter EP MODE if MS1=0 None kkkk kkkk BANK #k BSR<-k None kkkk kkkk TBPTH #k TABPTRH<-k None kkkk kkkk TBPTM #k TABPTRM<-k None kkkk kkkk TBPTL #k TABPTRL<-k None ii rrrr rrrr TBRD i,r r<-rom[(tabpt)] (*1,*2) rrrr rrrr TBRD A,r r<-rom[(tabptr+acc )] (*2) None 2 None 2 11

12 Logic Compare rrrr rrrr OR A,r A<- A.or.r Z rrrr rrrr OR r, A r<- r.or.a Z kkkk kkkk OR A, #k A<- A.or.k Z rrrr rrrr AND A,r A<- A.and.r Z rrrr rrrr AND r, A r<- r.and.a Z kkkk kkkk AND A, #k A<- A.and.k Z rrrr rrrr XOR A,r A<- A.xor.r Z rrrr rrrr XOR r, A r<- r.xor.a Z kkkk kkkk XOR A, #k A<- A.xor.k Z rrrr rrrr COMA r A<- /r Z rrrr rrrr COM r r<- /r Z rrrr rrrr RRCA r A(n-1)<-r(n) C 1 C<-r(0) ;A(7)<-C rrrr rrrr RRC r r(n-1)<- r(n) C 1 C<-r(0);r(7)<-C rrrr rrrr RLCA A(n+1)<-r(n) C 1 C<-r(7);A(0)<-C rrrr rrrr RLC r r(n+1)<- r(n) C 1 C<-r(7);r(0)<-C rrrr rrrr SHRA r A(n-1)<- r(n) A(7)<-C None rrrr rrrr SHLA r A(n+1)<- r(n) None 1 A(0)<- C bbb rrrr rrrr JBC r,b,addr If r(b)=0, jump to addr None 2 (*3) bbb rrrr rrrr JBS r,b,addr If r(b)=1, jump to addr None rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr (*3) JDNZ A,r,addr A<- r-1, jump to addr if not zero (*3) JDNZ r,addr r<- r-1, jump to addr if not zero (*3) JINZ A,r,addr A<-r+1, jump to addr if not zero (*3) JINZ r, addr r<- r+1, jump to addr if not zero (*3) None 2 None 2 None 2 None 2 12

13 Process Arithmetic kkkk kkkk JGE A,#k,addr Jump to addr if A>=k (*3) None kkkk kkkk JLE A,#k,addr Jump to addr if A<=k (*3) None kkkk kkkk JE A,#k,addr Jump to addr if A=k (*3) None rrrr rrrr JGE A,r,addr Jump to addr if A>=r (*3) None rrrr rrrr JLE A,r,addr Jump to addr if A<=r (*3) None rrrr rrrr JE A,r,addr Jump to addr if A=r (*3) None bbb rrrr rrrr BC r,b r(b)<- 0 None bbb rrrr rrrr BS r,b r(b)<- 1 None bbb rrrr rrrr BTG r,b r(b)<- /r(b) None rrrr rrrr SWAP r r(0:3)<- ->r(4:7) None rrrr rrrr SWAPA r r(0:3)->a(4:7) None 1 r(4:7)->a(0:3) rrrr rrrr CLR r r <- 0 Z rrrr rrrr TEST r Z<- 0 if r<>0 Z<-1 if r=0 Z rrrr rrrr RPT r Single repeat *(r) times on None 1 next instruction, *(r) is the content of register r rrrr rrrr ADD A,r A <- A+r C,DC,Z, rrrr rrrr ADD r,a r<-r+a (*4) C,DC,Z, kkkk kkkk ADD A,#k A<- A+k C,DC,Z, rrrr rrrr ADC A,r A<-A+r+C C,DC,Z, rrrr rrrr ADC r,a r<- r+a+c C,DC,Z, kkkk kkkk ADC A,#k A<- A+k+C C,DC,Z, 1 13

14 Move rrrr rrrr SUB A,r A<-r-A C,DC,Z, rrrr rrrr SUB r,a r<- r-a C,DC,Z, kkkk kkkk SUB A,#k A<- k-a C,DC,Z, rrrr rrrr SUBB A,r A<- r-a-/c C,DC,Z, rrrr rrrr SUBB r,a r<- r-a-/c C,DC,Z, kkkk kkkk SUBB A,#k A<- k-a-/c C,DC,Z, rrrr rrrr ADDDC A,r A <- C,DC,Z 1 (Decimal ADD) A+r+C rrrr rrrr ADDDC r,a R<- C,DC,Z 1 (Decimal ADD) r+a+c rrrr rrrr SUBDB A, r A<- C,DC,Z 1 (Decimal SUB) r-a-/c rrrr rrrr SUBDB r,a r<- (Decimal SUB) r-a-/c C,DC,Z rrrr rrrr MUL A,r PRODH:PRODL <- A*r None kkkk kkkk MUL A,#k PRODH:PRODL <- A*k None rrrr rrrr INCA r A<- r+1 C,Z rrrr rrrr INC r r<- r+1 C,Z rrrr rrrr DECA r A<- r-1 C,Z rrrr rrrr DEC r r<- r-1 C,Z rrrr rrrr MOV A,r A<-r Z rrrr rrrr MOV r,a r<- A None 1 100p pppp rrrr rrrr MOVRP p,r Register p<- Register r None 1 101p pppp rrrr rrrr MOVPR r,p Register r<- Register p None kkkk kkkk MOV A,#k A<- k None 1 14

15 Branch 110a aaaa aaaa aaaa SJMP addr PC<-addr; PC[13:16] unchangd None aaaa aaaa aaaa S0CALL addr [Top of stack]<- PC+1 PC[11:0]<-addr PC[12:16]<-0000 (*5) None 1 111a aaaa aaaa aaaa SCALL [Top of stack]<-pc+1 None 1 PC[12:0]<-addr PC[13:16] unchanged aaaa LJMP addr (2 words) PC<- addr None aaaa LCALL addr [Top of stack]<-pc+2 None 2 (2 words) PC<-addr (*1) TBRD i,r: r<- ROM[(TABPTR)]; i=00: TABPTR not change i=01: TABPTR<- TABPTR+1 i=10: TABPTR<- TABPTR-1 (*2) TABPTR=(TABPTRH: TABPTRM: TABPTRL) *Bit 7 of TABPTRH is used to select internal ROM space or external memory space. Bit7=0: internal ROM space Bit7=1: external memory space *Bit 0 of TABPTRL is used to select low byte or high byte of pointed ROM data. Bit0=0: Low byte of pointed ROM data Bit0=1: High byte of pointed ROM data *The maximum table look up space is internal 8Mbytes and external 8Mbytes. (*3) The maximum jump range is 64K absolute address. That is, it can only jump within the same 64K range, i.e., 0~64K or 64K~128K. (*4) Carry bit of ADD PCL,A or ADD TABPTRL,A will automatic carry into PCH or TABPTR. The instruction cycle of write to PC (program counter) takes TWO cycles. (*5) S0CALL addressing ability is from 0x000 to 0xFFF (4k space) 15

Microcontroller Intel [Instruction Set]

Microcontroller Intel [Instruction Set] Microcontroller Intel 8051 [Instruction Set] Structure of Assembly Language [ label: ] mnemonic [operands] [ ;comment ] Example: MOV R1, #25H ; load data 25H into R1 2 8051 Assembly Language Registers