CSE140 L. Instructor: Thomas Y. P. Lee. March 1, Agenda. Computer System Design. Computer Architecture. Instruction Memory design.

Transcription

1 CSE4 L Instructor: Thomas Y. P. Lee March, 26 Agenda Computer System Design Computer Architecture Instruction Memory design Datapath Registers Program Counter Instruction Decoder

2 Lab4 Simple Computer System Design A simple computer system with a minimal instruction set. Load/store data Addition Shift Left/Shift Right Compare AND (Mask) OR XOR NOT NOP Computer s Behavior 2

3 Computer Structure Block diagram view Processor address read data Program Memory Control Signals Control data conditions Data Path instruction unit - instruction fetch and interpretation FSM Execution unit and registers Computer Architecture 3

4 Computer Architecture (Cont.) Program Counter: The program counter is the address pointer for fetching the instructions in the instruction memory. Instruction Memory:The instruction memory can hold up to 6 instructions, each of which is 8 bits wide. Instruction Decoder: The instruction decoder is the control center. It specifies which arithmetic operation the datapath is going to execute, and takes care of the scheduling of registers. Datapath: The datapath is a pure combinational module which performs the useful computing. Registers: The registers, along with the instruction memory, provide operands for and receive the results from the datapath. Datapath module & registers perform each instruction and store the intermediate results. Control logic is the bridge between them. It compiles each instruction to the control signals needed by the datapath module and registers Clock Cycle and Program Execution. Each clock cycle, program counter will compute the address of the current instruction. 2. The instruction will be read into the control logic block and compiled to the corresponding control signals. 3. According to the control signals, datapath module will perform proper activities and get result ready to the input of registers. the result is written to the registers 4. When next clock cycle start, the program counter increment and the new instruction starts to run. 4

5 Instruction Sequencing Example an instruction to add the contents of two registers (R and R2) and place result in a third register (R3) Step : Read the ADD instruction from memory into an instruction register Step 2: decode instruction instruction in IR has the code of an ADD instruction register indices used to generate output enables for registers R and R2 register index used to generate load signal for register R3 Step 3: execute instruction enable R and R2 output and direct to ALU (datapath) setup ALU to perform ADD operation direct result to R3 so that it can be loaded into register System Architecture 5

6 Design of Instruction Memory Total 6 instructions in Instruction Memory, which need 4 bits address addr[3:] to access the program memory. Instr[7:4] control portion bits are sent to instruction decoder to decide the operation of the next cycle. Instr[3:], data portion bits are sent to the datapath for processing or stored in the registers. The datapath can also receive a 4-bits operand from the register files; and the results, including a 4-bit number and two flags (overflow and comparison). From the instruction set we find there are 8 arithmetic operations: ADD, SHIFT LEFT (SHL), SHIFT RIGHT (SHR), Mask, OR, XOR, NOT and COMP. During each cycle, we need to make a decision that which of the three 4-bit numbers is going to be stored back into the register files. Therefore, we will need a 3-bit control signal from the instruction decoder to do this task. SOURCE DESTINATION ADD Comp SHIFT LEFT (SHL) SHIFT RIGHT (SHR) MASK (AND) OR XOR NOT R,R2 R,R2 R, instr[3,2] R, instr[3,2] R,R2 R,R2 R,R2 R R3, Overflow Flag Comparison R3 R3 R3 R3 R3 R3 Datapath Logic Design R[3:] R2[3:] 4-bit SHIFT LEFT 4-bit SHIFT RIGHT 4-bit Adder 4-bit AND (Masker) 4-Bit OR 4-bit XOR 4-bit NOT 4-bit Comp sel[2:] - instruction decoder Overflow Mux dpath_out[3:] Comparison 6

7 Register File Logic Design Each Register should be enabled if and only if it s needed during the Next clock cycle Register Name Source Destination R memory or datapath datapath R2 memory datapath R3 datapath nowhere Overflow Flag Register datapath nowhere Compare Flag Register datapath nowhere Design of the Instruction Memory (ROM) Design ROM6x,Two Choices () Create 6x8 ROM block use Altera Megafunction (this has internal clock) (2) Use Verilog code provided How to Use Altera s Megafunction? Click on Tools-> MegaWizard Plugin Manager 7

8 Instruction Memory (ROM)- Cont. On MegaWizard Plugin Manager, choose Create a new custom megafunction variation Next on Plug-In Manager, select LPM_ROM, also, choose Verilog or VHDL, and type in your output file name Instruction Memory (ROM) (Cont.) Choose the same options to build LPM_ROM 6x8 as shown below 8

9 Instruction Memory (ROM) (Cont.) On the next screen, cchoose the same options to build LPM_ROM 6x8 as shown below Instruction Memory (ROM) (Cont.) On the next screen, choose the file which contains the program memory Content. Make sure you manually encode the instruction set into program memory 9

10 Instruction Memory (ROM) (Cont.) MegaWizard Plug-In Manager will create the ROM 6x8 for you when the Finish button is pressed. Instruction Memory (ROM) (Cont.) This is the instruction memory ROM 6x8, however, remember this ROM Component has build in clock.

11 Instruction Memory (ROM) (Cont.) Create ROM_Block.BDF file Instruction Memory (ROM) (Cont.) (2) Create ROM 6x8 using the following Verilog Code, notice this ROM does not include clock input module ROM6x8(addr, w); input [3:] addr; output[7:] w; wire [7:] w; endmodule assign w=(addr==4'h)? 8'h: (addr==4'h)? 8'h2: (addr==4'h2)? 8'h4: (addr==4'h3)? 8'h6: (addr==4'h4)? 8'h8: (addr==4'h5)? 8'ha: (addr==4'h6)? 8'hc: (addr==4'h7)? 8'he: (addr==4'h8)? 8'hc: (addr==4'h9)? 8'hc2: (addr==4'ha)? 8'hc4: (addr==4'hb)? 8'hc6: (addr==4'hc)? 8'hc8: (addr==4'hd)? 8'hca: (addr==4'he)? 8'hcc: (addr==4'hf)? 8'hce: 8'h;

12 Registers Block Diagram Instruction Decoder (Control Logic) Design Instruction Decoder (control logic) Input: data bits from program memory. Output: control signals to registers and datapath module A truth-table mapping INIT instruction code, clr input to registers should be, all other control signal should be. 2

13 Instruction Decoder (Control Logic) Design Ins[7] Ins[6] Ins[5] Ins[4] R_sel R_en R2_en R3_en OVL_en COMP_en For Combinational Logic Design, refer to Lab presentation Program Counter Design Several ways to design your own Program Counter, make sure your counter has clock input, clock enable input, and asynchronous clear reset, the output is 4-bit bus, which should connect to the address of ROM 6x8 Use Altera Build in Megafunction LPM_COUNTER Or, build your own counter If you use ROM 6x8 has clock input, make sure your clock input is not the same clock as program counter, insert a NOT gate between clock source and program counter 3

14 Simple Test Program and Simulation Init Move Move2 NOT STORE XOR SHR XX Move ADD Comp NOP An Example of Simulation Result: 4