CSE 140L Spring 2010 Bonus Final

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1 CSE 140L Spring 2010 Bonus Final Logistics for Bonus Final: This final should be done in individually. Use Xilinx tools version What is due: - Report: o Submit a single report in.pdf form via to the TAs at cse140lsp10@gmail.com by the end of your scheduled final exam time. The subject line of the should read "CSE140L Bonus Final Submission YourLastName-FirstName. s sent after the due date will not be accepted. Please include in the report all your Verilog code, diagrams, simulation results as requested in the question. Turn in only one PDF file containing all the solutions with your Full Name and PID on the first page of the report. o Include all the necessary files for us to test your designs in CSE140L Bonus Final Files - YourLastName-FirstName.zipped file that you attach to your . If all files are not present or don t run, the bonus grade will be zero. Bonus Lab Specifications: Design of a more realistic CPU This is an extension to Lab4. Do the following enhancements to the cpu design in lab4: Datapath: Adder, subtractor and comparison operations should be implemented without using + (add operator), - (subtraction operator) and <= (less than or equals or >=) operators. These 3 operations take one cycle each. Multiplication should be implemented using a sequential multiplier (without using * operator). Similarly, division should be implemented using a sequential divider (without using / or % operator). Both multiplication and division should take exactly 4 cycles each. Data RAM: Both read and write operation from/to RAM now take 10 cycles each. IROM: IROM size should be increased from 32 to 128 locations.

2 Instruction decoder: You need to add four extra instructions. 1. A STALL instruction, which stalls the CPU for one cycle (Opcode is decimal 16). 2. A second comparison instruction for doing greater or equals (>=) comparison (Opcode is decimal 17). 3. Load_R2 aaaa. Load memory value from location whose address is aaaa to R2 (Opcode is decimal 18). 4. Store_R4 aaaa. Store R4 to memory location whose address is aaaa (Opcode is decimal 19). Program counter: Redesign the branch instruction as follows: Branch now takes a 4-bit immediate value and pads 3 b000 at the end (as the least significant bits). The program counter now jumps this 7-bit address. (This way you will able to jump to locations in the whole length of IROM). Eg. BR 0111 PC jumps to if the previous COMP operation is true. Assembly code: You need to write the ROM code for min square error calculation and average square error calculation (you must use loops), do the simulation and submit results similar to lab4. Use the same RAM data as given in lab4 for both of these tasks. Report should include: A. Your complete Verilog code for the CPU with all the modules. B. Assembly code, IROM code for min square error calculation (do not unroll the loop). Simulation results for the same. C. Assembly code, IROM code for average square error calculation (do not unroll the loop) and simulation results for the same. D. In addition, TAs will use additional ROM code for testing your design, so you want to make sure your design works correctly for each and every instruction.

3 Lab 4 question is repeated here for your convenience: The CPU consists of a program counter (PC), a datapath unit, an instruction decoder (ID), a register file, an instruction ROM (IROM), a 16 location 4-bit wide memory and an ALU. The instruction ROM can hold 32 instructions. There are five 4-bit registers R1, R2, R3, R4 and R5. The CPU reads the 8-bit instruction from read-only IROM, and instruction decoder decides what kind of operation the datapath should do. Use the starter files provided to implement your CPU design. Make sure you don t edit the IO ports of the modules we provided. The instructions the CPU can perform are provided below. Table 1. Instruction Set Command 4-bit opcode 4 bit data Description Initialize Initialize all registers: R1=R2=R3=R4=R5=0000 And comparison output. Move R aaaa Put aaaa value in register R1 Move R aaaa Put aaaa value in register R2 Move R3_R XXXX Take previous result in R3 and store into register R1 Add Add R1 and R2 and store result in R3. Store overflow in R Add R5 and R2 and store result in R3. Store overflow in R4. Multiply 0101 XXXX Multiply R1 and R2, put the least significant 4-bit result in Compare 0110 R3 and MSB in R Compare the contents of R1 and R2. The flag bit is true iff R1 R Compare the contents of R5 and R2. The flag bit is true iff R5 R2 Branch 0111 aaaa Jump to instruction aaaa if the compare flag bit is true Divide 1000 XXXX Divide R1 and R2, put the quotient in R4 and remainder Subtract 1001 in R Subtract R2 from R1 (R1-R2) and store result in R3. Overflow should be in R Subtract R2 from R5 (R5-R2) and store result in R3. Overflow should be in R4. Move R3_R XXXX Take previous result in R3 and

4 store into register R2 Load R Memory address Load memory value to R1 Move R3_R XXXX Take previous result in R3 and store it in R5 Store R Memory address Store R3 to memory location. Move R aaaa Put aaaa value in register R5 LDR1ID 1111 XXXX Load R1 Indirect. R1 gets memory value whose address is stored in R5 1. Program Counter (PC) As mentioned above, the mini CPU is limited to 32 instructions. This is controlled by the PC. The PC increments by 1 every clock cycle. So the PC goes up to 31. At 31 the PC will stop, thus essentially shuts down the CPU. In case of branch, the PC should be able to accept a number aaaa from the last 4 bits of instruction as input and set the program counter value equal to 0aaaa (0 value for the fifth most significant bit, since instruction opcode is 5bits wide). For example, if the instruction is branch to address 0011, the CPU will first check the comparison bit. If it is high, the program counter will be set to 00011, and continue on from there. The PC interface is given in Table 2. Table 2. PC Interface Clk Input Clock Signal Enable Input Enable Signal Reset Input Reset signal PC increments by 1 when enable is 1 PC becomes zero when clear is 1 Load Input When load is 1, PC load external data via data input [3:0] data Input The data that will be loaded to PC when load is 1 [4:0] q Output PC value

5 2. Instruction ROM (IROM) This module connects to the program counter and outputs the instruction corresponding to the current program cycle. It basically is a table that stores an instruction at a given address. A program is a sequential list of instructions, and these instructions are stored in the instruction ROM in order. Thus, at address 0, the first instruction of a program is stored, and so on. The ROM reads in the current program cycle from the program counter, reads the address that the program cycle points to (so if the current program cycle is 3, then the ROM will read address 3), and will output the corresponding instruction. Remember, in our machine, instructions are 8 bits long, with the first 4 bits being the instruction type, and the last 4 bits being data. Because our program counter stops at 31, you can store up to 31 instructions in your instruction ROM. We will give you a sample IROM. The IROM interface is given in Table 3. Table 3. IROM interface [4:0] addr Input Address signal [7:0] inst Output Instruction signal 3. Instruction Decoder This module decodes the instructions by reading in the first 4 bits of the instruction (which correspond to the instruction type), decoding it, and outputting all the control signals needed to control the rest of the CPU. This instruction decoder can be thought of as the brain of the CPU. For example, the add instruction is The instruction decoder sees this, and based on the 0100, will output the correct control signals to control the other modules, such as the register file, the datapath, etc. In the case of an add instruction, the instruction decoder will tell the register file that R1 and R2 need to be outputted and R3 needs to be written into, and will also tell the datapath that we need to add R1 and R2 together. You need to define the interface of ID by yourself. 4. Register File This module contains the registers that will be used to store the data that we want to operate on. We want five 4-bit registers, R1, R2, R3, R4 and R5. Each register is made up of D flip flops. It will receive as input the 8-bits output from the datapath and the least significant 4 bits of the actual instruction (this corresponds to the 4-bit immediate value of a move instruction, in case the instruction was a move command). It also has many control signals, such as which register to move the values to, or which value to use (either the datapath output for the case of add or the 4-bit instruction value for a move). It outputs all five register values (yes, this means that every clock cycle, all five register values will be output). It also outputs the comparison result that it gets from the datapath. You need to define the interface of register file by yourself.

6 5. Datapath unit It takes in as inputs the two 4-bit values to be operated on, which are R1 and R2 (so this means our register file is directly connected to the ALU). It also has one 2-bit control signal input ("operation select"), which tells the ALU which operation to perform on the two values. It also takes in the 4-bit immediate value of the instructions since few instructions behavior depend on these values (for instance, SUB does R3=R1-R2 if immediate value is 0001 and R3=R5-R2 if the immediate value is 0101). It outputs the corresponding 8-bit result. For example, if R1 is 3, and R2 is 2, and the operation is add, then the output for the ALU will be 5. If the operation is multiply, then the output will be 6. Note that the output is also a 8-bit value. For Division put the quotient in R4 and the remainder in R3. Another output 1-bit comparison result that is used for the compare instruction. Both these values are fed into the register file. This module should be the easiest to implement. There are only several ALU operations you need to support: addition, multiplication, subtraction, division and compare. The datapath interface is given in Table 4. Table 4. Datapath interface [3:0] r1 Input First operand [3:0] r2 Input Second operand Op [7:0] dp_out Input Output Operation signal Datapath should do addition when op is 0. Datapath should do multiplication when op is Datapath 1. result output Comp Output Comparison output 6. Top module In the top module, all instances are provided and you need to hook them up properly. Simple combinational logics are necessary for some signals. The IO specification of the top module is as follows:

7 Table 5. IO specification of the top module cpu_clk Input System clock signal Clear Input Clear signal [4:0] inst_addr Output The address of the instruction being executed. Instruction Output The instruction being executed [3:0] r1 Output The value of R1 [3:0] r2 Output The value of R2 [3:0] r3 Output The value of R3 [3:0] r4 Output The value of R4 [3:0] r5 Output The value of R5 [7:0] dp_result Output The value of the 8-bit datapath output dp_comp_out Output The comparison result of datapath 7. Data RAM: This module serves as an on-chip RAM for data. It has 16 locations and each location is 4- bits wide. Its interface is given in the starter file. Design the RAM such that both load and store take one cycle each. The first 10 (from 0 to 9) memory locations are initialized in the DRAM interface given to you with values which you can use to compute both Minimum and Average Mean Square Errors. Table 6. RAM interface ram_clk input Ram clk to be synced with cpu clk. ram_en Input Ram enable signal ram_we Input 1 for writing to ram and 0 for reading from ram [3:0]data_addr Input Address port [3:0]ram_data_in Input Data ports for writing data to RAM [3:0]ram_data_out output Data port for reading data from RAM

8 CPU Task 1: Implement all modules needed to be able to run any set of assembly instructions using your CPU design. Provide results using sample code we provided for you below. The following assembly code loads ten data values from RAM memory one at a time. It computes the minimum of the square errors relative to a particular value (use 5 for this value). Output = minimum {( X i value) 2 }. Where i=number of values (in this case 0..9) Make sure you initialize the 0-10 RAM locations as given in the starter file. Table 7. Sample code IROM Sample Code (Commented, Optimized & updated): Addr Inst Description 0 INIT Initialize all registers 1 MOVE_R2 #15 Initialize R2 with decimal 15 2 MOVE_R5 #10 Initializes a count value. 3 LD_R1 [12] R1 gets the old min square value from [12] {except for the very first iteration} 4 COMP_0001 Compares stored value with R2 5 BR 9 If R1 less than R2, don t over write [12] 6 MOVE_R1 #0 Upto 8: Else copy R2 to [12] 7 ADD_ STORE_R3 [12] [12] gets the new minimum square value 9 LDR1ID Load R1 with mem[r5] 10 MOVE_R2 #1 Upto 12: Decrementing the count value 11 SUB_ MOVE_R3_R5 Count gets the decremented value. 13 COMP_ BR 0 Goto INIT if count exhausted. 15 MOVE_R2 #5 Till 19: Computing square error for one sample 16 SUB_ MOVE_R3_R1 18 MOVE_R3_R2 19 MUL Square error computed 20 MOVE_R1 #0 R1 gets #0 21 MOVE_R3_R2 R2 gets the square error value. 22 COMP_0001 Compare R1 and R2. 23 BR 3 Branch is always taken. Make sure your RAM location 12 has an initial value of (decimal) 15 before you execute the above program.

9 When you do the demo, be ready to show results of run of this sample code. In addition, TA may provide additional assembly code for testing your design, so you want to make sure your design works correctly for all instructions. CPU Task 2: Find the average square error by changing the code provided above. The initial statement in the RAM module of the starter file has N=10 values stored in locations 0 to 9. You need to compute the average of the square errors of these values with respect to the given value=5 using assembly; the ASE is defined as follows: N { (X i value) 2 }/ N = Average Squared Error i=0 ****Good Luck******

CSE 141L Computer Architecture Lab Fall Lecture 3

CSE 141L Computer Architecture Lab Fall 2005 Lecture 3 Pramod V. Argade November 1, 2005 Fall 2005 CSE 141L Course Schedule Lecture # Date Day Lecture Topic Lab Due 1 9/27 Tuesday No Class 2 10/4 Tuesday