Section 6. Memory Components Chapter 5.7, 5.8 Physical Implementations Chapter 7 Programmable Processors Chapter 8

Transcription

1 Section 6 Memory Components Chapter 5.7, 5.8 Physical Implementations Chapter 7 Programmable Processors Chapter 8

2 Types of memory Two major types of memory Volatile When power to the device is removed the contents in memory are lost Non-Volatile Contents in memory remain if power is removed

3 Volatile memory Usually made form Random Access Memory RAM Simple RAM First In First Out FIFO. Last In First Out LIFO. Dual-port RAM two independent parallel accesses to memory.

4 Volatile Memory RAM has further subdivisions Static RAM Write data at an address location and the memory doesn't change until the next write at same address. Dynamic RAM Same as Static RAM except memory refresh is required. Data in memory decays over a short time and must be refreshed (write the same value again).

5 Volatile Memory Static RAM symbol

6 Static RAM The output is usually a three-state output. Sometimes the Data in and Data out share the same I/O pins. CE controls the output and writing. To write The address and data must be set followed by the CE and R/W' signal set to false. To read The address and CE must be true.

7 Dynamic RAM Similar to Static RAM More controls for refresh Address is multiplexed between row and column Data in and Data out share the same pins. Cost and package size is a major advantage.

8 Non-Volatile Memory Read Only Memory Similar to SRAM but no data input or write signal. Programmable ROM Requires special programming devices. Erasable PROM Has a window to erase with UV light Electrically EPROM Can be programmed in circuit. Slow write speed.

9 Non-Volatile Memory ROM's can be used for implementing logic. Address in, data out. Looks like a huge truth table No logic optimizations Programmable Array Logic PAL Programmable Logic Array PLA Some have a register built-in.

10 Creating a larger memory Memory can be used to create larger memory. Increase the number of words Increase the number of bits per word

11 2Kx8 SRAM from 1K x 4 SRAMs

12 Mixed SRAM and ROM Parts of the address range can be ROM while other parts can be SRAM. Design a 4kx8 mixed ROM and SRAM memory. The least significant 1kx8 is ROM while the most significant 3kx8 is SRAM. Use 1kx8 ROM and SRAM devices and the minimum additional combinational logic.

13 Physical Implementation After circuit design the next step is to create a real circuit. There are multiple ways to implement a design. Each has its pros and cons. Full-Custom ICs Semicustom (Application-Specific) IC ASICs Off-the-shelf Programmable IC FPGA Other Off-the-shelf IC types

14 Full-Custom ICs An integrated circuit built to implement the specific desired circuit Takes months to develop Error-prone Expensive Small size Low power High performance

15 Application-Specific IC ASICs Reduced NRE compared to Full-Custom ICs Standard Cell Gate Arrays, Structured Cell, platform ASIC Slower than Full-Custom More power that Full-Custom

16 FPGAs Fast turn around time No large NRE costs Higher power requirements Larger size Performance not as good as Full-Custom ICs

17 FPGAs Combinational logic is implemented using Look-Up-Tables.

18 FPGAs FPGAs contain a large number of small LUTs See Figure 7.21, examples 7.7 and 7.8

19 FPGAs Programmable interconnects (Switch Matrices) See figure 7.26 Configurable Logic Block (CLB) See figure 7.28 Implement a 2-bit Up/Down counter with reset using a CLB

20 Overall FPGA Architecture A grid of CLBs and Switch Matrices Programming an FPGA is done as a large serial shift register. Different FPGA devices will have their own bit shift pattern. See Figure 7.31

21 Off-The-Shelf Logic 7400 series ICs When you need a simple logic gate or common logic function. Programmable Logic Device (PLD) See PAL and PLA fuse maps.

22 Programmable Processors GPP has: Datapath Register File ALU Control Unit Program Counter PC Instruction Register IR Instruction Memory Data Memory

23 Control Unit Interprets Instruction in IR Instructions for this machine are all the same size in bits. An instruction specifies an operation, and maybe operands, and result. Operands and result are from/too the RF. Operations includes load/store.

24 Control Unit Fetch/Execute cycle Fetch instruction from I memory Decode instruction Execute instruction Cycle may take multiple clock cycles PC starts at a known address (0 for this machine) PC increments to next instruction (usually)

25 Instruction Set Instruction is 16-bits Opcode is IR<15..12> Load and Store register address is IR<11..8> D Memory Address is IR<7..0> Operand 1 register address is IR<7..4> Operand 2 register address is IR<3..0>

26 Instruction Set Machine Code and Mnemonics MOV destination, source One address is a register address the other is a D memory address. Load and store use the MOV mnemonic Register address always starts with R. ADD result, operand1, operand2