Week1. EEE305 Microcontroller Key Points

Transcription

1 Week1 Harvard Architecture Fig. 3.2 Separate Program store and Data (File) stores with separate Data and Address buses. Program store Has a 14-bit Data bus and 13-bit Address bus. Thus up to 2 13 (8K) 14- bit instructions can be addressed. Data store Has an 8-bit Data bus and a maximum of a 9-bit Address bus. Thus up to 512 bytes of data can be addressed. Input and Output ports are part of this address space. Locations in the Data store are known as Files. Fetch and Execute Fig. 3.4 Concept of fetch and execute cycles. Parallel operation in Harvard architecture. Role of Program Counter, Pipeline, Instruction decoder, ALU and Working register. Each location in the Program store holds one 14-bit instruction. 1

2 Software Is aware of the principle of a program as a series of instructions. Understands the binary structure of a PIC instruction. Can read an instruction set for the mid-range PIC family Knows the purpose of the C and Z flags in the Status register (File 3) The Code Translation Process Figs. 8.1, 8.2, 8.5, 8.6, 8.7 Understands the function of an Assembler is to convert from Source code to Machine code. Appreciates the advantages of the use of Assembly-level source code as the coding medium as against raw machine code: Readibility: Errors: Mnemonics, labels, comments Less error prone, easier to spot errors Maintainability:Easier to modify and add extensions Reusability: Easier to use routines for more than one project 2

3 Understands the reason for and use of an Integrated Development Environment (IDE) in coding and testing software. Can use the MPLAB IDE to: Edit and save simple assembly-level programs. Make a Project. Assemble and correct syntax errors. Use the Simulator with a Watch window to Single-step through the program and monitor program variables. Set a Breakpoint and Animate the program execution. 3

4 Week2 PIC16F84 Architecture Fig. 4.1 Fetch Unit: Deals with fetching the appropriate 14-bit operation code from the Program store. 13-bit Program Counter and its relationship with the PCL (File 2) and PCLATH (File h 0A ). 2-stage pipeline leading to the Instruction decoder. 8-deep Stack. Figs 3.7, 4.2, 4.8. Execute Unit: Carries out commands as directed by the Execution circuitry. Loads and Stores 8-bit bytes from/to the Data store. The ALU carries out the logic/arithmetic in conjunction with the Working register and Status register (the Carry/Not Borrow and Zero flags). Data store is organised as two banks of up to 128 bytes each. The programmer can switch between them using the RP0 bit in the Status register. Figs 4.5, 4.7 4

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6 Instruction Set Chapter 5 Move Table 5.1 Load from Data store to W e.g. movf h 20,w Load constant into W e.g. movlw 6 Store W to Data store e.g. movwf h 21 Swap file nybbles e.g. swapf h 30,f Key concepts: TIP movf affects the Z flag and thus movf **,f is a useful way of Testing if File** is all Zero ( ). Non of the other Move instructions affect flags. 6

7 Arithmetic Table 5.2 Addition (Note use of W or f as destination) e.g.: Clear addwf h 20,w ; W <- W+[Fh 20 ] addwf h 20,f ; [Fh'20'] <- W+[Fh'20'] addlw 6 ; Add literal 6 to W (max value 255) addlw -1 ; Subtract 1 from W (i.e. decrement W) TIP: DO NOT USE SUBLW to subtract a constant clrf h'20' ; Clears the specified file reg clrw Increment and Decrement incf ; Clear W h'20',f ; Increment the contents of File h'20' incf h'20',w ; Put the incremented value of the contents of File h'20' into W. File h'20' remains unchanged 7

8 Subtract e.g.: subwf h'20',w ; W <- [Fh'20']-W subwf h'20',f ; [Fh'20'] <- [Fh'20']-w Bit Banging bcf bsf h'20',7 ; Clears bit 7 of File h'20' h'20',4 ; Set bit 4 of File h'20' Program Counter Table 5.4 Jump to an instruction somewhere in Program store goto goto h 050 ; Jump to the h 050 FRED ; Jump to instruction labelled FRED Bit Test and Conditionally Skip btfsc h'20',6 ; Skip if bit6 of File h'20' is clear(0) btfss h'20',4 ; Skip if bit 4 of File h'20' is set (1) Increment/Decrement File and Skip on Zero incfsz h'20',f ; Increment File h'20' & skip if all zero decfsz h'20',f ; Decrement File h'20' & skip if all zero 8

9 Week3 Indirect Addressing Fig. 5.2 The datum s location in the Data store is pointed to by the File Select Register (FSR = File 04). The Indirect mechanism is triggered by specifying the phantom File register INDF (INDirect File register at File 00). For example: clrf 0 ; Actually clears the file POINTED TO by the FSR! So if the contents of the FSR happened to be h'20' at this time, then File h'20' would be the location cleared; not File 00. Logic/Shifting Instructions NOT (1 s complement) Inverts all bits in the specified File; e.g.: File h'20' comf h'20',f File h'20' AND (Used to clear bits) ANDs all bits in the specified File; e.g. to clear the lower four bits of the Working register leave the upper nybble unchanged: W andlw b W Anding with 0 always gives 0, ANDing with 1 gives no change. 9

10 E.g. to zero the upper two bits of File h'20': File h'20' movlw b ; Mask byte andwf h'20',f ; Zero bits File h'20' OR-Inclusive (Used to set bits) Inclusive-ORs all bits in the specified File; e.g. to set bit 7 of the Working register: W iorlw b W e.g. to set bits 2 and 3 of File h'20' File h'20' movlw b ; Mask iorwf h'20',f ; Zero bits File h'20' Inclusive-ORing with 1 always gives 1, with a 0 gives no change. 10

11 OR-eXclusive (Used to toggle bits; also to check two numbers for changes and to generate parity) Exclusive-ORs all bits in the specified File. e.g. to toggle bits 7 & 6 in the Working register: W xorlw b W e.g. to toggle bits 0 & 1 of File h'20': File h'20' movlw b ; Mask byte xorwf h'20',f ; Zero bits File h'20' exclusive-oring with 1 always toggles, with a 0 giving no change. 11

12 Rotate (Shift) Used to shift a File left or right one place in conjunction with the Carry flag. e.g. to rotate the contents of File h'20' right one place: C 1 File h'20' rrf h'20',f ; Rotate Note: To do a plain shift (with a 0 coming in from the right), then clear the Carry bit before doing a Rotate; e,g,: bcf STATUS,C ; Clear the carry bit rrf h'20',f ; Do the shift Note: rlf rotates left but otherwise is the same as rrf Note: If a multiple-precison shift (> 1 byte) is required then clear the Carry flag and then rotate each file in turn; e.g. to shift left a 2-byte object in File h 22 & h 23 : bcf STATUS,C ; Clear Carry rlf h 22,f ; Shift the Least Significant Byte rlf h 23,f ; Shift the Most Significant Byte C 0 File h'20'

13 Comparing two Numbers If you want to know if your byte in the Working register is HIGHER THAN, EQUAL TO or LOWER THAN either the contents of a File register or a constant, then subtract the two numbers. If they are the same then the outcome will be zero (Z flag will be 1). If the first number is higher or the same as the second then there will be NO borrow (Carry flag will be 1). If the second number is higher then there will be a borrow (Carry flag will be 0). E.g. to compare a byte in W with that in File h'20': subwf h'20',w ; Contents of W is [File h'20'] - W then: IF f is Equal to W outcome is zero: Z flag is 1 IF f is Higher or Same as W then f W will not generate a borrow: C = 1 IF f is Lower Than W then f W will generate a borrow: C = 0 TIP TIP Remember that the Carry flag is a NOT Borrow flag after a subtract. 13

14 Parallel ports Chapter 11 Define a port as a way into or out of a digital system A parallel port enables the program to read in or write to a number (typically up to 8) of pins at one time. Conceptually a parallel I/O port can be considered as a File connected to pins on the IC; as below: 14

15 A pin may be configured by software to be either an Input or Output. Pins are labelled (e.g. in Port B) as RB7 thru RB0 corresponding to bits 7 thru 0 in File 06. A pin set-up as an input reflects if the voltage is low (logic0, typ zero volts) or high (logic1, typ +5V) at the appropriate bit in the port File A pin set-up as an output will go high or low following the appropriate bit in the port File. Each pin may be individually set to input or output with the port s TRIS register in Bank1 according to the scheme: TRISX bit n = 1 TRISX bit n = 0 Pin n in Port X is Input Pin n in Port X is Output On Reset all TRIS bits are set to 1 and therefore all pins are inputs. 15

16 Example: To pulse pin RA0 low:high twice whenever pin RB7 goes high. include p16f84.inc bsf STATUS,RP0 ; Change to Bank 1 movlw b ; Prepare to set pin RA0 to Output movwf TRISA movlw b ; Set up PortB as IPs (default on Reset) movwf TRISB bcf STATUS,RP0 ; Back to Bank 0 ; bcf PORTA,0 ; Make pin RA0 low LOOP btfss PORTB,7 ; Skip if RA7 is high goto LOOP ; Keep looking bcf PORTA,0 ; RA0 goes low bsf PORTA,0 ; and high bcf PORTA,0 ; and low bsf PORTA,0 ; and high Skip if high 16

17 Week4 Subroutines Chapter 6 The modular nature of software. The call-return mechanism and the use of the Stack to automatically save the address of the jumping-off point (i.e. the next value of the PC). Subroutine return call call Main routine Subroutine instructions call, return in Table Use of the Stack to save jumping-off points. Passing parameters back and forth to subroutines. 17

18 Rules for calculating execution time of an instruction: A cycle is ¼ of the crystal frequency; e.g. 4MHz gives a 1µs delay. Normal instructions take one cycle Instructions that cause the Program Counter to skip or jump take two cycles; e.g. goto, call, return, btfss when a skip occurs. Single loop delay subroutine giving a fixed 1ms 4MHz. Knows how to calculate the value of the constant loaded into W and decremented. Double loop delay subroutine based on an extra loop of 100 passes with the 1ms loop as a core, giving a 100ms 4MHz Variable delay subroutine with three nested loops, giving K times 100ms, where K is passed in the Working register Binary-Coded Decimal representation of decimal numbers but in binary; for example decimal 63 (which in natural binary is ) can be represented as (i.e. 6 3). 18

19 Look-up tables implemented as a series of retlw instructions (RETurn with Literal in W). Implemented by adding the number in the Working register (n) to the low byte of the Program Counter (PCL) to force a jump of n instructions to return with the appropriate constant: For example: LOOK_UP addwf PCL,f ; Add n to the low byte of PC retlw b ; Return pattern if n = 0 retlw b ; Return pattern if n = retlw b ; Return pattern if n = 2 retlw b ; Return pattern if n = 3 retlw b ; Return pattern if n = 4 retlw b ; Return pattern if n = 5 retlw b ; Return pattern if n = 6 retlw b ; Return pattern if n = 7 ; etc If, say, the contents of W were 04 on entry; then the addwf instruction would add 04 to the Program Counter, which is already pointing to the first retlw instruction, causing it to skip down to the fifth retlw instruction. This causes a return from the subroutine with the value b in W. 19

20 Week 5 Interrupt Handling Chapter 7 Interrupts are events which can come from an event from either: Outside the device (e.g. an object breaking a light beam) Inside via a Peripheral module wanting service (e.g. a Timer overflowing) Interrupts can be disabled completely by clearing the GIE bit in the INTCON register. Each particular interrupt can be disabled by clearing its own local Enable (Mask) bit. On reset all interrupt Mask bits are cleared. Each source of interrupts has its own Interrupt Flag which is set when a request is made; even if that interrupt is masked out. 20

21 When an enabled interrupt request arrives, the PIC will respond after the current instruction has been completed: The GIE General Interrupt Enable bit is cleared to lock out any more interrupts. A copy of the PC is made on the Stack. The program will jump (vector) to location h 004 in the Program store in which the programmer should have placed a goto instruction to the start of the Interrupt Request Routine (a type of subroutine used to service interrupts. The ISR should save W and STATUS and determine the source of the interrupt by checking the appropriate Interrupt flags. Such flags should be cleared before completing the ISR. At the end of the ISR any saved system Files should be retrieved and the instruction retfie (RETurn From Interrupt and Enable further requests) used to return to the interrupted instruction and set GIE 21

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23 Programming in CCS C Chapter 9 Structure of a C program Use of #include <16f84.h> header file Object definition and types Unsigned byte sized int unsigned 16-bit word-sized long Simple arithmetic in C The process of simulation C code with MPLAB Viewing decimal objects in Watch window of byte (int) and word (long) objects Names of non-global objects prefixed by function name; e.g. main.count if and if-else decisions while and for loops 23

24 C Function declarations Passing parameters to functions Definition of a function Returning a parameter from a function Global variables used by functions Binary to BCD conversion The #byte directive used to name specific File addresses; e.g. #byte FRED = 0x20 /* Name File h 20 as FRED */ The#bit directive used to name specific bits in a specific File; e.g. #bit FRED.7 = RELAY /* Bit7 of File h 20 is called RELAY*/ Example: To turn on the Relay (logic 1) for 6 seconds then turn it off. Assume an 8MHz crystal for the delay functions: #include <16f84.h> #delay (clock = ) /* Tell compiler 8MHz crystal */ main() { RELAY = 1; /* Turn it on (logic 1) */ delay_ms(6000); /* For 6 seconds */ RELAY = 0; /* and off */ } where delay_ms() is a built-in CCS C function 24

25 Can compare high-level C coding versus assembly language. Advantages of High-level code More compact and therefor more productive to code Syntax is more oriented to human problem solving, which makes it easier to document, debug, maintain and modify/extend Easier to port to different hardware platforms (processors), giving a longer productive life Better economics as being platform independent gives a larger customer base Disadvantages of High-level code compared to assembly Is less space efficient than assembler languages Runs more slowly Compilers cost more than assemblers Not the same intimate relationship to the hardware, so debugging interface with hardware can be more convoluted 25

26 Example: Example: To pulse pin RA0 low:high twice whenever pin RB7 goes high using CCS C (see Slide 16 for assembly version). #include <16f84.h> #byte PORTA = 05 /* PORTA is at File 05 */ #byte PORTB = 06 /* PORTB is at File 06 */ #bit OUT = PORTA.0/* Bit RA0 is to be used an input */ #bit IN = PORTB.7/* Bit RB7 is used as an input pin */ main() { set_tris_a(0xfe); /* Make pin RA0 and Output b */ Set_tris_b(0xFF); /* and all PORTB pins input */ while(in = 0) {;} /* Do nothing while RB7 stays low */ OUT = 0; OUT = 1; /* ELSE pulse RA0 low:high */ OUT = 0; OUT = 1; * and again pulse low:high */ } 26

27 Week 6 Watchdog timer (wdt) Fig Function: To automatically reset the microcontroller if it malfunctions (typically due to noise or software bug) How does it work? wdt is a (nominal) 18ms pulse generator; i.e. once started at Reset, it times out (oscillates ) with a period of about 18ms: It is possible to set the wdt by using the clrwdt instruction. Provided that the program does it more often than every 18ms the wdt will never timeout and the MCU will not reset If 18ms is too short it may be extended by selecting the Post/Prescaler using the PSA (PreScale Assign) in the OPTION_REG. The ratio can be selected by programming the PS2:1:0 bits at the start of the program to up to a factor of 128. NOTE: This scaler is shared between the wdt and TIMER0 Fig If the wdt does timeout it will clear the TO bit in STATUS, so the program can tell that a wdt reset occurred 18ms Reset MCU 27

28 config #fuses _wdt_on/_wdt_off wdt/nowdt ; Assembly /* CCS C */ 28

29 Timer 0 (Real-Time Counter/Clock) Fig 13.3 Function: To count either internal clock pulses or external events (pulses) at pin RA4/T0CKI How does it work? TMR0 is an 8-bit up counter at File 1. It can be Read from or Written to If the TMR0 counter overflows; e.g. FC FD FE FF 00, it will set the T0IF flag (Tmr0 Interrupt Flag) in the INTCON (INTerrupt CONtrol) register. This bit may be continually checked (polled) or else may be used to action an interrupt The source of counting pulses may be either the RA4 pin (called T0CKI, for Tmr0ClocKIn) or from the crystal clock 4 (e.g. 1µs for 4MHz) using the T0CS (Tmr0 Clock Select) bit in the OPTION_REG If external from T0CKI then the active edge or may be selected using the T0SE (Tmr0 Set Edge) bit in the OPTION_REG If bit PSA = 0 the Prescaler is chosen for the Timer rather than for the Watchdog timer. In this situation the clocking rate may be divided down as selected using the three PS[2:0] bits in OPTION_REG 29

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31 Week 7 (Chapter 14) Most physical signals (e.g. music, video) are analog; computing machines are binary digital. Analog to digital conversion is the process of converting smooth continuous signals to a series of binary numbers. The process is characterised as: Sampling: Converting the signal on a regular basis at discrete points in time; for example a music CD contains digitized samples taken at a rate of 44,100 samples per second. Shannon s sampling theory gives a minimum sampling rate of twice the highest analog frequency component. Resolution: The number of levels and hence binary bits each sample is converted to; in general 2 n, where n is the number of bits: For 8 bits (telephone) the resolution is 256 (2 8 ) levels; for 16-bit conversion (e.g. CD music) the resolution is 65,536 (2 16 ) 31

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33 Converting from digital to analog can be done by using a weighted network of resistors or capacitors with each bit contributing a current or voltage going up in powers of two. The circuit below is only useful where there are few bits, as a wide range of precision resistors is hard to implement. Other networks with only two values are resistors or capacitors are normal. 33

34 Converting from analog to digital is more complex. There are many techniques, of which a few are: Ramp generation: Here a voltage charges up a capacitor and the time taken is inversely proportional to the size of the analog voltage. The analog voltage causes a current to flow to the amplifier which charges up the capacitor giving a ramp. By measuring the time to reach a threshold voltage we can convert time to a digital number. Ramp converters are slow and not very accurate. Commercial versions are called dual-ramp and they measure the time for a precision reference voltage to charge up and then compare this to the time taken by the input discharging back to zero. 34

35 Counter ADCs use a binary counter with a DAC module to generate a staircase voltage. Using an analog comparator to compare this ramp with the input voltage gives a signal when equality is reached. The value of the counter is our digitized number. Counter ADCs are relatively slow but comparatively simple to construct. 35

36 Successive-approximation ADCs replace the counter by intelligent digital circuitry which tries each bit in turn, beginning with the highest bit. If the resulting analog voltage is too bit it is returned to 0 else it remains at 1. For an n-bit converter, only n tries are needed instead of 2 n for a counter type. Successive-approximation ADCs are medium speed and the most common. 36

37 The 10-bit ADC module in the PIC family has the following features: Up to 8 channels of analog input are available, shared with parallel port pins. At any one time ONE channel may be selected for conversion using the 3 Channel Select bits in ADCON0. The conversion is started by bringing the GO bit in ADCON0 to 1. This opens the sample and hold switch and the voltage is held on the sample capacitance during the conversion. After the conversion is complete, the GO/DONE bit goes to 0 (and the ADIF flag is set in the Peripheral Interrupt register) and the 10- bit datum is placed in the ADRESH (ADRESult High) and ADRESL (ADRESult Low) registers ready for reading. The clock for the converter is set using the two ADCS bits in ADCON0 either from the main processor clock or from a separate oscillator. The ADCON1 register is used to configure the pins to be digital or analog and to choose an internal reference or external reference voltages. 37

38 ADCON1 has an AD ForMat bit to store the 10-bit outcome in two possible formats; namely: Left justified with the upper 8 bits in ADRESH which can be used as a plain 8-bit outcome. Right justified with the lower 8 bits in ADRESL and ADRESH holding the two upper bits with padded zeros. In this case the two RESult registers can be treated as a double-byte 10-bit value. 38

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40 Week 8 (Chapter 12) Asynchronous serial data transmission sends each datum as a separate frame Line goes to logic 0 for one period to signal the start of the frame (START) The datum bits are then transmitted one bit at a time least significant first Line goes to logic 1 for one period to signal the end of the frame (STOP) Line then idles at logic 1 until the next START pulse For example, transmitting the letter E (h 45 or b ) Idle START LS bit MS bit STOP Idle 40

41 Concepts Baud rate is a measure of information flow rate. In simple systems this is the same as bit rate. Baud rate is conventionally 110, 300, 600, 1200, 2400, Bit period is 1/(Baud rate); e.g. 1/600 = 1.666ms. With a single Start and Stop bit there are ten bits in a frame. Thus at 600 baud, 60 characters per second are send at maximum. The receiver is set to the same nominal rate as the transmitter to avoid having to transmit the clock signal via a separate channel. The clocks can differ by no more than ±½ (±50%) of a bit period in the ten bits to avoid loss of synchronization; that is ±5% A Simplex channel can only transmit in one direction. A half Duplex channel can transmit in either direction but not simultaneously. full Duplex channel can transmit simultaneously in both directions. 41

42 Normal logic voltages not suitable for transmission distances above around 30cm. Signalling techniques are used to modify the two signals to give longer ranges and suit the transmission channel (e.g. tones are used for telephone and wireless links). RS-232 is one of the most common of these signal standards. Two bipolar voltage levels are used; with the positive voltage representing logic 0 and the negative voltage logic 1. At the transmitter levels of typically ±12V with respect to ground. The receiver can sense voltages down to ±3V with respect to ground. Used for distances up to 15m at low speed Rather poor noise immunity, especially if there is any difference in the ground voltages between transmitter and receiver. Not designed for network use, which needs multiple transmitters and receivers sharing the one line. 42

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44 RS485 uses two conductors (instead of relying on the ground connections at remote points), usually twisted together. This is known as differential signalling as opposed to single-ended signalling where voltages are measured with respect to ground. Transmitter uses ±5V (when idling B wire is more positive than A wire) across the conductors to signal either logic level. Receiver can detect differences across the wires down to ±200mV Good noise immunity, as any externally induced noise will effect both conductors equally and the receiver is only interested in differences. Long distances at high speed are possible. Each transmitter has an enable input, so more than one driver can be connected to the link, provided that only one is enabled at any time. Multiple receivers can be connected to the link, giving with the above a network (LAN) capability. 44

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46 Handshaking or flow control is the protocol used by the transmitter to determine if the receiver is ready to accept a character. For an asynchronous link there are basically two different techniques: Hardware: Where there is a separate connection between transmitter and receiver, often labelled /CTS (Clear To Send) and /RTS (Ready To Send) where the signals are active logic When ready to TX, transmitter (Master) activates its /RTS line. 2. Master then checks the /CTS line from receiver (Slave). If now active goto Transmit the character. Advantages; fast, reliable and simple. Disadvantages; Needs two extra wires or channels. 46

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48 Software: Where special reserved characters are sent to the Master by the Slave indicating the latter s readiness to accept more information. These characters are usually named XON (code b or h 11 ) and XOFF (code b or h 13 ). Basically the Master keeps transmitting until and if the Slave sends back an XOFF character. It doesn t start up again until an XON character is received. 1. Master sends a character. 2. Has the Slave sent an XOFF character? If not then goto Do not goto 1 until an XON character is received. Advantage: Doesn t need two dedicated handshake channels. Disadvantages: Needs a Duplex link, not as reliable as a hardware scheme as can lock up of an XON or XOFF character is lost due to noise. 48

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50 How to generate asynchronous protocol signals. In software using bit twiddling; e.g. to code a subroutine to transmit a single character (putchar) at 4800 baud: 1. Output a low on a port pin for one baud delay (1/4800 = 208µs) to give the Start bit. 2. DO eight times: a) Shift datum right and set pin high or low according to the state of the bit that pops out into the Carry flag. b) Wait one baud delay. 3. Output a high on the port pin for one baud delay to give the Stop bit. A receive (getchar) subroutine is similar but waits for the line connected to a port pin to go low and then uses a ½ baud delay to find the middle point of the Start bit. The signal is then sampled eight times at baud delay intervals. 50

51 In hardware using shift registers and logic circuitry. A dedicated circuit to do this is called a Universal Asynchonous Receiver/ Transmitter (UART). A Basic UART will have the following properties: Baud-rate generator (sometimes an external BRG needs to be used) to generate shifting pulses at the appropriate clock rate to suit the baud rate. Transmit Shift and Buffer registers to hold the datum being shifted out with a Start and Stop bit appended. Transmit Buffer Empty flag to say when the Transmit Buffer register is empty and so can be updated. Receive Shift and Buffer registers. Receive Buffer Full flag to say when a new character has been shifted in and dumped into the Buffer ready for collection. 51

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53 To transmit a character: 1. Software checks the TBUF flag. If active try again until Buffer is empty. 2. Copy code into the Transmit Data Buffer Register. 3. When the actual Transmit Data Register is empty, this datum will be automatically transferred from the Buffer and the TBUF flag reset. 4. The datum is shifted out LSB first from the TX pin 5. after which a Start bit is sent and a Stop bit is appended at the end. To receive a character: 1. Software checks the RBUF flag to check if the Receive Data Buffer Register is full. If not active, try again. 2. Copy the new datum into an internal register. This will automatically deactivate the RBUF flag. 3. When another Start pulse is sensed at the RX pin, it is shifted in, the Start and Stop bits stripped and the datum copied into the Buffer and RBUF activated. 53

54 PIC USART module 54