MICROCOMPUTER OPERATION

Size: px

Start display at page:

Download "MICROCOMPUTER OPERATION"

Berenice Gray
6 years ago
Views:

1 CET270 Intro to Microprocessors Notes 3 MICROCOMPUTER OPERATION Previously, we covered basics of microcomputers including terminology and simplified computer and processor architectural diagrams. Now we turn our attention to basic operation of a computer. We start with just the ALU then expand to the system as a whole. I. ALU Operation accepts one (accumulator only) or two (accumulator and data reg.) operands performs selected arithmetic or logic operation as commanded by controller/sequencer per decoded opcode Ex. This figure shows execution of an ADD instruction both before (A) and after (B) instruction execution: (Diagrams from Microprocessors by Heathkit Educational Systems) 1

II. Computer Operation: Fetch-Execute Cycle By design, the innate nature of a processor is to fetch an instruction, decode and execute it, and repeat this process as fast as possible, forever.

2 II. Computer Operation: Fetch-Execute Cycle By design, the innate nature of a processor is to fetch an instruction, decode and execute it, and repeat this process as fast as possible, forever. Thus, processor operation is described by the fetch-execute cycle of the two aptly named phases. Processors begin life in the fetch phase. Vis: Begin Fetch Instruction Execute Instruction The fetch phase involves fetching an opcode from memory into the data register and decoding it. This generally takes a single clock cycle. The execute phase requires a variable number of clock cycles depending on the particular instruction. Thus, the duration of this phase typically varies from one instruction to the next. Analysis: a simple 3-instruction program to add two numbers. 0. Initial conditions PC=0, memory with given contents: opcode 1 operand 1 opcode 2 operand 2 opcode 3 2

3 1. Instruction 1 opcode fetch a. Contents of the PC are transferred to the address register. 3

4 1. Instruction 1 opcode fetch b. The PC is incremented by one (in anticipation of the next fetch). 4

5 1. Instruction 1 opcode fetch c. Address register contents are broadcasted over the address bus to the system. The proper memory (or I/O) device will decode the address bus to identify which specific location is being summoned. 5

6 1. Instruction 1 opcode fetch d. The contents of the selected location will be retrieved and sent over the data bus from the memory to the processor. The processor receives all data bus transfers into the data register. 6

7 1. Instruction 1 opcode fetch e. Since this is a fetch cycle, the data register contents are examined by the instruction decoder to determine which instruction opcode was just retrieved, and signals the controller/sequencer appropriately. This completes the fetch phase. 7

8 2. Instruction 1 execution a. To execute a LDA instruction, the processor must go fetch the operand to be loaded. For this particular LDA, the operand follows the opcode so the PC is again copied to the address register. 8

9 2. Instruction 1 execution b. The address register is broadcast via the address bus, and c. the PC is incremented by one. 9

2. Instruction 1 execution d. The address bus is decoded and memory sends the contents of the requested location (i.e. instruction 1 s operand) to the processor via the data bus.

10 2. Instruction 1 execution d. The address bus is decoded and memory sends the contents of the requested location (i.e. instruction 1 s operand) to the processor via the data bus. e. Since a load accumulator instruction is being executed, the operand goes straight into the accumulator. Instruction 1 execution is now complete. 10

11 3. Instruction 2 opcode fetch In the same manner as instruction 1 fetch, the second instruction (ADD) is fetched. Follow the number sequence in this diagram for the process. 11

4. Instruction 2 execution The ADD instruction is a bit more involved and requires invoking the ALU to determine the sum of two operands one already in

12 4. Instruction 2 execution The ADD instruction is a bit more involved and requires invoking the ALU to determine the sum of two operands one already in the accumulator and the second from the ADD instruction. The resulting sum is internally placed in the accumulator overwriting the old first operand. 12

5. Instruction 3 fetch & execution Fetch is always the same: copy PC to address register, increment PC, read opcode from data bus into data register and decode it.

13 5. Instruction 3 fetch & execution Fetch is always the same: copy PC to address register, increment PC, read opcode from data bus into data register and decode it. Executing a HLT instruction is nothing more than the controller/sequencer turning off all MPU clocks! Observation: on an HC11 operating at 2 MHz, everything you just analyzed over the last 11 pages would occur in 2.5 µs!! Why? Each instruction takes some number of clock cycles to complete, but generally speaking 1 cycle per memory access. A clock cycle is the reciprocal of the operating clock frequency. Remember: p = 1/f, so a microprocessor clock cycle, represented as ~, is really p. 13

8085 Microprocessor Architecture and Memory Interfacing. Microprocessor and Microcontroller Interfacing

8085 Microprocessor Architecture and Memory 1 Points to be Discussed 8085 Microprocessor 8085 Microprocessor (CPU) Block Diagram Control & Status Signals Interrupt Signals 8085 Microprocessor Signal Flow