CS:APP Chapter 4 Computer Architecture Logic Design Randal E. Bryant Carnegie Mellon University

Transcription

1 S:PP hapter 4 omputer rchitecture Logic esign Randal E. Bryant arnegie Mellon University S:PP

2 Overview of Logic esign Fundamental Hardware Requirements ommunication How to get values from one place to another omputation Storage Bits are Our Friends Everything expressed in terms of values 0 and 1 ommunication Low or high voltage on wire omputation ompute Boolean functions Storage Store bits of information 2 S:PP

3 igital Signals Voltage Time Use voltage thresholds to extract discrete values from continuous signal Simplest version: 1-bit signal Either high range (1) or low range (0) With guard range between them Not strongly affected by noise or low quality circuit elements an make circuits simple, small, and fast 3 S:PP

4 omputing with Logic Gates a b nd Or Not out a b out a out out = a && b out = a b out =!a Outputs are Boolean functions of inputs Respond continuously to changes in inputs With some, small delay Rising elay Falling elay a && b b Voltage a Time 4 S:PP

5 ombinational ircuits cyclic Network Primary Inputs Primary Outputs cyclic Network of Logic Gates ontinously responds to changes on primary inputs Primary outputs become (after some delay) Boolean functions of primary inputs 5 S:PP

6 Bit Equality a Bit equal HL Expression eq bool eq = (a&&b) (!a&&!b) b Generate 1 if a and b are equal Hardware ontrol Language (HL) Very simple hardware description language Boolean operations have syntax similar to logical operations We ll use it to describe control logic for processors 6 S:PP

7 Word Equality Word-Level Representation b 31 a 31 b 30 a 30 Bit equal Bit equal eq 31 eq 30 B = Eq HL Representation Eq bool Eq = ( == B) b 1 a 1 b 0 a 0 Bit equal Bit equal eq 1 eq 0 32-bit word size HL representation Equality operation Generates Boolean value 7 S:PP

8 Bit-Level Multiplexor s Bit MUX HL Expression b a out bool out = (s&&a) (!s&&b) ontrol signal s ata signals a and b Output a when s=1, b when s=0 8 S:PP

9 Word Multiplexor s Word-Level Representation s b 31 out 31 B MUX Out a 31 b 30 a 30 out 30 HL Representation int Out = [ s : ; 1 : B; ]; b 0 a 0 out 0 Select input word or B depending on control signal s HL representation ase expression Series of test : value pairs Output value for first successful test 9 S:PP

10 HL Word-Level Examples Minimum of 3 Words B MIN3 Min3 int Min3 = [ < B && < : ; B < && B < : B; 1 : ; ]; Find minimum of three input words HL case expression Final case guarantees match 4-Way Multiplexor s1 s MUX4 Out4 int Out4 = [!s1&&!s0: 0;!s1 : 1;!s0 : 2; 1 : 3; ]; Select one of 4 inputs based on two control bits HL case expression Simplify tests by assuming sequential matching 10 S:PP

11 rithmetic Logic Unit Y X B L U OF ZF F X + Y Y X B L U OF ZF F X - Y Y X B L U OF ZF F X & Y Y X B L U OF ZF F X ^ Y ombinational logic ontinuously responding to inputs ontrol signal selects function computed orresponding to 4 arithmetic/logical operations in Y86 lso computes values for condition codes 11 S:PP

12 Storing 1 Bit Bistable Element q!q Q q = 0 or 1 V V V1 V1 V V in V Vin S:PP

13 Storing 1 Bit (cont.) Bistable Element q!q Q q = 0 or 1 Stable V in = V 2 V V1Vin V2 V2 0.5 V in V1 Stable Vin S:PP Vin Metastable

14 . Physical nalogy Stable V1Vin V2 V Metastable Stable Vin Vin Metastable Stable left.. Stable right 14 S:PP

15 Storing and ccessing 1 Bit Bistable Element R-S Latch q R!q q = 0 or 1 Q S Q Resetting Setting Storing R R R 0!q q S Q S Q S 0 q!q Q 15 S:PP

16 1-Bit Latch ata Latch R lock S Q Latching Storing d!d!d!d d R d!d 0 R!q q 1 S d d!d Q 0 0 S q!q Q 16 S:PP

17 Transparent 1-Bit Latch Latching hanging d!d!d!d d R 1 S d d!d Q Time When in latching mode, combinational propogation from to and Q Value latched depends on value of as falls 17 S:PP

18 Edge-Triggered Latch ata R lock T Trigger S Q T Time Only in latching mode for brief period Rising clock edge Value latched depends on data as clock rises Output remains stable at all other times 18 S:PP

19 Registers Structure i 7 o 7 i 6 o 6 i 5 o 5 i 4 i 3 o 4 o 3 I O i 2 i 1 o 2 o 1 lock i 0 o 0 lock Stores word of data ifferent from program registers seen in assembly code ollection of edge-triggered latches Loads input on rising edge of clock 19 S:PP

20 Register Operation State = x Input = y Output = x x Rising clock State = y y Output = y Stores data bits For most of time acts as barrier between input and output s clock rises, loads input 20 S:PP

21 State Machine Example In omb. Logic 0 L U 0 1 MUX Out ccumulator circuit Load or accumulate on each cycle Load lock lock Load In Out x 0 x 1 x 2 x 3 x 4 x 5 x 0 x 0 +x 1 x 0 +x 1 +x 2 x 3 x 3 +x 4 x 3 +x 4 +x 5 21 S:PP

22 Random-ccess Memory val Read ports src valb Register file W valw dstw Write port srcb B Stores multiple words of memory ddress input specifies which word to read or write Register file Holds values of program registers %eax, %esp, etc. Register identifier serves as address» I 8 implies no read or write performed Multiple Ports lock an read and/or write multiple words in one cycle» Each has separate address and data input/output 22 S:PP

23 Register File Timing x val src valb srcb B 2 x Register file Reading Like combinational logic Output data generated based on input address fter some delay 2 Writing Like register Update only as clock rises 2 x Register file W valw dstw y 2 Rising clock 2 y Register file W valw dstw lock lock 23 S:PP

24 Hardware ontrol Language Very simple hardware description language an only express limited aspects of hardware operation Parts we want to explore and modify ata Types bool: Boolean a, b, c, int: words, B,, Statements oes not specify word size---bytes, 32-bit words, bool a = bool-expr ; int = int-expr ; 24 S:PP

25 HL Operations lassify by type of value returned Boolean Expressions Logic Operations a && b, a b,!a Word omparisons == B, < B, <= B, >= B, > B Set Membership in { B,, } Word Expressions» Same as == B == == ase expressions [ a : ; b : B; c : ] Evaluate test expressions a, b, c, in sequence Return word expression, B,, for first successful test 25 S:PP

26 Summary omputation Performed by combinational logic omputes Boolean functions ontinuously reacts to input changes Storage Registers Hold single words Loaded as clock rises Random-access memories Hold multiple words Possible multiple read or write ports Read word when address input changes Write word as clock rises 26 S:PP