Data types defined in the standard package
|
|
- Ronald Stokes
- 5 years ago
- Views:
Transcription
1 Data Types Each data object has a type associated with it. The type defines the set of values that the object can have and the set of operation that are allowed on it.
2 Data types defined in the standard package Predefined data type are as follows: Bit Bit_vector Boolean Character File_open_kind* File_open_status* Integer Natural Positive Real Severity_level String Time*
3 User-defined Types The Syntax is TYPE identifier is Type_definition; Example: type small_int is range 0 to 1024; type my_word_length is range 31 downto 0; subtype data_word is my_word_length range 7 downto 0;
4 Data Types A type declaration defines the name of the type and the range of the type. Type declaration are allowed in package declaration sections, entity declaration sections, architecture declaration sections, subprogram declaration section and process declaration sections.
5
6 Types available in VHDL Scalar types Integer types Real types Enumerated Physical Composite Types Arrays type Records Access Types (equivalent of pointers in C) File types
7 Scalar Types Scalar types describe objects that can hold, at most, one value at a time. Integer Type It is same as mathematical integers. All of the normal predefined mathematical function apply to integer types. Minimum Range: -2,147,483,647 to 12,147,483,647
8 Example - Integer Architecture test of test is Begin Process (x) Variable a: integer; Begin a := 1; --ok a := -1 ; -- ok a := 1.0; -- error End process; End test;
9 Real Types Real Types are used to declare objects that emulate mathematical real numbers. Real number can be used to represent numbers out of the range of integer value as well as fractional values. Minimum Range: -1.0E+38 to +1.0E+38
10 Example Real Types Architecture test of test is signal a : real; Begin a <= 1.0; -- ok a <= 1; -- error a <= -1.0E10; -- ok a <= 1.5E-20; --ok a <= 5.3 ns; -- error End test;
11 Enumerated types Enumerated type is used to represent exactly the values required for a specific operation. All of the values of an enumerated type are user-defined. This values can be identifiers or single-character literals. A typical example: TYPE fourval IS ( x, 0, 1, z ); TYPE color IS (red,yellow, blue,green,orange);
12 IEEE standard 1164 Type std_logic is ( U, -- uninititalized X, -- forcing unknown 0, -- forcing 0 1, -- forcing 1 Z, --high impedence W, --weak unknown L, --weak 0 H, -- weak 1 - ); -- don t care
13 Physical Types Physical types are used to represent physical quantities such as distance,current, time and so on. A physical type provides for a base unit,and successive units are then defined in terms of this unit. The smallest unit represented is one base unit. The largest unit is determined by the range specified in physical type declaration. TIME is a predefined physical types
14 Example Physical Type Package example is type current is range 0 to units na; ua = 1000 na; -- nano amp ma = 1000 ua; -- micro amp a = 1000 ma; End units; type load_factor is (small, med, big); End example;
15 Architecture delay-cal of delay is Begin delay <= 10 ns when (load = small) else 20 ns when (load = med) else 30 ns when (load = big) else 40 ns; out-current <= 1000 ua when (load= small) else 1 ma when (load = med) else 100 ua; End delay-cal;
16 Predefined physical type - Time Type TIME is Range <implementation defined> units fs; --femtosecond ps = 1000 fs; -- picosecond ns = 1000 ps; -- nansecond us = 1000 ns; -- microsecond ms = 1000 us; -- millisecond sec = 1000 ms; -- second min = 60 sec;-- minute hr = 60 min; -- hour End units;
17 Composite Types Arrays Type are groups of elements of the same type. Arrays are useful for modeling linear structure such as RAMs and ROMs. Record Types allow the grouping of elements of different types. Record are useful for modeling data packets, instructions and so on.
18 Array Types Array types group one or more elements of the same type together as a single object Each element of the array can be accessed by one or more array indices. Format of type declaration: TYPE data_bus IS array (0 to 31) of BIT;
19 Array slices and Ranges Assignment of arrays preserves the left-toright ordering regardless of the direction. Example Signal x : std_logic_vector(0 to 3);--case 1 Signal y : std_logic_vector(3 downto 0); --case2 X <= 1010 ; Y <= 0101 ;
20 Cont.. The assignment x<=y is equivalent to: X(0) <= Y(3); -- the left element X(1) <= y(2); X(2) <=Y(1); X(3) <=Y(0); -- the right elements The array range for case I in 0 to 3 loop, the elements of the array would be accessed from left to right. The array range for caseii in 3 downto 0 loop, the elements of the array would be accessed from right to left.
21 Multidimensional Array Type aggregate is array (range<>) of std_logic; Type identifier_a is array(range<>) of aggregate; Constant identifier_b : identifier_a := ((e1,e2 en), -- E1 (e1,e2, en), --E2. (e1,e2, en)); --En
22 Example-Multidimensional arrays Library ieee; Use ieee.std_logic_1164.all; Package memory is constant width : integer := 3; constant memsize : integer := 7; Type data_out is array (0 to width) of std_logic; Type mem_data is arrary (0 to memsize) of data_out; End memory;
23 Library ieee; Use ieee.std_logic_1164.all; Use work.memory.all; Enity rom is -- ROM declaration port (addr : in integer; data : out data_out; cs : in std_logic; End rom;
24 Architecture basic of rom is constant z_state : data_out := ( z, z, z, z ); constant x_state : data_out := ( x, x, x, x ); constant rom_data : mem_data := ( ( 0, 0, 0, 0 ), ( 0, 0, 0, 1 ), ( 0, 0, 1, 0 ), ( 0, 0, 1, 1 ), ( 0, 1, 0, 0 ), ( 0, 1, 0, 1 ), ( 0, 1, 1, 0 ), ( 0, 1, 1, 1 ), ); Begin data <= rom_data (addr) when cs = 1 else x_state when cs = 0 else z_state; End basic;
25 Record Types Record types group object of may types together as a single object. Each element of the record can be accessed by its field name. Record elements can include elements of any type, including arrays and records. The elements of a record can be of the same type or different types.
26 Features of Records A record is referenced by a single identifier. Records are very useful to collapse multiple related elements into a single type so that record objects can be handle as a objects. They are very useful in Bus Functional Models and test benches to pass a set of information to another process or another component. Values can be assigned to a record type using aggregates in a manner similar to aggregates for arrays.
27 Limitation Many synthesizers can compile records provided the elements of the record are of type Bit, bit_vector, boolean, std_ulogic, Std_ulogic_vector, integer or subtypes of these types. However, most current synthesizers do not accept record aggregate assignments, and thus require individual assignment of the record elements.
28 Example - Records Type optype is (add,sub,mpy,div,jmp); Type instruction is Record -- declaration of record opcode : optype; -- field of record src : integer; dat : integer; End record;
29 Process (x) variable inst : instruction; variable source,dat : integer; variable operator : optype; Begin source := inst.src; -- ok dest := inst.src; -- ok source := inst.opcode; -- error operator := inst.opcode; --ok inst.src := dest; --ok
30 Access Types Access types allow the designer to model objects of a dynamic nature. E.g. Queues, FIFO, Creating and Maintaining of a linked list. Only variables can be declared as access types. Used in Sequential processing Not Synthesizeable statement.
31 Cont.. Access types are used to declare values that access dynamically allocated variables. Dynamically allocated variables are referenced, not by name, but by an access value that acts like a pointer to the variable. Access types are used in the TextIO subprograms to read and write text strings. Access types were efficiently used in VHDL in the functional modeling of large memories where fixed memory allocation is not realistic.
32 File Types A file type allows declaration of objects that have a type FILE. A file object type is actually a subset of the variable object type. A variable object can be assigned with a variable assignment, while a file object cannot be assigned. A file object can be read from, written to, and checked for end of file only with special procedure and functions.
33 Cont.. File types are typically used to access files in the host environment. File types are used to define objects representing files in the host system environment. The value of a file object is the sequence of values contained in the host environment. Package TextIO provides for the definition of file type TEXT as type TEXT is file of string. TextIO package supports human readable IO.
34 Characters, Strings To use character literal in a VHDL Code, one puts it in a single quotation mark. a, B,, A string of character are placed in double quotation marks: aa, bb Any printing character can be included inside a string.
35 Bit Strings A bit-strings represents a sequence of bit values. E.g. Binary : B 1100_1001, b Hexagonal : X C9, X 4b Octal : O 311, o 113
Inthis lecture we will cover the following material:
Lecture #8 Inthis lecture we will cover the following material: The standard package, The std_logic_1164 Concordia Objects & data Types (Signals, Variables, Constants, Literals, Character) Types and Subtypes
More informationIntroduction to VHDL. Main language concepts
Introduction to VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Current standard is IEEE 1076-1993 (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab
More informationVHDL Part 2. What is on the agenda? Basic VHDL Constructs. Examples. Data types Objects Packages and libraries Attributes Predefined operators
VHDL Part 2 Some of the slides are taken from http://www.ece.uah.edu/~milenka/cpe428-02s/ What is on the agenda? Basic VHDL Constructs Data types Objects Packages and libraries Attributes Predefined operators
More informationDigital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II
Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA VHDL Lexical Description Code
More informationSynthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden
Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March
More informationDigitaalsüsteemide disain
IAY 0600 Digitaalsüsteemide disain VHDL discussion Verification: Testbenches Design verification We want to verify that our design is correct before the target PLD is programmed. The process performed
More informationECE U530 Digital Hardware Synthesis. Course Accounts and Tools
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu Sept 13, 2006 Lecture 3: Basic VHDL constructs Signals, Variables, Constants VHDL Simulator and Test benches Types Reading: Ashenden
More informationLANGUAGE VHDL FUNDAMENTALS
LANGUAGE VHDL FUNDAMENTALS Introduction Entities and architectures Sentences and processes Objects Data types and operands Authors: Luis Entrena Arrontes, Celia López, Mario García, Enrique San Millán,
More informationVHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit
VHDL VHDL Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL Alternative (Student Generated) Definition Very Hard Digital Logic language VHDL Design
More informationLecture 3 Introduction to VHDL
CPE 487: Digital System Design Spring 2018 Lecture 3 Introduction to VHDL Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 Managing Design
More informationUNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library :
UNIT I Introduction to VHDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming languages used to model a digital system by dataflow, behavioral
More informationMulti-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized
Multi-valued Logic Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized X, unknown 0, logic 0 1, logic 1 Z, high impedance W, unknown L, logic 0 weak H, logic 1 weak - ); don t care Standard
More informationEmbedded Systems CS - ES
Embedded Systems - 1 - REVIEW Hardware/System description languages VDHL VHDL-AMS SystemC TLM - 2 - VHDL REVIEW Main goal was modeling of digital circuits Modelling at various levels of abstraction Technology-independent
More informationReview. VHDL in Action. This week. Lexical Elements. Literals. More Literals. Concurrent statements Conditional and selected signal assignments
Review Concurrent statements Conditional and selected signal assignments Cannot be placed inside a process Equivalent to some process Assert statement Debugging VHDL in Action Chapter 3 Chapter 5, Section
More informationOutline CPE 626. Advanced VLSI Design. Lecture 4: VHDL Recapitulation (Part 2) Signals. Variables. Constants. Variables vs.
CPE 626 Lecture 4: VHDL Recapitulation (Part 2) Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and
More informationSubprograms, Packages, and Libraries
Subprograms, Packages, and Libraries Sudhakar Yalamanchili, Georgia Institute of Technology ECE 4170 (1) function rising_edge (signal clock: std_logic) return boolean is declarative region: declare variables
More informationVHDL BASIC ELEMENTS INTRODUCTION
VHDL BASIC ELEMENTS INTRODUCTION VHDL Basic elements Identifiers Basic identifiers Extended identifiers Data Objects Constant Variable Signal File Data Types Scalar Composite Access File type Identifiers
More informationVHDL 200X: The Future of VHDL
VHDL 200X: The Future of VHDL By Jim Lewis VHDL Training Team Leader VHDL-200X Fast Track jim@synthworks.com Lewis 1 MAPLD 2005 / P255 VHDL-200X: The Future of VHDL Currently the work is being funded through
More informationBASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS. Lecture 7 & 8 Dr. Tayab Din Memon
BASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS Lecture 7 & 8 Dr. Tayab Din Memon Outline Data Objects Data Types Operators Attributes VHDL Data Types VHDL Data Objects Signal Constant Variable File VHDL Data
More informationProcesses. #44/137 TKT-1212 Dig.järj.tot., syksy 2008, A. Kulmala, TTY
Processes #44/137 TKT-1212 Dig.järj.tot., syksy 2008, A. Kulmala, TTY Process Basic modeling concept of VHDL Processes are executed in parallel Contains a set of statements that are executed sequentially
More informationVHDL And Synthesis Review
VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only
More informationOutline. CPE/EE 422/522 Advanced Logic Design L07. Review: JK Flip-Flop Model. Review: VHDL Program Structure. Review: VHDL Models for a MUX
Outline CPE/EE 422/522 Advanced Logic Design L07 Electrical and Computer Engineering University of Alabama in Huntsville What we know How to model Combinational Networks in VHDL Structural, Dataflow, Behavioral
More informationBasic Language Constructs of VHDL
Basic Language Constructs of VHDL Chapter 3 1 Outline 1. Basic VHDL program 2. Lexical elements and program format 3. Objects 4. Data type and operators Chapter 3 2 1. Basic VHDL program Chapter 3 3 Design
More informationBasic Language Concepts
Basic Language Concepts Sudhakar Yalamanchili, Georgia Institute of Technology ECE 4170 (1) Describing Design Entities a sum b carry Primary programming abstraction is a design entity Register, logic block,
More informationEE 595. Part IV Basic Elements in VHDL. EE 595 EDA / ASIC Design Lab
EE 595 Part IV Basic Elements in VHDL Identifiers An identifier can be any length, in other words, as many characters as desired An identifier case insensitive, meaning that there no difference between
More informationEEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 9: Short Introduction to VHDL* Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 What does HDL stand for? HDL is short for Hardware Description
More informationLogic and Computer Design Fundamentals VHDL. Part 1 Chapter 4 Basics and Constructs
Logic and Computer Design Fundamentals VHDL Part Chapter 4 Basics and Constructs Charles Kime & Thomas Kaminski 24 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Overview
More informationWhat Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993)
What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993) Only possible to synthesize logic from a subset of VHDL Subset varies according to
More informationSpecifying time in VHDL
Computer System Structures cz:struktury počítačových systémů Lecturer: Richard Šusta richard@susta.cz, susta@fel.cvut.cz, +420 2 2435 7359 Version: 1.0 ČVUT-FEL in Prague, CR subject A0B35SPS Specifying
More informationIntroduction to VHDL
Introduction to VHDL Agenda Introduce VHDL Basic VHDL constructs Implementing circuit functions Logic, Muxes Clocked Circuits Counters, Shifters State Machines FPGA design and implementation issues FPGA
More informationLecture 4. VHDL Fundamentals. George Mason University
Lecture 4 VHDL Fundamentals George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL 2 Design Entity ECE 448 FPGA and ASIC Design with
More informationCSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\
CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,
More informationConcurrent Signal Assignment Statements (CSAs)
Concurrent Signal Assignment Statements (CSAs) Digital systems operate with concurrent signals Signals are assigned values at a specific point in time. VHDL uses signal assignment statements Specify value
More informationDesign units can NOT be split across different files
Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical elements, program format, data types and operators A VHDL program consists of a collection
More informationDigital Systems Design
IAY 0600 Example: HalfAdder Behavior Structure Digital Systems Design a b Sum Carry 0 0 0 0 0 1 1 0 a b HalfAdder Sum Carry 1 0 1 0 VHDL discussion Dataflow Style Combinational Design 1 1 0 1 a Sum Sum
More informationIntroduction to VHDL #1
ECE 3220 Digital Design with VHDL Introduction to VHDL #1 Lecture 3 Introduction to VHDL The two Hardware Description Languages that are most often used in industry are: n VHDL n Verilog you will learn
More informationECE 545 Lecture 4. Simple Testbenches. George Mason University
ECE 545 Lecture 4 Simple Testbenches George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3 Testbench
More informationCprE 583 Reconfigurable Computing
Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering
More informationThe University of Alabama in Huntsville ECE Department CPE Midterm Exam February 26, 2003
The University of Alabama in Huntsville ECE Department CPE 526 01 Midterm Exam February 26, 2003 1. (20 points) Describe the following logic expression (A B D) + (A B C) + (B C ) with a structural VHDL
More informationThe Designer's Guide to VHDL Second Edition
The Designer's Guide to VHDL Second Edition Peter J. Ashenden EDA CONSULTANT, ASHENDEN DESIGNS PTY. VISITING RESEARCH FELLOW, ADELAIDE UNIVERSITY Cl MORGAN KAUFMANN PUBLISHERS An Imprint of Elsevier SAN
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 4 Introduction to VHDL
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 4 Introduction to VHDL Read before class: Chapter 2 from textbook (first part) Outline VHDL Overview VHDL Characteristics and Concepts
More informationVHDL for FPGA Design. by : Mohamed Samy
VHDL for FPGA Design by : Mohamed Samy VHDL Vhdl is Case insensitive myvar = myvar = MYVAR IF = if = if Comments start with -- Comments can exist anywhere in the line Semi colon indicates the end of statements
More informationCDA 4253 FPGA System Design VHDL Testbench Development. Hao Zheng Comp. Sci & Eng USF
CDA 4253 FPGA System Design VHDL Testbench Development Hao Zheng Comp. Sci & Eng USF art-4- > 70% projects spent > 40% time in verification 2 Validation, Verification, and Testing Validation: Does the
More informationVHDL for Complex Designs
ELEC 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 1998/99 WINTER SESSION, TERM 2 VHDL for Complex Designs This lecture covers VHDL features that are useful when designing complex logic circuits. After
More informationIEEE VHDL-200X
IEEE 1076-2008 VHDL-200X By Jim Lewis, VHDL Training jim@synthworks.com IEEE 1076-2008 IEEE VASG - VHDL-200X effort Started in 2003 and made good technical progress However, no $$$ for LRM editing Accellera
More informationLecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
More informationLecture 10 Subprograms & Overloading
CPE 487: Digital System Design Spring 2018 Lecture 10 Subprograms & Overloading Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 Subprograms
More informationA bird s eye view on VHDL!
Advanced Topics on Heterogeneous System Architectures A bird s eye view on VHDL Politecnico di Milano Conference Room, Bld 20 19 November, 2015 Antonio R. Miele Marco D. Santambrogio Politecnico di Milano
More information0. Overview of this standard Design entities and configurations... 5
Contents 0. Overview of this standard... 1 0.1 Intent and scope of this standard... 1 0.2 Structure and terminology of this standard... 1 0.2.1 Syntactic description... 2 0.2.2 Semantic description...
More informationMenu. Introduction to VHDL EEL3701 EEL3701. Intro to VHDL
3-Jul-1 4:34 PM VHDL VHDL: The Entity VHL: IEEE 1076 TYPE VHDL: IEEE 1164 TYPE VHDL: The Architecture Mixed-Logic in VHDL VHDL MUX examples See also example file on web: Creating graphical components (Component_Creation.pdf)
More informationHardware Modeling. VHDL Syntax. Vienna University of Technology Department of Computer Engineering ECS Group
Hardware Modeling VHDL Syntax Vienna University of Technology Department of Computer Engineering ECS Group Contents Identifiers Types & Attributes Operators Sequential Statements Subroutines 2 Identifiers
More informationVHDL is a hardware description language. The code describes the behavior or structure of an electronic circuit.
VHDL is a hardware description language. The code describes the behavior or structure of an electronic circuit. Its main applications include synthesis of digital circuits onto CPLD/FPGA (Complex Programmable
More informationLecture 4. VHDL Fundamentals. Required reading. Example: NAND Gate. Design Entity. Example VHDL Code. Design Entity
Required reading Lecture 4 VHDL Fundamentals P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL George Mason University 2 Example: NAND Gate Design Entity a b z a b z 0
More informationDigital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
More information[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.
Lecture 12 1 Reference list [1] Douglas L. Perry, VHDL, third edition, ISBN 0-07-049436-3, McRaw- Hill Series on Computer Engineering. [2] Kevin Skahil, VHDL for programmable logic, ISBN 0-201-89586-2
More informationAdvanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis. 26 October - 20 November, 2009
2065-15 Advanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis 26 October - 20 November, 2009 FPGA Architectures & VHDL Introduction to Synthesis Nizar Abdallah ACTEL Corp.2061
More informationBasic Language Elements
Basic Language Elements Identifiers A basic identifier: May only contain alphabetic letters (A to Z and a to z), decimal digits (0 to 9) and the underline character (_) Must start with an alphabetic letter
More informationECOM 4311 Digital System Design using VHDL. Chapter 7
ECOM 4311 Digital System Design using VHDL Chapter 7 Introduction A design s functionality should be verified before its description is synthesized. A testbench is a program used to verify a design s functionality
More information!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"
!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"!!"#$%&'#()#*+"+#,-."/0110#230#4."50",+"+#)6# 6+-+#(.6+-0#)4475.8)60#0/#.65-0#230#9+**+"+# 2.48).-0#(.6+-0#! 2+"*5."5*:#,."/0110#;)**0! *),".6*:#-.99-0*0"5."+#2+660,.40"5)#;)*)2)#
More informationENGIN 241 Digital Systems with Lab
ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided
More information310/ ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006
310/1780-10 ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006 VHDL & FPGA - Session 2 Nizar ABDALLH ACTEL Corp. 2061 Stierlin Court
More informationPART I THE VHDL LANGUAGE CHAPTER 1: TOP LEVEL VHDL OVERVIEW
PART I THE VHDL LANGUAGE CHAPTER 1: TOP LEVEL VHDL OVERVIEW 1.0 VHDL design Units The VHDL language is specifically tailored to designing circuits at both behavioral and gate levels. Although it may be
More informationVHDL: Modeling RAM and Register Files. Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2
VHDL: Modeling RAM and Register Files Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2 Memory Synthesis Approaches: Random logic using flip-flops or latches Register files in datapaths RAM standard components
More informationAssignment. Last time. Last time. ECE 4514 Digital Design II. Back to the big picture. Back to the big picture
Assignment Last time Project 4: Using synthesis tools Synplify Pro and Webpack Due 11/11 ning of class Generics Used to parameterize models E.g., Delay, bit width Configurations Configuration specification
More informationVerilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL.
Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. HDL s allows the design to be simulated earlier in the design
More informationConstructing VHDL Models with CSA
Constructing VHDL Models with CSA List all components (e.g., gate) inclusive propagation delays. Identify input/output signals as input/output ports. All remaining signals are internal signals. Identify
More informationVHDL 200X: The Future of VHDL
March 1-3, 2004 VHDL 200X: The Future of VHDL By Jim Lewis VHDL Training Team Leader VHDL-200X Fast Track jim@synthworks.com VHDL-200X: The Future of VHDL VHDL-200X is a multi-phased effort. Covers the
More informationJUNE, JULY 2013 Fundamentals of HDL (10EC45) PART A
JUNE, JULY 2013 Fundamentals of HDL (10EC45) Time: 3hrs Max Marks:100 Note: Answer FIVE full questions, selecting at least TWO questions from each part. PART A Q1.a. Describe VHDL scalar data types with
More informationCDA 4253 FPGA System Design Introduction to VHDL. Hao Zheng Dept of Comp Sci & Eng USF
CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci & Eng USF Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 1, Gate-level combinational circuits Two purposes of using
More informationLecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1
Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1
DIGITAL LOGIC WITH VHDL (Fall 23) Unit DESIGN FLOW DATA TYPES LOGIC GATES WITH VHDL TESTBENCH GENERATION DESIGN FLOW Design Entry: We specify the logic circuit using a Hardware Description Language (e.g.,
More informationAccellera VHDL By Jim Lewis, SynthWorks VHDL Training
Accellera VHDL-2006 By Jim Lewis, VHDL Training jim@synthworks.com MARLUG - Mid-Atlantic Region Local Users Group ANNUAL CONFERENCE - OCTOBER 12, 2006 Johns Hopkins University Applied Physics Lab Laurel,
More informationIntroduction to VHDL. Yvonne Avilés Colaboration: Irvin Ortiz Flores Rapid System Prototyping Laboratory (RASP) University of Puerto Rico at Mayaguez
Introduction to VHDL Yvonne Avilés Colaboration: Irvin Ortiz Flores Rapid System Prototyping Laboratory (RASP) University of Puerto Rico at Mayaguez What is VHDL? Very High Speed Integrated Circuit Hardware
More informationINTRODUCTION TO VHDL ADVANCED COMPUTER ARCHITECTURES. Slides by: Pedro Tomás. Additional reading: - ARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC)
INTRODUCTION TO VHDL Slides by: Pedro Tomás Additional reading: - ADVANCED COMPUTER ARCHITECTURES ARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC) Outline 2 Hardware Description Languages (HDL) VHDL Very
More informationLeonardoSpectrum for Altera HDL Synthesis Manual
LeonardoSpectrum for Altera HDL Synthesis Manual Software Version v2001.1 July 2001 Copyright 2001 Exemplar Logic, Inc., A Mentor Graphics Company. All rights reserved. This document contains information
More informationBuilding Blocks. Entity Declaration. Entity Declaration with Generics. Architecture Body. entity entity_name is. entity register8 is
Building Blocks Entity Declaration entity entity_name is [signal] identifier {, identifier}: [mode] signal_type {; [signal] identifier {, identifier}: [mode] signal_type}); end [entity ] [entity_name];
More informationHardware Modeling. VHDL Basics. ECS Group, TU Wien
Hardware Modeling VHDL Basics ECS Group, TU Wien VHDL Basics 2 Parts of a Design Unit Entity Architecture Configuration Package Package Package Body Library How to create a Design Unit? Interface to environment
More informationGeneratore di parità. LIBRARY ieee; USE ieee.std_logic_1164.all ; ENTITY xor2 IS PORT( A, B : in std_logic ; Y : out std_logic ) ; END xor2 ;
LIBRARY ieee; USE ieee.std_logic_1164.all ; ENTITY xor2 IS PORT( A, B : in std_logic ; Y : out std_logic ) ; END xor2 ; ARCHITECTURE arch1 OF Xor2 IS BEGIN Y
More informationLab # 5. Subprograms. Introduction
Lab # 5 Subprograms Introduction Subprograms consist of procedures and functions. A procedure can return more than one argument; a function always returns just one. In a function, all parameters are input
More informationECE 3401 Lecture 10. More on VHDL
ECE 3401 Lecture 10 More on VHDL Outline More on VHDL Some VHDL Basics Data Types Operators Delay Models VHDL for Simulation VHDL for Synthesis 1 Data Types Every signal has a type, type specifies possible
More informationOutline CPE 626. Advanced VLSI Design. Lecture 3: VHDL Recapitulation. Intro to VHDL. Intro to VHDL. Entity-Architecture Pair
Outline CPE 626 Lecture 3: VHDL Recapitulation Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and Computer
More informationContents. Appendix D VHDL Summary Page 1 of 23
Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data
More informationLecture 5: State Machines, Arrays, Loops. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 5: State Machines, Arrays, Loops BCD to Excess-3 (XS 3 ) Code Converter Example: Fig. 2-53 2 Easier to use one type of code (e.g. XS 3 ) over the other type (e.g. BCD)
More informationVHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents
VHDL Testbench Tutorial 1 Contents 1 VHDL Testbench 2 Test Bench Syntax 3 Testbench Example: VHDL Code for Up Down Binary Counter 4 VHDL Testbench code for up down binary counter 5 Testbench Waveform for
More informationDigital Systems Design
IAY 0600 Digital Systems Design VHDL discussion Dataflow Style Combinational Design Tallinn University of Technology Combinational systems Combinational systems have no memory. A combinational system's
More informationC-Based Hardware Design
LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples
More informationThe CPU Bus : Structure 0
The CPU Bus : Structure 0 The following can be applied to both the internal CPU buses and the external system buses. This distinction becomes blurred when we discuss Systems on a single Chip (SoC). The
More informationTest Bench. Top Level Model Test Bench MUT
A test bench is usually a simulation-only model used for design verification of some other model(s) to be synthesized. A test bench is usually easier to develop than a force file when verifying the proper
More informationVery High Speed Integrated Circuit Har dware Description Language
Very High Speed Integrated Circuit Har dware Description Language Industry standard language to describe hardware Originated from work in 70 s & 80 s by the U.S. Departm ent of Defence Root : ADA Language
More informationVHDL Instant. Table of contents. History
VHDL Instant This document aims at giving essential information on VHDL syntax including small examples. It does not provide a complete coverage of the language. History v1.0 2002 Initial version. v1.1
More information5. VHDL - Introduction - 5. VHDL - Design flow - 5. VHDL - Entities and Architectures (1) - 5. VHDL - Entities and Architectures (2) -
Sistemas Digitais I LESI - 2º ano Lesson 5 - VHDL Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática - Introduction - VHDL was developed, in the mid-1980s, by DoD and IEEE. VHDL stands
More informationSub-programs in VHDL
ECE381(CAD), Lecture 12: Sub-programs in VHDL Mehdi Modarressi Department of Electrical and Computer Engineering, University of Tehran Pictures and examples are taken from the slides of VHDL: Analysis
More informationIntroduction to the VHDL language. VLSI Digital Design
Introduction to the VHDL Hardware description language 1. Introduction 2. Basic elements 3. Scalar data types 4. Composed data types 5. Basic constructs (system definition) 6. Data flow description level
More informationVHDL: skaitmeninių įtaisų projektavimo kalba. 2 paskaita Pradmenys
VHDL: skaitmeninių įtaisų projektavimo kalba 2 paskaita Pradmenys Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical elements, program format,
More informationThe block diagram representation is given below: The output equation of a 2x1 multiplexer is given below:
Experiment-3: Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. multiplexer b. De-Multiplexer Objective: i. To learn the VHDL coding for Multiplexer and
More informationHardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
More information5. 0 VHDL OPERATORS. The above classes are arranged in increasing priority when parentheses are not used.
Filename= ch5.doc 5. 0 VHDL OPERATORS There are seven groups of predefined VHDL operators: 1. Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < >= 3. Shifts operators:
More informationCPE/EE 422/522. Chapter 8 - Additional Topics in VHDL. Dr. Rhonda Kay Gaede UAH. 8.1 Attributes - Signal Attributes that return a value
CPE/EE 422/522 Chapter 8 - Additional Topics in VHDL Dr. Rhonda Kay Gaede UAH 1 8.1 Attributes - Signal Attributes that return a value A event true if a has just occurred A active true if A has, even if
More informationVHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit
More informationECOM4311 Digital Systems Design
ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1 Agenda 1. VHDL : Data Types Cont d 2. VHDL : Operators 3. VHDL : Signal Assignments
More information