Module 6 : VHDL 1. Module- 6 VHDL

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1 Module 6 : VHDL 1 Module- 6 VHDL 6.1 Motivation VHDL (Very High Speed IC Hardware description Language) is one of the Standard hardware description language used to design digital systems. VHDL can be used to design the lowest level (gate level) of a digital system to the highest level (VLSI module). VHDL though being a rigid language with a standard set of rules allows the designer to use different methods of design giving different perspectives to the digital system. 6.2 Syllabus: Module Contents Duration Self-Study 6.1 Introduction to VHDL, 01 Hr 02 Hrs 6.2 Library, Entity, 01 Hr 6.3 Architecture Modeling styles, 01 Hr 02 Hrs 6.4 Concurrent and Sequential statements, 01 Hr 6.5 data objects and data types, attributes, 01 Hr 02 Hrs 6.6 design examples for combinational circuits 01 Hr 01 Hrs 6.3. Weightage in university Examination: 6.4. Learning Objective/outcomes: Learning Objective :Students will try to Describe Hardware description language Learning outcomes: Student will be able to Translate real world problems into digital logic formulations using VHDL Theoretical Background: One has to have very good knowledge of C programming and combinational logic for understanding the VHDL programming. 6.6 Introduction

2 Module 6 : VHDL VHDL Introduction VHDL is a description language for digital electronic circuits that is used in dierent levels of abstraction. The VHDL acronym stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. This means that VHDL can be used to accelerate the design process. It is very important to point out that VHDL is NOT a programming language. Therefore, knowing its syntax does not necessarily mean being able to designing digital circuits with it. VHDL is an HDL (Hardware Description Language), which allows describing both asynchronous and synchronous circuits. For this purpose, we shall: Think in terms of gates and ip-ops, not in variables or functions. Avoid combinatorial loops and conditional clocks. Know which part of the circuit is combinatorial and which one is sequential. Why to use an HDL? To discover problems and faults in the design before actually implementing it in hardware. The complexity of an electronic system grows exponentially. For this reason, it is very convenient to build a prototype of the circuit previously to its manufacturing process. It makes easy for a team of developers to work together. In particular, VHDL allows not only describing the structure of the circuit (description from more simple sub circuits), but also the specification of the functionality of a circuit using directives, in a similar way as most standard programming languages do. The most important aim of an HDL is to be able to simulate the logical behavior of a circuit by means of a description language that has many similarities with software description languages. Digital circuits described in VHDL can be simulated using simulation tools that reproduce the operation of the involved circuit. For this purpose, developers use a set of rules standardized by the IEEE, which explain the syntax of the language, as well as how to simulate it. In addition, there are many tools that transform a VHDL code into a downloadable le that can be used to program a reconfigurable device. This process is named synthesis. The way a given tool carries out the synthesis process is very particular, and it greatly differs from what other synthesis tools do Libraries and Packages. In most vhdl programs you have already seen examples of packages and libraries. Here are two: library ieee;

3 Module 6 : VHDL 3 use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; The packages are "std_logic_1164" and "std_logic_signed" and the library is "ieee". Since the "scope" of the library statement extends over the entire file, it is not necessary to repeat that for the second package. It's instructive to show where the packages are physically located. For Altera Max+2 and Xilinx Foundation these locations typically are: Altera: ~\maxplus2\vhdl93\ieee\std1164.vhd Xilinx: ~\fndtn\synth\lib\packages\ieee\src\std_logic_1164.vhd It is thus tempting to come to the conclusion that the "library ieee;" statement indicates the "directory" in which the std_logic_1164 package is located. Note, however, where it is in Synplicity: Synplicty: ~\synplcty\lib\vhd\std1164.vhd In the latter there is no mention of "ieee" at all. It is thus more appropriate to think of "ieee" as a pointer to the location of the package. The directory structure shown in those three examples depicts the directories where the packages are loaded when the software is installed. The pointer "ieee" is hardcoded in the compilers and thus there is no need for the user to associate that pointer with the directory structure, nor is it possible to put the packages anywhere else after the software has been loaded. The files "std1164.vhd" (Altera and Synplicty) and "std_logic_1164.vhd" (Xilinx) show a close resemblance to the package name as given in the "use" statement, but apparently they don't have to be the same as the package name. The actual package is in those files and shows up in there as the following statement: package std_logic_1164 is which is identical for all three.vhd files. That statement is reminiscent of the entity statement and indeed, a package is also considered a design unit, similar to an entity and an architecture. It's in the "st_logic_1164" package that std_logic values, such as 1, 0, Z, etc. are defined. Open up one of those.vhd files with any ascii editor, and see how that is done. Make sure, however, not to make any changes in these files. So it'd be better to

4 Module 6 : VHDL 4 first copy them to a file with another name and look at that one, just to be on the safe side. In addition to a "package", the file containing the package may also have a "package body", which is yet another design entity in the VHDL sense. An example is the definition of the "+" (addition) operator for use with std_logic_vectors. The language only defines "+" for integers and reals, thus a package in a library is needed to "overload", as it is called, the "+" operator so it can be applied to other things, e.g. std_logic_vector. The package std_logic_signed contains the definition of "+" for that case and the package body defines its functionality. Thus a package and a package body go together similarly to an entity and its architecture. However, a package may or may not have a package body, unlike an entity, which must have an architecture. Here is an example how that is arranged in the file containing the package std_logic_signed (in the file "signed.vhd" in both Altera and Synplicity and in the file "std_logic_signed.vhd" in Xilinx). The pertinent excerpt from that file is shown below: package STD_LOGIC_SIGNED is function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- other similar function definitions end STD_LOGIC_SIGNED; package body STD_LOGIC_SIGNED is function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is constant length: INTEGER := maximum(l'length, R'length); variable result : STD_LOGIC_VECTOR (length-1 downto 0); end; -- other similar function descriptions end STD_LOGIC_SIGNED; result := SIGNED(L) + SIGNED(R); return std_logic_vector(result);

5 Module 6 : VHDL 5 The "L" and "R" stand for the left and right operand respectively, on either side of the operator "+". The "return" indicates the type of signal that results from the operation. The use of the "maximum" function allows the two operands to be of different length and makes the resultant signal width equal to the widest of the two vectors. Note, the function "maximum" must also be defined in the package body, as it is not an inherent part of the language. Note also that the.vhd file that contains a package need not be named the same as the package. Constants, variables, types and subtypes are defined similarly in the various packages that come with the software. However, the contents of these packages is not identical and which items are defined where, may also differ from manufacturer to manufacturer. It is unfortunate that the standardization of the language does not extend to the contents of the packages or even their names. This may make the code nonportable. On the other hand, the concept of the "package" is powerful, especially since there is also a mechanism for setting up user libraries and packages Entity Entity is the description of the interface between a design and its external environment. It may also specify the declarations and statements that are part of the design entity. A given entity declaration may be shared by many design entities, each of which has a different architecture. Thus, an entity declaration can potentially represent a class of design entities, each having the same interface. Simplified Syntax entity entity_name is generic (generic_list); port (port_list);] end entity entity_name; Description An entity specifies the interface between the specified design (formally called a design entity) and the environment in which it operates. On the other hand, an architecture is a description of the inner design operation and it must be assigned to an entity. The architecture can be assigned to one entity only but one entity may be assigned to a number of architectures.

6 Module 6 : VHDL 6 The entity statement declares the design name (the identifier item in the Syntax example). In addition, it defines generic parameters (see generic) and ports (see port) of the design entity. Generic parameters provide static information (like timing parameters or bus width) to a design. Ports provide communication channels between the design and its environment. For each port, its mode (i.e. data flow) and type are defined. Optionally, an entity may contain a declarative part. Any subprograms, types, subtypes, and constants can be declared here. Declarations which are defined in an entity are visible to all architectures assigned to this entity. An entity may contain its own statements, declared after the keyword. The statements here must be passive, which means they cannot alter values of any signals; Passive processes, concurrent assertion statements and passive concurrent procedure calls can be used here. The entity declaration may be preceded by the library and use clauses. This way all declarations defined in a package will be visible for the entity and all architectures assigned to it. Examples Example 1 library IEEE; use IEEE.std_logic_1164.all; entity BCD_Decoder is port ( BCD : in Bit_Vector (2 downto 0); Enable : in Bit; LED : out Std_Ulogic_Vector (3 downto 0)); constant ZERO : Std_Ulogic_Vector(3 downto 0) := "0000"; assert (BCD /= "111") report "BCD = 7 " severity note; end entity BCD_Decoder; The above example illustrates several important issues related to entities. First two lines contain a call to the IEEE library and to the std_logic_1164 package, respectively. These two lines are required because the Std_Ulogic_Vector type used for the output signal LED is not a standard type but it is defined in the mentioned package. If LED would be of Bit_Vector type then the two lines could have been omitted.

7 Module 6 : VHDL 7 The BCD_Decoder identifier, which is following the entity keyword, is a name assigned by the designer to the entity. Note that this name is repeated at the very end of the entity. The above listed entity contains the specification of ports only. In this case there are two inputs (BCD and Enable) and one output (LED). The mode for each of them is supported after a colon and is followed by a specification of the signal's type. See ports for more details on modes and types of ports. The Declarative part of the above entity contains two declarations: constant and assert statements. The constant introduced here will be visible in all architectures of the BCD_Decoder entity. This type of a declaration makes sense if there are more than one such architectures. Otherwise, it might be better to place it in the architecture section to make the entity more clear. See constant for more details on constants. The assert statement is a concurrent statement which will be active whenever any of the BCD_Decoder architectures is active. This particular statement will generate a Message listed in the report clause, whenever BCD will be equal to "111" ("BCD = 7"). Note that the condition in the assert statement should be interpreted as "if not condition - then report". Turn to assert for more information on this topic. Important Notes The VHDL Language Reference Manual uses the name design entity for a complete specification of the design, i.e. both its interface (entity unit) and behaviour or structure (architecture unit). Therefore entity and design entity are not the same concepts! The identifier for an entity must conform to VHDL identifier rules; it must start with a letter followed by an arbitrary combination of letters, digits and underline symbols. While it is not necessary to repeat the name of an entity at the end of the declaration, it is strongly recommended to do it for the sake of clarity of the description; for the same reason it is advised to add the entity keyword between the end and the entity name. It is possible to write an entity without any generics, ports and passive statements. Example :Entity and Architecture Descriptions A circuit description consists of two parts: the interface (defining the I/O ports) and the body. In VHDL, the entity corresponds to the interface and the architecture describes the behavior. Entity Declaration The I/O ports of the circuit are declared In the entity. Each port has a name, a mode (in, out, inout or buffer) and a type (ports A, B, C, D, E in the Example 6-1).

8 Module 6 : VHDL 8 Note that types of ports must be constrained, and not more than onedimensional array types are accepted as ports. Architecture Declaration Internal signals may be declared in the architecture. Each internal signal has a name and a type (signal T in Example 6-1). Example 6-1 Entity and Architecture Declaration Library IEEE; use IEEE.std_logic_1164.all; entity EXAMPLE is port ( A,B,C : in std_logic; D,E : out std_logic ); end EXAMPLE; architecture ARCHI of EXAMPLE is signal T : std_logic;... end ARCHI; Component Instantiation Structural descriptions assemble several blocks and allow the introduction of hierarchy in a design. The basic concepts of hardware structure are the component, the port and the signal. The component is the building or basic block. A port is a component I/O connector. A signal corresponds to a wire between components. In VHDL, a component is represented by a design entity. This is actually a composite consisting of an entity declaration and an architecture body. The entity declaration provides the "external" view of the component; it describes what can be

9 Module 6 : VHDL 9 seen from the outside, including the component ports. The architecture body provides an "internal" view; it describes the behavior or the structure of the component. The connections between components are specified within component instantiation statements. These statements specify an instance of a component occurring inside an architecture of an other component or the circuit. Each component instantiation statement is labeled with an identifier. Besides naming a component declared in a local component declaration, a component instantiation statement contains an association list (the parenthesized list following the reserved word port map) that specifies which actual signals or ports are associated with which local ports of the component declaration. Example 6-2 gives the structural description of a half adder composed of four nand2 components. Example 6-2 Structural Description of a Half Adder entity NAND2 is port ( A,B : in BIT; Y : out BIT ); end NAND2; architecture ARCHI of NAND2 is Y <= A nand B; end ARCHI; entity HALFADDER is port ( X,Y : in BIT; C,S : out BIT ); end HALFADDER;

10 Module 6 : VHDL 10 architecture ARCHI of HALFADDER is component NAND2 port ( A,B : in BIT; Y : out BIT ); end component; for all : NAND2 use entity work.nand2(archi); signal S1, S2, S3 : BIT; NANDA : NAND2 port map (X,Y,S3); NANDB : NAND2 port map (X,S3,S1); NANDC : NAND2 port map (S3,Y,S2); NANDD : NAND2 port map (S1,S2,S); C <= S3; end ARCHI; The synthesized top level netlist is shown in the following figure. Figure 6-1 Synthesized Top Level Netlist

11 Module 6 : VHDL 11 Component Configuration Associating an entity/architecture pair to a component instance provides the means of linking components with the appropriate model (entity/architecture pair). XST supports component configuration in the declarative part of the architecture: for instantiation_list: component_name use LibName.entity_Name(Architecture_Name); Following example shows how to use a configuration clause for component instantiation. The example contains the following "for all" statement: for all : NAND2 use entity work.nand2(archi); This statement indicates that all NAND2 components will use the entity NAND2 and Architecture ARCHI. Note When the configuration clause is missing for a component instantiation, XST links the component to the entity with the same name (and same interface) and the selected architecture to the most recently compiled architecture. If no entity/architecture is found, a black box is generated during the synthesis. Generic Parameter Declaration Generic parameters may also be declared in the entity declaration part. An example use of generic parameters would be setting the width of the design. In VHDL, describing circuits with generic ports has the advantage that the same component can be repeatedly instantiated with different values of generic ports as shown in Example 6-3. Example : Generic Instantiation of Components Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity addern is generic (width : integer := 8); port (A,B : in std_logic_vector (width-1 downto 0);

12 Module 6 : VHDL 12 Y : out std_logic_vector (width-1 downto 0)); end addern; architecture bhv of addern is Y <= A + B; end bhv; Library IEEE; use IEEE.std_logic_1164.all; entity top is port (X, Y, Z : in std_logic_vector (12 downto 0); A, B : in std_logic_vector (4 downto 0); S :out std_logic_vector (16 downto 0) ); end top; architecture bhv of top is component addern generic (width : integer := 8); port (A,B : in std_logic_vector (width-1 downto 0); Y : out std_logic_vector (width-1 downto 0)); end component; for all : addern use entity work.addern(bhv); signal C1 : std_logic_vector (12 downto 0); signal C2, C3 : std_logic_vector (16 downto 0);

13 Module 6 : VHDL 13 U1 : addern generic map (n=>13), port map (X,Y,C1); C2 <= C1 & A; C3 <= Z & B; U2 : addern generic map (n=>17), port map (C2,C3,S); end bhv; Architecture Modeling styles A body associated with an entity declaration to describe the internal organization or operation of a design entity. An architecture body is used to describe the behavior, data flow, or structure of a design entity. Simplified Syntax architecture architecture_name of entity_name is architecture_declarations concurrent_statements end [ architecture ] [ architecture_name ]; Description Architecture assigned to an entity describes internal relationship between input and output ports of the entity. It consists of two parts: declarations and concurrent statements. First (declarative) part of an architecture may contain declarations of types, signals, constants, subprograms (functions and procedures), components, and groups. See respective topics for details.

14 Module 6 : VHDL 14 Concurrent statements in the architecture body define the relationship between inputs and outputs. This relationship can be specified using different types of statements: concurrent signal assignment, process statement, component instantiation, concurrent procedure call, generate statement, concurrent assertion statement and block statement. It can be written in different styles: structural, dataflow, behavioral (functional) or mixed. The description of a structural body is based on component instantiation and generate statements. It allows to create hierarchical projects, from simple gates to very complex components, describing entire subsystems. The connections among components are realized through ports. Example 1 illustrates this concept for a BCD decoder. The Dataflow description is built with concurrent signal assignment statements. Each of the statements can be activated when any of its input signals changes its value. While these statements describe the behavior of the circuit, a lot of information about its structure can be extracted form the description as well. Example 2 contains this type of description for the same BCD decoder as in the previous example. The architecture body describes only the expected functionality (behavior) of the circuit, without any direct indication as to the hardware implementation. Such description consists only of one or more processes, each of which contains sequential statements (Example 3). The architecture body may contain statements that define both behavior and structure of the circuit at the same time. Such architecture description is called mixed. Example 1 architecture Structure of Decoder_bcd is signal S: Bit_Vector(0 to 1); component AND_Gate port(a,b:in Bit; D:out Bit); end component; component Inverter port(a:in Bit; B:out Bit); end component; Inv1:Inverter port map(a=>bcd(0), B=>S(0)); Inv2:Inverter port map(a=>bcd(1), B=>S(1)); A1:AND_Gate port map(a=>bcd(0), B=>bcd(1), D=>led(3)); A2:AND_Gate port map(a=>bcd(0), B=>S(1), D=>led(2)); A3:AND_Gate port map(a=>s(0), B=>bcd(1), D=>led(1));

15 Module 6 : VHDL 15 A4:AND_Gate port map(a=>s(0), B=>S(1), D=>led(0)); end Structure; The components Inverter and AND_Gate are instantiated under the names Inv1, Inv2, A1, A2, A3 and A4. The connections among the components are realized by the use of signals S(0), S(1) declared in the architecture's declarative part. Example 2 architecture Dataflow of Decoder_bcd is led(3) <= bcd(0) and bcd(1); led(2) <= bcd(0) and (not bcd(1)); led(1) <= (not bcd(0)) and bcd(1); led(0) <= (not bcd(0)) and (not bcd(1)); end Dataflow; All the four statements here are executed concurrently and each of them is activated individually when any of its input signals changes its value. Example 3 architecture procedural of Decoder_bcd is signal S: bit_vector (3 downto 0); P1: process (bcd, S) case bcd is when "00" => S <= "0001" after 5 ns; when "01" => S <= "0010" after 5 ns; when "10" => S <= "0100" after 5 ns; when "11" => S <= "1000" after 5 ns; end case; led <= S; end process; end procedural; The clause "after 5 ns" here allows to introduce time delay of the circuit. The assignment of a new value to the led signal will be done only after 5 nanoseconds of the simulated time.

16 Module 6 : VHDL 16 Example 4 architecture Mixed of Decoder_bcd is signal S: Bit_Vector(0 to 2); component Inverter port(a: in Bit; B: out Bit); end component; Inv1: Inverter port map (A=>bcd(0), B=>S(0)); Inv2: Inverter port map (A=>bcd(1), B=>S(1)); P: process (S, bcd) led(0) <= S(0) and S(1) after 5 ns; led(1) <= S(0) and bcd(1) after 5 ns; led(2) <= bcd(0) and S(1) after 5 ns; led(3) <= bcd(0) and bcd(1) after 5 ns; end process; end Mixed; Above, two Inverter component instantiation statements define the circuit responsible for determining the value of the signal S. This signal is read by behavioral part i.e. the process statement P. In this process, the values computed by the and operation are assigned to the led output port. Important Notes Single entity can have several architectures, but architecture cannot be assigned to different entities. Architecture may not be used without an entity. All declarations defined in an entity are fully visible and accessible within each architecture assigned to this entity. Different types of statements (i.e. processes, blocks, concurrent signal assignments, component instantiations, etc.) can be used in the same architecture Concurrent and Sequential statements These statements are for use in Architectures. Concurrent Statements block statement process statement

17 Module 6 : VHDL 17 concurrent procedure call statement concurrent assertion statement concurrent signal assignment statement conditional signal assignment statement selected signal assignment statement component instantiation statement generate statement block statement Used to group concurrent statements, possibly hierarchically. label : block [ ( guard expression ) ] [ is ] [ generic clause [ generic map aspect ; ] ] [ port clause [ port map aspect ; ] ] [ block declarative items ] concurrent statements end block [ label ] ; clump : block A <= B or C; D <= B and not C; end block clump ; maybe : block ( B'stable(5 ns) ) is port (A, B, C : inout std_logic ); port map ( A => S1, B => S2, C => outp ); constant delay: time := 2 ns; signal temp: std_logic; temp <= A xor B after delay; C <= temp nor B; end block maybe; process statement Used to do have sequential statements be a part of concurrent processing. label : process [ ( sensitivity_list ) ] [ is ] [ process_declarative_items ] sequential statements

18 Module 6 : VHDL 18 end process [ label ] ; -- input and output are defined a type 'word' signals reg_32: process(clk, clear) if clear='1' then output <= (others=>'0'); elsif clk='1' then output <= input after 250 ps; end if; end process reg_32; -- assumes use IEEE.std_logic_textio.all printout: process(clk) -- used to show state when clock raises variable my_line : LINE; -- not part of working circuit if clk='1' then write(my_line, string'("at clock ")); write(my_line, counter); write(my_line, string'(" PC=")); write(my_line, IF_PC); writeline(output, my_line); counter <= counter+1; end if; end process printout; process_declarative_items are any of: subprogram declaration subprogram body type declaration subtype declaration constant, object declaration variable, object declaration file, object declaration alias declaration attribute declaration attribute specification use clause group template declaration group declaration

19 Module 6 : VHDL 19 BUT NOT signal_declaration, all signals must be declared outside the process. sig1 <= sig2 and sig3; -- considered here as a sequential statement -- sig1 is set outside the process upon exit or wait A process may be designated as postponed in which case it starts in the same simulation cycle as an equivalent non postponed process, yet starts after all other nonpostponed processes have suspended in that simulation cycle. concurrent procedure call statement A sequential procedure call statement may be used and its behavior is that of an equivalent process. [ label : ] [ postponed ] procedure name [ ( actual_parameters ) ] ; trigger_some_event ; Check_Timing(min_time, max_time, clk, sig_to_test); Note that a procedure can be defined in a library package and then used many places. A process can not be similarly defined in a package and may have to be physically copied. A process as some additional capability not available in a concurrent procedure. concurrent assertion statement A sequential assertion statement may be used and its behavior is that of an equivalent process. [ label : ] [ postponed ] assertion_statement ; concurrent signal assignment statement A sequential signal assignment statement is also a concurrent signal assignment statement. Additional control is provided by the use of postponed and guarded. [ label : ] sequential signal assignment statement [ label : ] [ postponed ] conditional_signal_assignment_statement ; [ label : ] [ postponed ] selected_signal_assignment_statement ;

20 Module 6 : VHDL 20 The optional guarded causes the statement to be executed when the guarded signal changes from False to True. conditional signal assignment statement A conditional assignment statement is also a concurrent signal assignment statement. target <= waveform when choice; -- choice is a boolean expression target <= waveform when choice else waveform; sig <= a_sig when count>7; sig2 <= not a_sig after 1 ns when ctl='1' else b_sig; "waveform" for this statement seems to include [ delay_mechanism ] selected signal assignment statement A selected assignment statement is also a concurrent signal assignment statement. with expression select target <= waveform when choice [, waveform when choice ] ; with count/2 select my_ctrl <= '1' when 1, -- count/2 = 1 for this choice '0' when 2, 'X' when others; component instantiation statement Get a specific architecture-entity instantiated component. part_name: entity library_name.entity_name(architecture_name) port map ( actual arguments ) ; optional (architecture_name) part_name: component_name port map ( actual arguments ) ; Given entity gate is port (in1 : in std_logic ; in2 : in std_logic ;

21 Module 6 : VHDL 21 out1 : out std_logic) ; end entity gate; architecture circuit of gate is... architecture behavior of gate is... A101: entity WORK.gate(circuit) port map ( in1 => a, in2 => b, out1 => c ); -- when gate has only one architecture A102: entity WORK.gate port map ( in1 => a, in2 => b, out1 => c ); -- when order of actual arguments is used A103: entity WORK.gate port map ( a, b, c ); Given an entity entity add_32 is -- could have several architectures port (a : in std_logic_vector (31 downto 0); b : in std_logic_vector (31 downto 0); cin : in std_logic; sum : out std_logic_vector (31 downto 0); cout : out std_logic); end entity add_32; Create a simple component interface component add_32 -- use same port as entity port (a : in std_logic_vector (31 downto 0); b : in std_logic_vector (31 downto 0); cin : in std_logic; sum : out std_logic_vector (31 downto 0); cout : out std_logic); end component add_32; Instantiate the component 'add_32' to part name 'PC_incr' PC_incr : add_32 port map (PC, four, zero, PC_next, nc1); Create a component interface, changing name and renaming arguments component adder -- can have any name but same types in port port (in1 : in std_logic_vector (31 downto 0); in2 : in std_logic_vector (31 downto 0); cin : in std_logic;

22 Module 6 : VHDL 22 sum : out std_logic_vector (31 downto 0); cout : out std_logic); end component adder; Instantiate the component 'adder' to part name 'PC_incr' PC_incr : adder -- configuration may associate a specific architecture port map (in1 => PC, in2 => four, cin => zero, sum => PC_next, cout => nc1); generate statement Make copies of concurrent statements label: for variable in range generate -- label required block declarative items \ optional / concurrent statements -- using variable end generate label ; label: if condition generate -- label required block declarative items \ optional / concurrent statements end generate label ; band : for I in 1 to 10 generate b2 : for J in 1 to 11 generate b3 : if abs(i-j)<2 generate part: foo port map ( a(i), b(2*j-1), c(i, J) ); end generate b3; end generate b2; end generate band; Variables Variable is an object with a single current value. Simplified Syntax

23 Module 6 : VHDL 23 variable variable_name : type; variable variable_name : type := initial_value; Description Variables are objects which store information local to processes and subprograms (procedures and functions) in which they are defined. Their values can be changed during simulation through the variable assignment statements. A variable declaration includes one or more identifiers, a subtype indication and an optional globally static expression defining the initial value for the variable(s). The identifiers specify names for the variables, with one identifier per each variable. The variable can be declared to be of any type or subtype available, either constrained or unconstrained (Example 1). The initial value of a variable can be assigned by a globally static expression. The expression must reference a value of the same type as the variable itself. If the variable is declared to be of a composite type other than a string, Bit_Vector or Std_Logic_Vector, then an aggregate must be used (see Example 2). If the initial value of a variable is not specified, then it is implicitly set as the left bound of the type used. For example for a scalar named T, the default initial value will be T'LEFT. For a composite type, the initial value will be the aggregate consisting of the set of the default values of all the scalar elements. The default initial value for a variable of the access type is null. Variables declared in processes are initialized with their default values, given either explicitly or implicitly, at the start of the simulation. Variables declared in subprograms are initialized each time the subprogram is called. The scope of variables is limited to the process or subprogram they are defined in. The only exception to this rule is a shared variable, which may be shared by multiple processes. Variables can be also declared outside of a procedure or process to be shared between many processes. Shared variables may be declared within an architecture, block, generate statement or package. Declaration of a shared variable must be preceded by the shared keyword (Example 3). Although the Language Reference Manual allows several processes to access a single shared variable it does not define what happens when two or more conflicting

24 Module 6 : VHDL 24 processes try to access the same variable at the same time. Such a situation may lead to unpredictable results and therefore should be avoided. Example 1 type Mem is array (Natural range <>, Natural range <>) of Std_Logic; variable Delay1, Delay2 : Time; variable RAM1: Mem (0 to 1023, 0 to 8); The type Mem is specified as an unconstrained memory (the limit depends on the implementation of the Natural subtype). The variable RAM1, specified in the third line, is based on the Mem type and is defined as a subtype constrained to a 1 KB memory. Both Delay1 and Delay2 variables are of the Time type and are declared in the second line. Example 2 type Mem is array (Natural range <>, Natural range <>) of Std_Logic; variable TempCond : Boolean := true; variable RAM2: Mem (0 to 7, 0 to 7):= (('0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '0', '0', '0', '0', '0')); Both variables are initialized according to the types used. Note the aggregate has been used for initializing RAM2, which is an 88 bit memory. Example 3 shared variable FreeAccess : Boolean := true; The shared variable FreeAccess statement is used to determine whether a shared resource can be accessed at any particular time. However, in real applications a signal

25 Module 6 : VHDL 25 declaration would better serve for this purpose because using signals makes the specification more deterministic. Important Notes Unlike signals, variables have neither history nor future, because according to its definition, each variable has only current value. No checking for the last event, time elapsed since the last event, previous value, etc. can be performed on variables. The non-shared variables are limited to subprograms and processes only. If a value of a variable is read before it is assigned in a clocked process (i.e. where operations are performed when an edge of clock signal is detected) then a register will be synthesized for this variable. A similar situation inside a combinatorial process may lead to generation of a latch. Variables declared in a subprogram are synthesized as combinatorial logic. During simulation variables consume a lot less (even an order of magnitude) memory space than signals. Therefore, it is highly recommended to use them for storage elements (such as memories) instead of signals. Shared variables may cause a system to be non-deterministic and therefore they should be avoided Data objects and data types DATA OBJECTS A data object holds a value of a specified type, created by using object declaration. Every data object belongs to one of the following three classes: An object declaration is used to declare an object, its type, and its class, and optionally assign it a value Constant An object of constant class can hold a single value of a given type. This value is assigned to the object before simulation starts and the value cannot be changed during the course of the simulation. constant RISE_TIME: TIME := 10ns; constant BUS_WIDTH: INTEGER := 8: The first declaration declares the object RISE_TIME that can hold a value of type TIME, with the value assigned at the start of simulation is 10 ns. The second constant declaration declares a constant BUS_WIDTH of type INTEGER with a value of 8. The value of the constant has not been specified, called as a deferred constant and it can appear only inside a package declaration. The complete constant declaration with the associated value must appear in the corresponding package body. constant NO_OF_INPUTS: INTEGER; Variable

26 Module 6 : VHDL 26 An object of variable class can also hold a single value of a given type. However in this case, different values can be assigned to the object at different times using a variable assignment statement. variable COUNT: INTEGER; This results in the creation of a data object called COUNT which can hold integer values and the object COUNT is also declared to be of variable class. variable CTRL_STATUS: BIT_VECTOR(10 downto 0); variable SUM: INTEGER range 0 to 100 := 10; variable FOUND, DONE: BOOLEAN; The first declaration specifies a variable object CTRL_STATUS as an array of 11 elements, with each array element of type BIT. In the second declaration, an explicit initial value has been assigned to the variable SUM, with a an initial value of 10 at the start of simulation. If no initial value is specified for a variable object, a default value is used as an initial value. This default value is T'LEFT, where T is the object type and LEFT is a predefined attribute of a type that gives the leftmost value in the set of values belonging to type T. In the third declaration, the initial values assigned to FOUND and DONE at start of simulation is FALSE. The initial value for all the array elements of CTRL_STATUS is '0' Signal An object belonging to the signal class has a past history of values, a current value, and a set of future values. Future values can be assigned to a signal object using a signal assignment statement. The Signal objects can be regarded as wires in a circuit while variable and constant objects are analogous to their counterparts in a high-level programming language like C or Pascal. Signal objects are typically used to model wires and flip-flops while variable and constant objects are typically used to model the behavior of the circuit. signal CLOCK: BIT; signal DATA_BUS: BIT_VECTOR(0 to 7); signal GATE_DELAY: TIME := 10 ns; The first signal declaration declares the signal object CLOCK of type BIT and gives it an initial value of '0'. The Second Signal Declaration declares the signal object DATA_BUS of type BIT_VECTOR with 1-dimensional array of 8 bits with an intial value of The third signal declaration declares a signal object GATE_DELAY of type TIME that has an initial value of 10 ns. Other Ways to Declare Objects The object declarations that are not created using object declarations are declared as 1. ports of an entity. All ports are signal objects. 2. generics of an entity which are constant objects.

27 Module 6 : VHDL formal parameters of functions and procedures. Function parameters are constant objects or signal objects while procedure parameters can belong to any object class. 4. a file declared by a file declaration. There are two other types of objects that are implicitly declared, these are the indices of a for... loop statement and the generate statement an implicit declaration for the loop index in a for... loop statement for COUNT in 1 to 10 loop SUM := SUM + COUNT; end loop; In this for... loop statement, object COUNT has an implicit declaration of type INTEGER with range I to 10. The object COUNT is created when the loop is first entered and ceases to exist after the loop is exited Data types Every data object in VHDL can hold a value that belongs to a set of values, specified by using a type declaration. A type is a name that has associated with it a set of values and a set of operations. Certain types, and operations that can be performed on objects of these types, are predefined in the language. INTEGER is a predefined type with the set of values being integers in a specific range provided by the VHDL system i.e., from -(2 31-1) to +(2 31-1). Some of the allowable and frequently used predefined operators are +, for addition, -, for subtraction, /, for division, and *, for multiplication. BOOLEAN is predefined type that has the values FALSE and TRUE, and some of its predefined operators are and, or, nor, nand, and not. The declarations for the predefined types of the language are contained in package STANDARD. The language also provides the facility to define new types by using type declarations and also to define a set of operations on these types by writing functions that return values of this new type. Four major categories of types exist. They are 1. Scalar types: Values belonging to these types appear in a sequential order. 2. Composite types: These are composed of elements of a single type (an array type) or elements of different types (a record type). 3. Access types: These provide access to objects of a given type (via pointers). 4. File types: These provide access to objects that contain a sequence of values of a given type. It is possible to derive restricted type, called subtype, from other predefined or userdefined type which is a type with a constraint. The constraint specifies the subset of values for the type. The type is called the base type of the subtype. An object is said to belong to a subtype if it is of the base type and if it satisfies the constraint. Subtype declarations are used to declare subtypes. An object can be declared to either belong to a type or to a subtype.

28 Module 6 : VHDL 28 The set of operations belonging to a subtype is the same as that associated with its base type. Subtypes are useful for range checking and for imposing additional constraints on types. subtype MY_INTEGER is INTEGER range 48 to 156 ; type DIGIT is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ; subtype MIDDLE is DIGIT range '3' to '7' ; MY_INTEGER is a subtype of the INTEGER base type and has a range constraint with values ranging from 48 through 156. DIGIT is a user-defined enumeration type. The last subtype declaration declares a new subtype called MIDDLE whose base type is DIGIT and has the values '3', '4', '5', '6' and '7'. A subtype need not impose a constraint, it can have another name to an already existing type. subtype NUMBER is DIGIT; NUMBER is a subtype with no constraint, its set of values are the same as that for type DIGIT SCALAR TYPES The values belonging to this type are ordered, i.e., relational operators can be used on these values. BIT is a scalar type and the expression '0' < 1' is valid and has the value TRUE. There are four different kinds of scalar types. They are 1. enumeration, 2. integer, 3. physical, 4. floating point. Integer types, floating point types, and physical types are classified as numeric types since the values associated with these types are numeric. Enumeration and integer types are called discrete types since these types have discrete values associated with them. Every value belonging to an enumeration type, integer type, or a physical type has aposition number associated with it. This number is the position of the value in the ordered list of values belonging to that type. ENUMERATION TYPES An enumeration type declaration defines a type that has a set of user-defined values consisting of identifiers and character literals. Type MVL is ('U','0','1','Z);

29 Module 6 : VHDL 29 type MICRO_OP is (LOAD, STORE, ADD, SUB, MUL, DIV); subtype ARITH_OP is MICRO_OP range ADD to DIV; The objects defined for these types can be signal CONTROL_A: MVL; signal CLOCK: MVL range '0' to '1'; -- Implicit subtype declaration. variable IC: MICRO_OP := STORE; -- STORE is the initial value for IC. variable ALU: ARITH_OP; MVL is an enumeration type that has the set of ordered values, 'U', '0', '1', and 'Z'. ARITH_OP is a subtype of the base type MICRO_OP and has a range constraint specified to be from ADD to DIV, i.e., the values ADD, SUB, MUL, and DIV belong to the subtype ARITH_OP. A range constraint can also be specified in an object declaration as shown in the signal declaration for CLOCK; here the value of signal CLOCK is restricted to '0' or 1'. The order of values appearing in an enumeration type declaration defines the lexical order for the values. i.e., when using relational operators, a value is always less than a value that appears to its right in the order. In the MICRO_OP type declaration, STORE < DIV is true, and SUB > MUL is false. Values of an enumeration type also have a position number associated with them. The position number of the leftmost element is 0. The position number of any particular element is one more than the position number of the element to its left. The values of an enumeration type are called enumeration literals. type CAR_STATE is (STOP, SLOW, MEDIUM, FAST); The enumeration literals specified in this type declaration are STOP, SLOW, MEDIUM, and FAST; therefore, objects of type CAR_STATE may be assigned only these values. If the same literal is used in two different enumeration type declarations, the literal is said to be overloaded. Then whenever such a literal is used, the type of the literal is determined from its surrounding context. type MVL is ('U', '0', '1 ', 'Z); --line 1 type TWO_STATE is ('0', '1'); --line 2

30 Module 6 : VHDL variable CLOCK: TWO_STATE; -- line 3 variable LATCH.CTRL: MVL; -- line 4... CLOCK := '0': -- line 5 LATCH.CTRL := LATCH.CTRL xor '0'; -- line 6... Here '0' and '1' are two literals that are overloaded since they appear in both the types, MVL and TWO_STATE. The value '0' being assigned to CLOCK in line 5 refers to the literal in the TWO_STATE type since variable CLOCK is of that type. The value '0' in the expression for LATCH.CTRL refers to the literal in type MVL since the first argument of the xor operator is of type MVL. The predefined enumeration types of the language are CHARACTER, BIT, BOOLEAN, and SEVERITY_LEVEL. Values belonging to the type CHARACTER constitute the 128 characters of the ASCII character set. These values are called character literals and are always written between two single quotes (' '). 'A', '_', '" (the single quote character itself), '3' (the character literal 3) The predefined type BIT has the literals '0' and 1', while type BOOLEAN has {he literals FALSE and TRUE. Type SEVERITY_LEVEL has the values NOTE, WARNING, ERROR, and FAILURE; this type is typically used in assertion statements. INTEGER TYPES An integer type defines a type whose set of values fall within a specified integer range. type INDEX is range 0 to 15; type WORD_LENGTH is range 31 downto 0; subtype DATA_WORD is WORD_LENGTH range 15 downto 0; type MY_WORD is range 4 to 6; object declarations are constant MUX_ADDRESS: INDEX := 5; signal DATA_BUS: DATA_WORD;

31 Module 6 : VHDL 31 INDEX is an integer type that includes the integer values from 0 through 15. DATA_WORD is a subtype of WORD_LENGTH that includes the integer values ranging from 15 through 0. The position of each value of an integer type is the value itself. In the type declaration of WORD_LENGTH, value 31 is at position 31, value 14 is at position 14, and so on. In the declaration of MY_WORD, the position number of values 4,5, and 6, is 4,5, and 6, respectively. Contrast this with the position number of elements of an enumeration type; the position number in case of integer types does not refer to the index of the element in the range, but to its numeric value itself. The bounds of the range for an integer type must be constants or locally static expressions; a locally static expression is an expression that computes to a constant value at compile time (a globally static expression is an expression that computes to a constant value at elaboration time). Values belonging to an integer type are called integer literals. Examples of integer literals are E2 0 98_71_28 Literal 6E2 refers to the decimal value 6 * (10^) = 600. The underscore ( _ ) character can be used freely in writing integer literals and has no impact on the value of the literal; 98_71_28 is same as INTEGER is the only predefined integer type of the language, its range is implementation dependent but must at least cover the range -(2 31-1) to +(2 31-1). FLOATING POINT TYPES A floating point type has a set of values in a given range of real numbers. type TTL_VOLTAGE is range -5.5 to -1.4; type REAL_DATA is range 0.0 to 31.9; object declaration is variable LENGTH: REAL_DATA range 0.0 to 15.9;... variable LI, L2, L3: REAL_DATA range 0.0 to 15.9;

32 Module 6 : VHDL 32 LENGTH is a variable object of type REAL_DATA that has been constrained to take real values in the range 0.0 through 15.9 only. The range constraint was specified in the variable declaration itself. Alternately, it is possible to declare a subtype and then use this subtype in the variable declarations. subtype RD16 is REAL_DATA range 0.0 to 15.9;... variable LENGTH: RD16;... variable Li, L2, L3: RD16; The range bounds specified in a floating point type declaration must be constants or locally static expressions. Floating -point literals are values of a floating point type _1.4_2 Floating point literals differ from integer literals by the presence of the dot (. ) character. Thus 0 is an integer literal while 0.0 is a floating point literal. Floating point literals can also be expressed in an exponential form. The exponent represents a power of ten and the exponent value must be an integer E E+2 Integer and floating point literals can also be written in a base other than 10 (decimal). The base can be any value between 2 and 16. Such literals are called based literals. The exponent represents a power of the specified base. The syntax for a based literal is base # based-value # -- form 1 base # based-value # E exponent form2 2#101_101_000# represents ( )2 = (360) in decimal, 16#FA# represents (FA)16= ( )2 = (250) in decimal, 16#E#E1 represents (E)16* (16^1) = 14* 16= (224) in decimal, 2# # represents (110.01)2 = (6.25) in decimal. The base and the exponent values in a based literal must be in decimal notation.