Digital Design. Chapter 9: Hardware Description Languages
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1 Digital Design Chapter 9: Hardware Description Languages Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by, John Wiley and Sons Publishers, Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) Digital may Design not be posted 2e to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may Copyright make printouts 2010 of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors 1 may obtain PowerPoint source or obtain special use permissions from Wiley see for information.
2 9.1 Introduction A drawing of a circuit, or schematic, contains graphical information about a design c h p DoorOpener f Inverter is above the OR gate, AND gate is to the right, etc. Such graphical information may not be useful for large designs Can use textual language instead si a atap tocontr g Note: Slides with animation are denoted with a small red "a" near the animated items 2
3 Textual Language English Can describe circuit using English text rather than using a drawing Of course, English isn't a good language for a computer to read Need a more precise, computer-oriented language (a) (b) DoorOpener We'll now describe a circuit whose name isdooropener. Inv_1 The external inputs are c, h and p, which are bits. The external output isf, which is a bit. c We assume you know the behavior of these components: An inverter, which has a bit input x, and bit output F. h f n1 A 2-input OR gate, which has inputs x and y, and bit output F. p A 2-input AND gate, which has bit inputs x and y, and bit output F. n2 AND2_1 The circuit has internal wires n1 and n2, both bits. OR2_1 The DoorOpener circuit internally consists of: An inverter named Inv_1, whose input x connectsto external input c, and whose output connectsto n1. A 2-input OR gate named OR2_1, whose inputsconnect to external inputs h and p, and whose output connectsto n2. A 2-input AND gate named AND2_1, whose inputsconnect to n1 and n2, and whose output connectsto external output f. That's all. 3
4 Computer-Readable Textual Language for Describing Hardware Circuits: HDLs Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S. military; Ada-like language Verilog Defined in 1980s by a company; C-like language SystemC Defined in 2000s by several companies; consists of libraries in C++ 4
5 Combinational Logic Description using Hardware Description Languages 9.2 Structure Another word for "circuit" An interconnection of components Key use of HDLs is to describe structure c h p DoorOpener f Note: The term "instantiate" will be used to indicate adding a new copy of a component to a circuit The OR component Three instances of the OR component OR_1 OR_2 OR_3 5
6 Describing Structure in VHDL Entity Defines new item's name & ports (inputs/outputs) std_logic means bit type, defined in ieee library Architecture Describes internals, which we named "Circuit" Declares 3 previouslydefined components Declares internal signals Note "--" comment Instantiates and connects those components c h p DoorOpener Inv_1 n1 n2 AND2_1 OR2_1 (a) We'll now describe a circuit whose name is DoorOpener. The external inputs are c, h and p, which are bits. The external output is f, which is a bit. We assume you know the behavior of these components: An inverter, which has a bit input x, and bit output F. A 2-input OR gate, which has inputs x and y, and bit output F. A 2-input AND gate, which has bit inputs x and y, and bit output F. The circuit has internal wires n1 and n2, both bits. The DoorOpener circuit internally consists of: An inverter named Inv_1, whose input x connects to external input c, and whose output connects to n1. A 2-input OR gate named OR2_1, whose inputs connect to external inputs h and p, and whose output connects to n2. A 2-input AND gate named AND2_1, whose inputs connect to n1 and n2, and whose output connects to external output f. That's all. (b) f l i br ar y i eee; use i eee. st d_l ogi c_1164. al l ; ent i t y Door Opener i s por t ( c, h, p: i n st d_l ogi c; f : out st d_l ogi c ) ; end Door Opener ; ar chi t ect ur e Ci r cui t of Door Opener i s component I nv por t ( x: i n st d_l ogi c; F: out st d_l ogi c) ; end component ; component OR2 por t ( x, y: i n st d_l ogi c; F: out st d_l ogi c) ; end component ; component AND2 por t ( x, y: i n st d_l ogi c; F: out st d_l ogi c) ; end component ; si gnal n1, n2: st d_l ogi c; - - i nt er nal wi r es begi n I nv_1: I nv por t map ( x=>c, F=>n1) ; OR2_1: OR2 por t map ( x=>h, y=>p, F=>n2) ; AND2_1: AND2 por t map ( x=>n1, y=>n2, F=>f ) ; end Ci r cui t ; (c) 6
7 Combinational Behavior Combinational behavior Description of desired behavior of combinational circuit without creating circuit itself e.g., F = c' * (h + p) can be described as equation rather than circuit HDLs support description of combinational behavior 9
8 Describing Combinational Behavior in VHDL Describing an OR gate's behavior Entity defines input/output ports Architecture Process Describes behavior Process "sensitive" to x and y» Means behavior only executes when x changes or y changes Behavior assigns a new value to output port F, computed using built-in operator "or" library ieee; use ieee.std_logic_1164.all; entity OR2 is port (x, y: in std_logic; F: out std_logic ); end OR2; architecture behavior of OR2 is begin process (x, y) begin F <= x or y; end process; end behavior; 10
9 Describing Combinational Behavior in VHDL Describing a custom function's behavior Desired function: f = c'*(h+p) Entity defines input/output ports (not shown) Architecture Process Sensitive to c, h, and p Assigns a new value to output port f, computed using built-in operators "not", "and", and "or" architecture beh of DoorOpener is begin process(c, h, p) begin f <= not(c) and (h or p); end process; end beh; 11
10 Testbench Testbenches Assigns values to a system's inputs, check that system outputs correct values A key use of HDLs is to simulate system to ensure design is correct Testbench Set input values, check output values SystemToTest 16
11 Entity No inputs or outputs Architecture Declares component to test, declares signals Instantiates component, connects to signals Process writes input signals, checks output signal Waits a small amount of time after writing input signals Checks for correct output value using "assert" statement process Testbench in VHDL Set input values, check output values Testbench DoorOpener1 SystemToTest l i br ar y i eee; use i eee. st d_l ogi c_1164. al l ; ent i t y Test bench i s end Test benc h; ar chi t ect ur e behavi or of Test bench i s component Door Opener por t ( c, h, p: i n st d_l ogi c; f : out st d_l ogi c ) ; end component ; si gnal c, h, p, f : st d_l ogi c; begi n Door Opener 1: Door Opener por t map ( c, h, p, f ) ; pr ocess begi n - - case 0 c <= ' 0' ; h <= ' 0' ; p <= ' 0' ; wai t f or 1 ns; asser t ( f =' 0' ) r epor t " Case 0 f ai l ed" ; - - case 1 c <= ' 0' ; h <= ' 0' ; p <= ' 1' ; wai t f or 1 ns; asser t ( f =' 1' ) r epor t " Case 1 f ai l ed" ; - - ( cases 2-6 omi t t ed f r om f i gur e) - - case 7 c <= ' 1' ; h <= ' 1' ; p <= ' 1' ; wai t f or 1 ns; asser t ( f =' 0' ) r epor t " Case 7 f ai l ed" ; wai t ; - - pr oces s does not wake up agai n end pr ocess; end behavi or ; 17
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