Chapter 8: Programmable Processors

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Chapter 8: Programmable Processors Slides to accompany the textbook, First Edition, by, John Wiley and Sons Publishers, 2007. http://www.ddvahid.

1 Chapter 8: Programmable Processors Slides to accompany the textbook, First Edition, by, John Wiley and Sons Publishers, Copyright 2007 Instructors of courses requiring Vahid's textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping Digital this copyright Design notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors 1 may obtain PowerPoint Frank source Vahid or obtain special use permissions from Wiley see for information.

2 Introduction 8.1 Programmable (general-purpose) processor Mass-produced, then programmed to implement different processing tasks Well-known common programmable processors: Pentium, Sparc, PowerPC Lesser-known but still common: ARM, MIPS, 8051, PIC Low-cost embedded processors found in cell phones, blinking shoes, etc. Instructive to design a very simple programmable processor Seatbelt warning light single-purpose processor Real processors can be much more complex e x4 x(t) x(t-1) x(t-2) xt0 c0 xt1 c1 xt2 c2 + + reg 3-tap F filter single-purpose processor s i Seatbelt warning light program Instruction memory I PC 0 Note: Slides with animation are denoted with a small red "a" near the animated items 3-tap F filter program a t a p a r t n o c o t g Other programs Data memory D n-bit 2x1 Register file RF ALU Datapath General-purpose processor 2

3 Basic Architecture Processing generally consists of: Loading some data Transforming that data Storing that data Basic datapath: Useful circuit in a programmable processor Can read/write data memory, where main data exists Has register file to hold data locally Has ALU to transform local data s i Data memory D n-bit 2x1 t a p Register file RF a a r t n o c o t g ALU 8.2 somehow connected to the outside world Datapath 3

4 Basic Datapath Operations Load operation: Load data from data memory to RF ALU operation: Transforms data by passing one or two RF register values through ALU, performing operation (ADD, SUB, AND, OR, etc.), and writing back into RF. Store operation: Stores RF register value back into data memory Each operation can be done in one clock cycle Data memory D Data memory D Data memory D n-bit 2x1 n-bit 2x1 n-bit 2x1 Register file RF Register file RF Register file RF ALU ALU ALU Load operation ALU operation Store operation 4

5 Basic Datapath Operations Q: Which are valid single-cycle operations for given datapath? Move D[1] to RF[1] (i.e., RF[1] = D[1]) A: YES That's a load operation Store RF[1] to D[9] and store RF[2] to D[10] A: NO Requires two separate store operations Add D[0] plus D[1], store result in D[9] A: NO ALU operation (ADD) only works with RF. Requires two load operations (e.g., RF[0]=D[0]; RF[1]=D[1], an ALU operation (e.g., RF[2]=RF[0]+RF[1]), and a store operation (e.g., D[9]=RF[2]) Data memory D Data memory D Data memory D n-bit 2x1 n-bit 2x1 n-bit 2x1 Register file RF Register file RF Register file RF ALU ALU ALU Load operation ALU operation Store operation 5

6 Exercise: Basic Datapath Operations Q: How many cycles does each of the following take for given datapath? Move RF[1] to RF[2] 1 Add D[8] with RF[2] and store the result in RF[4] 2 Add D[8] with RF[1], then add the result with RF[4], and store the final result in D[8] 4 X.S. Hu 6

7 Basic Architecture Control Unit D[9] = D[0] + D[1] requires a sequence of four datapath operations: 0: RF[0] = D[0] 1: RF[1] = D[1] 2: RF[2] = RF[0] + RF[1] 3: D[9] = RF[2] Each operation is an instruction Sequence of instructions program Looks cumbersome, but that's the world of programmable processors Decomposing desired computations into processor-supported operations Store program in Instruction memory reads each instruction and executes it on the datapath PC: Program counter address of current instruction : Instruction register current instruction Instruction memory 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC I Data memory D n-bit 2x1 Register file RF ALU Datapath 7

8 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 0 >1 (a) Fetch RF[0]=D[0] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 1 RF[0]=D[0] (b) Decode "load" Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 1 RF[0]=D[0] Execute Data memory D D[0]: 99 n-bit 2x1 Register file RF R[0]:?? 99 ALU (c) Datapath 8

9 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 1 >2 (a) Fetch RF[1]=D[1} Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 2 RF[1]=D[1] (b) Decode "load" Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 2 RF[1]=D[1] Execute Data memory D D[1]: 102 n-bit 2x1 Register file RF R[1]:?? 102 ALU (c) Datapath 9

10 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 2 >3 (a) Fetch RF[2]=RF[0]+RF[1] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 3 RF[2]=RF[0]+RF[1] (b) Decode "ALU (add)" Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 3 RF[2]=RF[0]+RF[1] Execute Data memory D n-bit 2x1 Register file RF R[2]:?? 201 ALU (c) Datapath

11 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 3 >4 (a) Fetch D[9]=RF[2] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 4 D[9]=RF[2] (b) Decode "store" Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 4 D[9]=RF[2] Execute Data memory D D[9]=?? 201 n-bit 2x1 Register file RF R[2]: 201 ALU (c) Datapath 11

12 Basic Architecture Control Unit Init PC=0 Fetch = I[PC] PC=PC+1 Decode Execute Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] Data memory D PC n-bit 2x1 Register file RF Datapath ALU 12

13 Creating a Sequence of Instructions Q: Create sequence of instructions to compute D[3] = D[0]+D[1]+D[2] on earlier-introduced processor A1: One possible sequence A2: Alternative sequence First load data memory First load D[0] and D[1] and locations into register file add them R[3] = D[0] R[1] = D[0] R[4] = D[1] R[2] = D[1] R[2] = D[2] R[1] = R[1] + R[2] (Note arbitrary register locations) Next, load D[2] and add Next, perform the additions R[2] = D[2] R[1] = R[3] + R[4] R[1] = R[1] + R[2] Finally, store result D[3] = R[1] R[1] = R[1] + R[2] Finally, store result D[3] = R[1] 13

14 Exercise: Creating Instruction Sequences Q1: D[8] = D[8] + RF[1] + RF[4] RF[2] = RF[1] + RF[4] RF[3] = D[8] RF[2] = RF[2] + RF[3] D[8] = RF[2] Q2: RF[2] = RF[1] RF[2] = RF[1] + 0 X.S. Hu 14

15 Number of Cycles Q: How many cycles are needed to execute six instructions using the earlier-described processor? A: Each instruction requires 3 cycles 1 to fetch, 1 to decode, and 1 to execute Thus, 6 instr * 3 cycles/instr = 18 cycles 15

16 Three-Instruction Programmable Processor 8.3 Instruction Set List of allowable instructions and their representation in memory, e.g., Load instruction 0000 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Store instruction 0001 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Add instruction 0010 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2} Instruction memory 0: : : : I Instructions in 0s and 1s machine code opcode operands

17 Program for Three-Instruction Processor Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2} Instruction memoryi 0: : : : Computes D[9]=D[0]+D[1] Data memory D PC n-bit 2 1 Register file RF ALU Datapath 17

18 Program for Three-Instruction Processor Another example program in machine code Compute D[5] = D[5] + D[6] + D[7] 0: // RF[0] = D[5] 1: // RF[1] = D[6] 2: // RF[2] = D[7] 3: // RF[0] = RF[0] + RF[1] // which is D[5]+D[6] 4: // RF[0] = RF[0] + RF[2] // now D[5]+D[6]+D[7] 5: // D[5] = RF[0] Load instruction 0000 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Store instruction 0001 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Add instruction 0010 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 18

19 Assembly Code Machine code (0s and 1s) hard to work with Assembly code Uses mnemonics Load instruction MOV Ra, d specifies the operation RF[a]=D[d]. a must be 0,1,..., or 15 so R0 means RF[0], R1 means RF[1], etc. d must be 0, 1,..., 255 Store instruction MOV d, Ra specifies the operation D[d]=RF[a] Add instruction ADD Ra, Rb, Rc specifies the operation RF[a]=RF[b]+RF[c] Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] 0: : : : : MOV R0, 0 1: MOV R1, 1 2: ADD R2, R0, R1 3: MOV 9, R2 machine code assembly code 19

20 Exercise: Creating Assembly Code Q1: D[8] = D[8] + RF[1] + RF[4] RF[2] = RF[1] + RF[4] Add R2, R1, R4 RF[3] = D[8] MOV R3, 8 RF[2] = RF[2] + RF[3] Add R2, R2, R3 D[8] = RF[2] MOV 8, R2 Q2: RF[2] = RF[1] RF[2] = RF[1] + 0 MOV R1, 0?? X.S. Hu 20

21 Control-Unit and Datapath for Three-Instruction Processor To design the processor, we can begin with a high-level state machine description of the processor's behavior Init PC=0 Fetch =I[PC] PC=PC+1 Decode op=0000 op=0001 op=0010 Load RF[ra]=D[d] Store D[d]=RF[ra] Add RF[ra] = RF[rb]+ RF[rc] 21

22 Control-Unit and Datapath for Three-Instruction Processor Create detailed connections among components Load Init PC=0 RF[ra]=D[d] Fetch Decode Store D[d]=RF[ra] =I[PC] PC=PC+1 op=0000 op=0001 op=0010 Add RF[ra] = RF[rb]+ RF[rc] addr PC clr up rd _ r d R _ l d I P C _ c l r I P C _ i n c data Id I D_addr 8 D_rd D_wr RF_s RF_W_addr 4 RF_W_wr RF_Rp_addr 4 RF_Rp_rd RF_Rq_addr 4 RF_Rq_rd alu_s0 addr rd 256x wr W_data R_data s 1 -bit 2x1 W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd Rp_data 0 D x RF Rq_data s0 A B ALU Datapath 22

23 Control-Unit and Datapath for Three-Instruction Convert high-level state machine description of entire processor to FSM description of controller that uses datapath and other components to achieve same behavior s t a t e s Init PC=0 PC_ clr=1 Load RF[ra]=D[d] D_addr=d D_rd=1 RF_s=1 RF_W_addr=ra RF_W_wr=1 E x e c u t e Fetch Decode op=0000 op=0001 op=0010 Store D[d]=RF[ra] D_addr=d D_wr=1 RF_s=X RF_Rp_addr=ra RF_Rp_rd=1 =I[PC] PC=PC+1 I_rd=1 PC=PC+1 PC_inc=1 _ld=1 Add Add RF[ra] RF[ra] = RF[rb]+ = RF[rb]+ RF[rc] RF_Rp_addr=rb RF[rc] RF_Rp_rd=1 RF_s=0 RF_Rq_addr=rc RF_Rq _rd=1 RF_W_addr=ra RF_W_wr=1 alu_s0=1 Processor addr PC clr up rd data Id _ r d R _ l d I P C _ c l r I P C _ i n c I RF_W_addr RF_W_wr RF_Rp_addr RF_Rp_rd RF_Rq_addr RF_Rq_rd alu_s0 D_addr 8 addr D_rd rd D_wr 256x wr W_dataR_data RF_s s Datapath 1 0 -bit 2x1 W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd D x RF Rp_data Rq_data s0 A B ALU 23

24 Exercise: Understanding the Processor Design (1) Will the correct instruction be fetched if PC is incremented during the fetch cycle? No, since PC will not be updated until the beginning of the next cycle While executing MOV R1, 3, what is the content of PC and at the end of the 1st cycle, 2nd cycle, 3rd cycle, etc.? 1st cycle: PC = 0, = xxxx 2 nd cycle: PC = 1, = I[0] 3 rd cycle: PC = 1, = I[0] What if it takes more than 1 cycle for memory read? Cannot decode until is loaded X.S. Hu 24

25 Exercise: Understanding the Processor Design (2) Q1: D[8] = D[8] + RF[1] + RF[4] I[15]: Add R2, R1, R4 RF[1] = 4 CLK I[]: MOV R3, 8 RF[4] = 5 I[17]: Add R2, R2, R3 D[8] = 7 (n+1) Fetch PC=15 =xxxx (n+2) Decode PC= =2214h (n+3) Execute PC= =2214h RF[2]= xxxxh (n+4) (n+5) Fetch Decode PC= PC=17 =2214h =0308h RF[2]= 0009h (n+6) Execute PC=17 =0308h RF[3]= xxxxh (n+7) Fetch PC=17 =0308h RF[3]= 0007h X.S. Hu 25

26 Exercise: Extending the Three-Instruction Processor Add a instruction: JMP: jump to a location specified by the 12-bit offset RTL: PC = PC+I[15:4] AS: JMP 3 MC: a+b-1 12 addr PC up ld clr rd data Id I D_addr 8 D_rd D_wr RF_s addr rd 256x wr W_data R_data s 1 -bit 2x1 0 D Init PC=0 Fetch Decode =I[PC] PC=PC+1 RF_W_addr 4 RF_W_wr RF_Rp_addr 4 RF_Rp_rd RF_Rq_addr 4 RF_Rq_rd W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd x RF op=0000 op=0001 op=0010 op=1000 Jump alu_s0 Rp_data Rq_data PC_ld =1 s0 A B ALU X.S. Hu Datapath 26

27 A Six-Instruction Programmable Processor 8.4 Let's add three more instructions: Load-constant instruction 0011 r 3 r 2 r 1 r 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 MOV Ra, #c specifies the operation RF[a]=c Subtract instruction 0100 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 SUB Ra, Rb, Rc specifies the operation RF[a]=RF[b] RF[c] Jump-if-zero instruction 0101 ra 3 ra 2 ra 1 ra 0 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 JMPZ Ra, offset specifies the operation PC = PC + offset if RF[a] is 0 27

28 Program for the Six-Instruction Processor Example program Count number of non-zero words in D[4] and D[5] Result will be either 0, 1, or 2 Put result in D[9] _ r d I MOV R0, #0; // initialize result to 0 MOV R1, #1; // constant 1 for incrementing result P C _ l d P C _ c Pl r C _ i n c I R _ l d MOV R2, 4; // get data memory location 4 JMPZ R2, lab1; // if zero, skip next instruction ADD R0, R0, R1; // not zero, so increment result lab1:mov R2, 5; // get data memory location 5 JMPZ R2, lab2; // if zero, skip next instruction ADD R0, R0, R1; //not zero, so increment result lab2:mov 9, R0; // store result in data memory location (a) (b) 28

29 Exercise: More on Programming Q1: Compare the contents of D[4] and D[5]. If equal, D[3] =1, otherwise set D[3]=0. MOV R0, #1 // RF[0] = 1 MOV R1, 4 // RF[1] = D[4] MOV R2, 5 // RF[2] = D[5] SUB R3, R1, R2 // RF[3] = RF[1]-RF[2] JMPZ R3, B1 // if RF[3] = 0, jump to B1 SUB R0, R0, R0 // RF[0] = 0 B1: MOV 3, R0 // D[3] = RF[0] X.S. Hu 29

30 Modifications to the Three-Instruction Processor Load-constant instruction 0011 r 3 r 2 r 1 r 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 Subtract instruction 0100 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 Jump-if-zero instruction 0101 ra 3 ra 2 ra 1 ra 0 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 addr PC clr up rd data Id I RF_W_addr RF_W_wr RF_Rp_addr RF_Rp_rd RF_Rq_addr RF_Rq_rd alu_s0 D_addr 8 addr D_rd rd D_wr 256x wr W_dataR_data RF_s s Datapath 1 0 -bit 2x1 W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd D x RF Rp_data Rq_data s0 A B ALU X.S. Hu 30

31 Extending the Control-Unit and Datapath 1: The load constant instruction requires that the register file be able to load data from [7..0], in addition to data from data memory or the ALU output. Thus, we widen the register file s multiplexer from 2x1 to 3x1, add another mux control signal, and also create a new signal coming from the controller labeled RF_W_data, which will connect with [7..0]. + 2: The subtract instruction requires that we use 3ban ALU capable of subtraction, so we add another a+b-1 ALU control signal. 3: The jump-if-zero instruction requires that we be able to detect if a register is zero, and that we be able to add [7..0] to the PC. 3a: We insert a datapath component to detect if the register file s Rp read port is all zeros (that component would just be a NOR gate). 3b: We also upgrade the PC register so it can be loaded with PC plus [7..0]. The adder used for this also subtracts 1 from the sum, to compensate for the fact that the Fetch state already added 1 to the PC. ld addr PC _ r d I clr up [7..0] rd P C _ c Pl r P C _ l d C _ i n c I R _ l d data Id D_addr D_rd D_wr RF_W_addr RF_Rp_addr RF_Rq_addr RF_Rp_zero 1 8 RF_W_data 1 RF_s1 RF_s0 alu_s1 alu_s a =0 addr rd 256x wr W_data R_data Datapath 2 s1 s0 1 -bit 3x1 W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd Rp_data s1 s0 0 A B ALU D x RF Rq_data s s ALU operation pass A through A+B A-B 31

32 FSM for the Six-Instruction Processor Init PC_clr=1 Fetch I_rd=1 PC_inc=1 _ld=1 Decode op=0000 op=0001 op=0010 op=0011 op=0100 op=0101 Load D_addr=d D_rd=1 RF_s1=0 RF_s0=1 RF_W_addr=ra RF_W_wr=1 Store D_addr=d D_wr=1 RF_s1=X RF_s0=X RF_Rp_addr=ra RF_Rp_rd=1 Add RF_Rp_addr=rb RF_Rp_rd=1 RF_s1=0 RF_s0=0 RF_Rq_add=rc RF_Rq_rd=1 RF_W_addr_ra RF_W_wr=1 alu_s1=0 alu_s0=1 RF_s1=1 RF_s0=0 RF_W_addr=ra RF_W_wr=1 Subtract RF_Rp_addr=rb RF_Rp_rd=1 RF_s1=0 RF_s0=0 RF_Rq_addr=rc RF_Rq_rd=1 RF_W_addr=ra RF_W_wr=1 alu_s1=1 alu_s0=0 RF_Rp_zero Jump-if-zero RF_Rp_addr=ra RF_Rp_rd=1 R F _ R p _ z e r o Loadconstant Jump-ifzero-jmp PC_ld=1? RF_Rp_zero' R F _ R p _ z e r o 32

33 More on Processor Implementation (1) Decode op=0000 op=0001 op=0010 op=0011 op=0100 op=0101 Load Store Add Loadconstant Subtract Jump-if-zero D_addr=d D_rd=1 RF_s1 =0 RF_s0 =1 RF_W_addr=ra RF_W_wr=1 D_addr=d D_wr=1 RF_s1 =X RF_s0 =X RF_Rp_addr=ra RF_Rp_rd=1 RF_Rp_addr=rb RF_Rp_rd=1 RF_s1 =0 RF_s0 =0 RF_Rq_add=rc RF_Rq_rd=1 RF_W_addr_ra RF_W_wr=1 alu_s1 =0 alu_s0 =1 RF_s1=1 RF_s0=0 RF_W_addr=ra RF_W_wr=1 RF_Rp_addr=rb RF_Rp_rd=1 RF_s1=0 RF_s0=0 RF_Rq_addr=rc RF_Rq_rd=1 RF_W_addr=ra RF_W_wr=1 alu_s1=1 alu_s0=0 RF_Rp_zero RF_Rp_addr=ra RF_Rp_rd=1 Jump-ifzero-jmp PC_ld=1? RF_Rp_zero' X.S. Hu 33

34 More on Processor Implementation (2) + a+b-1 ld addr PC clr up [7..0] rd data Id [7:0] D_addr D_rd D_wr RF_W_data RF_s1 RF_s addr rd wr W_data 2 s1 s0 256 x R_data 1 -bit 3 x 1 0 D RF_Rp_s [11:8] [7:4] [11:8] [3:0] RF_W_addr RF_Rp_addr RF_Rq_addr W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd x RF? RF_Rp_zero alu_s1 alu_s0 =0 Datapath Rp_data s1 s0 A ALU Rq_data B X.S. Hu 34

35 What is the Problem?? X.S. Hu 35

36 Further Extensions to the Programmable 8.5 Processor Typical processor instruction set will contain dozens of data movement (e.g., loads, stores), ALU (e.g., add, sub), and flow-of-control (e.g., jump) instructions Extending the control-unit/datapath follows similarly to previously-shown extensions Input/output extensions Certain memory locations may actually be external pins e.g, D[240] may represent 8-bit input I0, D[255] may represent 8-bit output P7 addr rd wr 0: 1: 2: 239: 240: 241: 248: 255: 256x D W_data R_data I0 I1 P0 P7 36

Program using I/O Extensions Recall Chpt 1 Desired motion-at-night detector C-Program Example Programmed microprocessor Custom designed digital circuit Microprocessors a common choice to implement a

37 Program using I/O Extensions Recall Chpt 1 Desired motion-at-night detector C-Program Example Programmed microprocessor Custom designed digital circuit Microprocessors a common choice to implement a digital system Easy to program Cheap (as low as $1) Available now M r o r o c I0 I1 I2 I3 I4 I5 I6 I7 p P0 P1 P2 P3 P4 P5 P6 P7 void main() { while (1) { P0 = I0 &&!I1; // F = a and!b, } } 1 a 0 1 b 0 1 F 0 6:00 7:057:06 9:009:01 time 37

38 Program Using Input/Output Extensions Underlying assembly code for C expression I0 &&!I1. 0: MOV R0, 240 // move D[240], which is the value at pin I0, into R0 1: MOV R1, 241 // move D[241], which is that value at pin I1, into R1 2: NOT R1, R1 // compute!i1, assuming existence of a complement instruction 3: AND R0, R0, R1 // compute I0 &&!I1, assuming an AND instruction 4: MOV 248, R0 // move result to D[248], which is pin P0 256x D void main() { while (1) { P0 = I0 &&!I1; // F = a and!b, } } addr rd wr 0: 1: 2: 239: 240: 241: 248: I0 I1 P0 255: P7 W_data R_data 38

39 Chapter Summary Programmable processors are widely used Easy availability, short design time Basic architecture Datapath with register file and ALU with PC,, and controller Memories for instructions and data fetches, decodes, and executes Three-instruction processor with machine-level programs Extended to six instructions Real processors have dozens or hundreds of instructions Extended to access external pins Modern processors are far more sophisticated Instructive to see how one general circuit (programmable processor) can execute variety of behaviors just by programming 0s and 1s into an instruction memory 39

40 Generic Computer Organization Stored Program Machine (vonneumann Model) Instructions are represented as numbers Programs in memory are read or written just as normal data Data Memory Register Data Path Program Memory Control Logic (Interprets the ISA) Clock Program Counter X.S. Hu 40

41 Memory Organization Two main memory organizations: HARVARD ARCHITECTURE PRINCETON ARCHITECTURE Instruction Memory CPU Data Memory CPU Instruction and Data Memory X.S. Hu 41

42 What to Come Next Introduction MIPS Aeembly & instr. set A very simple processor Performance, costs... MIPS Organization Computer implementation X.S. Hu Memory hierarchy Pipelining 42

CSE140L: Components and Design Techniques for Digital Systems Lab. RTL design. Tajana Simunic Rosing. Source: Vahid, Katz

CSE140L: Components and Design Techniques for Digital Systems Lab RTL design Tajana Simunic Rosing Source: Vahid, Katz 1 Lab #4 due next week Outline Report due at the beginning of class (2pm) Demo hours