VHDL Quick Start. Edward Gatt

Transcription

1 VHDL Quick Start Edward Gatt

2 Modeling Digital Systems VHDL is for writing models of a system Reasons for modeling requirements specification design needs to meet specifications which maybe incomplete or ambiguous and formal model is necessary to communicate requirements formal modeling useful to communicate understanding of the function to the user. designer cannot predict all uses of the system. therefore presents model to user to check it against set of inputs also useful in documentation Edward Gatt VHDL 2

3 Modeling Digital Systems Reasons for modeling testing using simulation and formal verification - systems can be designed from subsystems each with its own model of behaviour. compare outputs/inputs froom circuit to simulation if they coincide the design is fine otherwise need re-designing process can be reiterated until we arrive at the bottom level in the design hierarchy and the manufactured product can be verified to meet specifications synthesis modeling allows automatic synthesis of circuits function is translated to circuitry saving human costs Edward Gatt VHDL 3

4 Modeling Digital Systems Goal most reliable design process, with minimum cost and time allows optimisation normally speed vs gate count compromise avoid design errors! Edward Gatt VHDL 4

5 Domains and Levels of Modeling Structural Functional high level of abstraction low level of abstraction Geometric Y-chart due to Gajski & Kahn Edward Gatt VHDL 5

6 Domains and Levels of Modeling Structural Functional Algorithm (behavioral) Register-Transfer Language Boolean Equation Differential Equation Geometric Y-chart due to Gajski & Kahn Edward Gatt VHDL 6

7 Domains and Levels of Modeling Behavioural Model - Function of the entire system may be described by an algorithm similar to programming eg. loop for each data input loop read the value on the input scale the value using a scale factor end loop wait for 10 ms; end loop; Edward Gatt VHDL 7

8 Domains and Levels of Modeling Register-Transfer Level (RTL) Storage of data is represented using register variables and transformations are represented by arithmetic and logical operations eg. MAR PC, memory_read 1 PC PC + 1 wait until ready = 1 IR memory_data memory_read 0 Boolean Algebra Truth Tables Differential Equations Transistor Behaviour Edward Gatt VHDL 8

9 Domains and Levels of Modeling Structural Processor-Memory Switch Functional Register-Transfer Gate Transistor Geometric Y-chart due to Gajski & Kahn Edward Gatt VHDL 9

10 Domains and Levels of Modeling Processor Memory Switch (PMS) Describing a system as interconnections of Processing Elements Memory Components Input/Output Devices Processor Interconnection Switch Memory Input/Outputs PMS Model for a Controller Edward Gatt VHDL 10

11 Domains and Levels of Modeling Register Transfer Level Register-Transfer- Level for Controller System can then be translated to gates and transistor implementation Edward Gatt VHDL 11

12 Domains and Levels of Modeling Structural Functional Polygons Sticks Standard Cells Floor Plan Geometric Y-chart due to Gajski & Kahn Edward Gatt VHDL 12

13 Domains and Levels of Modeling Floor Planning Reset VSS_Osc ADC [0..3] CAN OSC VDD_Osc NC Capa NC VDD PortA PortB VSS NC PortC NC Edward Gatt VHDL 13

14 Domains and Levels of Modeling Geometric Level of Abstraction Standard Library Cells are used to implement the Registers and Data Transformation Units and must be placed in the areas allocated in the Chip Floor Plan Stick Diagrams Use of Stick Diagrams to Implement Gate Layout Floorplanning Edward Gatt VHDL 14

15 Domains and Levels of Modeling Geometric Level of Abstraction Polygons for Layout Masks Edward Gatt VHDL 15

16 Digital Circuit Design Circuit Design Schematic Entry HDL State Diagrams VHDL Verilog 16

17 VHDL VHDL or VHSIC Hardware Description Language is commonly used as a design-entry language for field-programmable gate arrays and applicationspecific integrated circuits in electronic design automation of digital circuits. VHDL is a fairly general-purpose language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a test bench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). 17

18 VHDL VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). When a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip. To start coding in VHDL, one needs a simulation tool. While very few open source VHDL simulators exist today, most commercial vendors offer free, but often limited, versions of their software. Furthermore, it is highly recommended to use a synthesis tool even when you do not plan to test your code on real hardware. The reason for this is that you can often see the graphical representation (i.e. gates) of your code after synthesis. Seeing what kind of hardware correspond to your code is a very important step in learning any HDL and becoming a good designer. 18

19 Design Flow Design Entry Functional Simulation Library Elements Vendor Synthesis Schematic {Basic Gates; Flip Flop; Complex Gates} Place and Route {Parasitic Cap Extraction} Post Layout Simulation {Check Timing Constraints} 19

20 VHDL Architectures VHDL architectures are divided into two main categories: structural: with full circuit details {netlist form} functional: description of the functionality of the circuit no need of circuit details 20

21 Constructs in VHDL There are three main constructs in VHDL: Component Declaration Component Instantiation Component Configuration 21

22 Component Declaration Define Component name and input/output ports A B component component_name port ( A,B: In BIT; Y: Out BIT); end component component_name Y More versatile types Can have different values other than {1,0} VHDL logic types: e.g u,w,x,z u unresolved BIT {1,0} z tri-state BIT_VECTOR x don t care STD_LOGIC STD_LOGIC_VECTOR 22

23 Component Instantiation Instance = occurrence component port names A1 B1 signal names signal names have to be declared before hand A B Y Y1 These statements represent the use of a component. They specify: A unique name for each instance of the component How the ports of the component are to be connected to the rest of the signals. 23

24 Component Instantiation component port names A1 B1 signal names A B Y Y1 instance_name: component_name port map (A => A1, B => B1, Y=> Y1); component ports wire/signal names 24

25 Component Configuration Maps component instantiations to pre-compiled VHDL library design units. Component Configurations are named to allow multiple configurations to exist for a single design, allowing design alternatives and modifications to be explored in parallel. ALL refers to all instances configuration config_name of entity_name is for component_label: component_name use entity library_name.entity_name(architecture_name); end for end config_name Low Level vs High level Description 25

26 Example 1: Half Adder Structural VHDL Description Entity Name: Halfadder Architecture Name: Structural 26

27 Example 1: Half Adder Structural VHDL Description entity Halfadder is port (A1,B1: In BIT; Sum,Carry: Out BIT); end Halfadder; architecture structural of Halfadder is component Xor2 port (A,B: IN Bit; Y: OUT Bit); end component; component Nand2 port (A,B: IN Bit; Y: OUT Bit); end component; component declaration in this section the components to be used are declared signal icarry: BIT; 27

28 Example 1: Half Adder Structural VHDL Description begin Gate1: Xor2 port map (A => A1,B => B1,Y => sum); Gate2: Nand2 port map (A => A1,B => B1,Y => icarry); Gate3: Nand2 port map (A => icarry,b => icarry,y => carry); end structural; component instantiation in this section the different components are connected together via the port map 28

29 Example 1: Half Adder Structural VHDL Description configuration Halfadderconfig of Halfadder is for structural entity name for Gate1:Xor2 use entity work.xorgate2(simple); end for; refers to all instances for ALL:Nand2 use entity work.xorgate2(simple); end for; library name architecture name end for; Assume that Xor2 and Nand2 are pre-compiled in library called work. Component Name Entity Name Architecture Name Xor2 XorGate2 simple Nand2 NandGate2 simple component configuration end Halfadderconfig; 29

30 Testing VHDL description using a test bench TB: Testbench HA: Halfadder A DriveA1 A1 Sum Monitorsum B DriveB1 B1 Carry Monitorcarry Entity Name: HalfadderTop Architecture Name: Structural 30

31 Testing VHDL description using a test bench entity HalfadderTop is -- no i/o ports end HalfadderTop; architecture structural of HalfadderTop is component Halfadder is (A1, B1: In BIT; Sum, Carry: Out BIT); end component; component Testbench is (A, B: Out BIT); end component; component declaration Structural VHDL is used for VHDL testing signal declaration signal DriveA1, DriveB1, MonitorSum, MonitorCarry: Bit; continues 31

32 Testing VHDL description using a test bench continues begin HA: Halfadder Requires configuration file & pre-compiled testbench entity port map (A1=>DriveA1,B1=>DriveB1, sum=>monitorsum, Carry=>MonitorCarry); TB: Testbench component instantiation port map (A=>DriveA1,B=>DriveB1); TB: Testbench HA: Halfadder end structural; A B DriveA1 DriveB1 A1 Sum B1 Carry Monitorsum Monitorcarry 32

33 VHDL Functional Description Functional descriptions can be made using: Concurrent VHDL statements Sequential VHDL statements Concurrent VHDL statements: no implied sequence/timing i.e. statements are executed in parallel. Sequential VHDL statements: statements are executed one after the other as in a normal programming language {order is important}. Sequential VHDL statements are identified since they have to be in a process block. 33

34 The Process Block process_label: process (sensitivity list) begin Sequential statements; end process process_label; optional Process A Process B The sensitivity list is a list of signals which will trigger (start) the process. If no sensitivity list exists, then the process will continue to loop indefinitely: in this case the execution is typically controlled by wait statements forming part of the sequential statements in the process block. A process will therefore typically have a sensitivity list or wait statements, but it cannot have both. There can be more than one process running concurrently. However the statements in each process block would be executed sequentially. Changes in the value of any one of the signals in the sensitivity list will cause the process to be executed. The process will continue serial execution until the last statement has been executed. The process then suspends execution until another change occurs in one of the signals referenced in the sensitivity list. 34

35 Example 2: Half Adder Functional VHDL Description library IEEE; use IEEE.std_logic_1164.all; entity Halfadder is port (A1, B1: in std_logic; sum, carry: out std_logic); end Halfadder; Concurrent VHDL Description architecture functional of Halfadder is begin sum <= A1 xor B1; carry <= A1 and B1; end functional; Alternatively: sum <= A1+B1; where sum is a 2-bit vector sum: out std_logic_vector(1 downto 0); 35

36 Example 3: Half Adder Functional VHDL Description library IEEE; use IEEE.std_logic_1164.all; entity Halfadder is port (A1, B1: in std_logic; sum, carry: out std_logic); end Halfadder; Sequential VHDL Description architecture functional of Halfadder is Adder: process (A1,B1) begin sum <= A1 xor B1; carry <= A1 and B1; combinational logic end process Adder; end functional; 36

37 Example 4: Latched Half Adder Functional VHDL Description library IEEE; use IEEE.std_logic_1164.all; entity Halfadder is port (A1, B1: in std_logic; sum, carry: out std_logic); end Halfadder; Sequential VHDL Description architecture functional of Halfadder is Latch_Adder: process (Clk) begin If (Clk = 1 ) then sum <= A1 xor B1; carry <= A1 and B1; end if; sequential logic end process Latch_Adder; end functional; 37

38 VHDL Basic Statements 38

39 Wait Statements Execution of a process suspends when a wait statement is encountered. Execution restarts when the condition of the wait statement is met. Syntax: process block : sequential statements : wait condition : sequential statements end process wrap 39

40 Type of Wait Statements (1) wait wait forever: usually used within a test bench (2) wait on <signal list> Waits for an event on any one of the signals (same purpose as sensitivity list) (3) wait until <condition> Waits until condition becomes true e.g. wait until A = 1 ; (4) wait for <time> e.g. wait for 10ns; {typically this is not supported by synthesis tool} 40

41 Example for Wait Statements Adder: process begin sum <= A xor B; carry <= A and B; wait on A,B; If in the wait statement we remove B, we would require memory to store value of B since a change in it will keep the adder idle -> it becomes a sequential logic circuit. end process Adder; 41

42 If statement If condition then sequential statements elsif condition then sequential statements optional else sequential statements end if; 42

43 Case statement Allows selection of sequential statements to be executed, based on the value of a selection expression. Choice of a case statement must be unique. If not all possible values of the selector expression are listed, an others choice must be included. Example: type select is array (3 downto 0) of BIT; -- defining a new type signal operationselect: select; case operationselect is when 0000 => sequential statements; when 0001 => sequential statements; when others => sequential statements; end case; The NULL statement signifies no operation. It is useful to explicitly show that no action is required for a particular choice in a case statement. e.g. : : when 0101 => NULL; 43

44 Loop Statement Syntax: while condition loop sequential statements; end loop; Boolean condition is checked each time before the loop is executed. If condition is true, loop is executed. If condition is false, execution continues with the next statement after the end loop. 44

45 Generic Loop A loop label is used in this case: Syntax: loop_label: loop sequential statements; end loop; Infinite loop used in conjunction with a wait statement or exit statement exit and next statements can be used to control the flow of a generic loop. Syntax: next loop_label when condition; exit loop_label when condition; The exit statement also terminates the current Iteration and additionally also exists the loop. The next statement terminates the execution of the current loop iteration and starts a subsequent iteration. 45

46 For Loop Specifies a fixed number of iterations of the loop. Loop index does not have to be explicitly declared. Loop index only exists within the loop and disappears as soon as the loop is terminated. Example: for I in 1 to 10 loop factorial = factorial*i; end loop; Index type of enumerated type: Step is always 1 for numeric values Example: type RGB is (Red,Green,Blue); signal rgb_signal: RGB; for RGB_Index in RGB loop -- sequential statements end loop; 46

47 Nested Loops outerloop: For X in 1 to 100 loop innerloop: For Y in 1 to 100 loop : : : exit outerloop when (Y=1 and X=99); : : end loop; end loop; 47

48 Assert Statement Used to verify a condition and report if the condition is violated. The assertion statement will also specify the severity of the condition violation: note, warning, error, failure. Syntax: assert condition report report expression severity severity_level; Example: assert (x < 32) report ( x out of limit ); severity error; This is printed if condition is not true 48

49 Conditional Assignment with selector select signal_name <= value when choice_1; <= value when choice_2; : : <= value when choice_n; <= value when others; The conditional assignment is very similar to a multiplexer implementation. choice_1 choice_2 choice_3 : : choice_n selector signal_name 49

50 Expressions and Operators Highest precedence of evaluation Miscellaneous: abs not Multiplying: * / mod Signing: + Adding: + & {concatenation of 1D arrays} Relational Operators: = /= < <= > >= Logical Operators: and or nand nor xor Lowest precedence of evaluation 50

51 Signals and Variables Signals: used for communication between concurrently executed VHDL blocks will physically map into a wire (or bus). Variables: only valid with sequential code (higher level of abstraction) are local to an individual process or function. Signal Attributes: If s is a signal: s event : returns true if s changed (either or ) current time s last_event: returns the time elapsed since the previous transition on s. 51

52 Code Examples - 1 Edward Gatt VHDL 52

53 Code Examples - 2 Edward Gatt VHDL 53

54 Code Examples -3 Edward Gatt VHDL 54

55 Code Example - 4 Edward Gatt VHDL 55

56 VHDL Process - Timing Edward Gatt VHDL 56

57 Code Example - 5 Edward Gatt VHDL 57

58 Code Example - 6 Edward Gatt VHDL 58

59 Code Example - 7 Edward Gatt VHDL 59

60 Code Example - 8 Edward Gatt VHDL 60

61 Test Bench Code transport delay used to model delays introduced by wiring delays input by a specified time Edward Gatt VHDL 61

62 Timings for Testbench Edward Gatt VHDL 62

63 Code Example - 9 Edward Gatt VHDL 63

64 Code Example 9 (cont/d) Edward Gatt VHDL 64

65 Code Example - 10 Edward Gatt VHDL 65

66 Code Example - 11 Edward Gatt VHDL 66

67 Code Example - 12 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_unsigned.all; entity ALU is port ( Accumulator_in: in STD_LOGIC_VECTOR (7 downto 0); Data_in : in STD_LOGIC_VECTOR (7 downto 0); Opcode_in : in STD_LOGIC_VECTOR (3 downto 0); Result_out : out STD_LOGIC_VECTOR (7 downto 0) ); end ALU; architecture ALU_arch of ALU is begin Main: process(accumulator_in,opcode_in, Data_in) begin case Opcode_in is when "0000" => Result_out <= Data_in; -- result = Data_in when "0001"=> Result_out <= Accumulator_in; -- result = accumulator_in when "0010"=> Result_out <= " "; -- result = accumulator_in + Data_in when "0011"=> Result_out <= " "; -- result = accumulator_in - Data_in when "0100"=> Result_out <= Accumulator_in and Data_in; -- result = accumulator_in and Data_in Edward Gatt VHDL 67

68 Code Example - 12 (cont/d) when "0101"=> Result_out <= Accumulator_in or Data_in; -- result = accumulator_in or Data_in when "0110"=> Result_out <= Accumulator_in xor Data_in; -- result = accumulator_in xor Data_in when "0111"=> Result_out <= not(accumulator_in); -- result = not(accumulator_in) when "1000"=> Result_out <= not(accumulator_in); -- result = not(data_in); when "1001"=> Result_out <= " "; -- result = 0 when "1010"=> Result_out <= " "; -- result = 8 LSBs of ( accumulator_in * Data_in) when "1011"=> Result_out <= " "; -- result = 8 MSBs of ( accumulator_in * Data_in) when "1100"=> Result_out <= accumulator_in nand Data_in; -- result = accumulator_in nand Data_in when "1101"=> Result_out <= accumulator_in nor Data_in; -- result = accumulator_in nor Data_in when "1110"=> Result_out <= accumulator_in xnor Data_in; --result=accumulator_in xnor Data_in when "1111"=> Result_out <= " "; --result=accumulator_in+1 when others => Result_out <="XXXXXXXX"; end case; end process Main; end ALU_arc Edward Gatt VHDL 68

69 Test Bench for ALU library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_unsigned.all; entity alu_tb is port ( Accumulator_out: out std_logic_vector (8 downto 1); Data_out : out std_logic_vector (8 downto 1); Opcode_out : out std_logic_vector (4 downto 1) ); end alu_tb; architecture alu_tb_arch of alu_tb is begin operation_1: PROCESS begin wait for 0ns; Opcode_out <= "0000"; wait for 10 ns; Opcode_out <= "0001"; wait for 10 ns; Opcode_out <= "0010"; wait for 10 ns; Opcode_out <= "0011"; wait for 10 ns; Opcode_out <= "0100"; Edward Gatt VHDL 69

70 Test Bench for ALU (cont/d) wait for 10 ns; Opcode_out <= "0101"; wait for 10 ns; Opcode_out <= "0110"; wait for 10 ns; Opcode_out <= "0111"; wait for 10 ns; Opcode_out <= "1000"; wait for 10 ns; Opcode_out <= "1001"; wait for 10 ns; Opcode_out <= "1010"; wait for 10 ns; Opcode_out <= "1011"; wait for 10 ns; Opcode_out <= "1100"; wait for 10 ns; Opcode_out <= "1101"; wait for 10 ns; Opcode_out <= "1110"; wait for 10 ns; Opcode_out <= "1111"; wait; end PROCESS operation_1; operation_2: PROCESS begin wait for 0ns; Data_out <= " "; wait; end PROCESS operation_2; operation_3: PROCESS begin wait for 0ns; Accumulator_out <= " "; wait; end PROCESS operation_3; end alu_tb_arch; Edward Gatt VHDL 70

71 Top Level for ALU library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_unsigned.all; entity alu_tl is port ( Result : out std_logic_vector (8 downto 1) ); end alu_tl; architecture alu_tl_arch of alu_tl is component alu port ( Accumulator_in: in std_logic_vector (8 downto 1); Data_in: in std_logic_vector (8 downto 1); Opcode_in: in std_logic_vector (4 downto 1); Result_out: out std_logic_vector (8 downto 1) ); end component ; component alu_tb is port ( Accumulator_out: out std_logic_vector (8 downto 1); Data_out: out std_logic_vector (8 downto 1); Opcode_out: out std_logic_vector (4 downto 1) ); end component; Edward Gatt VHDL 71

72 Top Level for ALU (cont/d) signal Accumulator : std_logic_vector(8 downto 1); signal Data : std_logic_vector(8 downto 1); signal Opcode : std_logic_vector(4 downto 1); begin alu_1 : alu port map ( Accumulator_in => Accumulator, Data_in => Data, Opcode_in => Opcode, Result_out => Result ); tb_1 : alu_tb port map ( Accumulator_out => Accumulator, Data_out => Data, Opcode_out => Opcode ); end alu_tl_arch; Edward Gatt VHDL 72

73 Field Programmable Gate Arrays FPGAs are ICs that contain an array of identical blocks with programmable interconnections User can program the functions realised by each logic block and the connections between the blocks FPGAs offer easier design iterations Easier to correct mistakes that creep into the design Prototyping cost is reduced Edward Gatt VHDL 73

74 Disadvantages: FPGAs FPGAs are less dense than traditional gate arrays A lot of resources is spent to achieve programmability Programmable points have resistances and capacitances FPGAs are slower than traditional gate arrays Edward Gatt VHDL 74

75 Organisation of FPGAs The interior of FPGAs typically contain three elements that are programmable: Programmable logic blocks Programmable input/output blocks Programmable routing resources Edward Gatt VHDL 75

76 Organisation of FPGAs Edward Gatt VHDL 76

77 Organisation of FPGAs Arrays of programmable logic blocks are distributed within the FPGA Logic blocks are surrounded by (I/O) interface blocks I/O blocks are on the periphery on the chip They connect the logic signals to the FPGA pins Space between logic blocks are used to route connections between the logic blocks Edward Gatt VHDL 77

78 Programmable Logic Blocks Programmable Logic Blocks are created by using multiplexers, look-up tables, AND-OR or NAND-NAND arrays Programming means changing the input or control signals to the multiplexers, changing look-up table contents or selecting/not selecting particular gates in AND-OR gate blocks For a programmable interconnect, programming means making or breaking specific connections This is required to interconnect various blocks in the chip and to connect specific I/O pins to specific logic blocks Edward Gatt VHDL 78

79 Programmable I/O blocks Programmable I/O blocks denote blocks which can be programmed to be input, output or bidirectional lines They can also be programmed to adjust the properties of their buffers such as inverting/noninverting, tristate, passive pull-ups or even adjust the slew rate Edward Gatt VHDL 79

80 FPGA Programming Technologies Several techniques have been used to achieve the programmable interconnections between FPGAs Static RAM programming technology EPROM/EEPROM/flash programming technology Antifuse programming technology Edward Gatt VHDL 80

81 SDRAM Programming Technology The SDRAM programming technology involves creating reconfigurability by bits stored in SRAM cells The logic blocks, I/O blocks and interconnect can be programmed by using configuration bits stored in SRAM Reconfigurable logic blocks can be easily implemented as look-up tables Problem is that system is volatile Edward Gatt VHDL 81

82 SRAM Programming Technology 16 SRAM cells can implement any 4 variable function Programmable interconnect can also be achieved by SRAM The key idea is to use pass transistors to create switches and then control them using SRAM content SDRAM requires 6 transistors therefore number of transistors to provide a connection is high Write Controlled by Data Pass Transistor Edward Gatt VHDL 82

83 EPROM/EEPROM Programming Technology EPROM cells used to control programmable connections A transistor with 2 gates is used floating gate and control gate Transistor turned off by injecting charge on the floating gate using a high voltage between the control gate and drain of the transistor Charge increases the threshold voltage of the transistor and it switches off Charge can be removed by exposing the floating gate to ultraviolet light Edward Gatt VHDL 83

84 EPROM EPROM technology slower than SRAM EPROM switches have high ON resistance and high static power consumption EEPROM technology is similar to EPROM but removal of gate charge can be done electrically Edward Gatt VHDL 84

85 Antifuse Programming Technology Antifuse programming element changes from open to closed when a high voltage is applied They are often built using dielectric layers between N+ diffusion and polysilicon layers or by amorphous silicon between metal layers Antifuses are normally OFF and put ON when programmed Process is irreversible and not reprogrammable but consumes little area Edward Gatt VHDL 85

86 Programmable Logic Block Arrays LUT-based FPGAs use four-variable look-up tables plus a flip-flop as the basic element and then connect several of them in various topologies Edward Gatt VHDL 86

87 Programmable Logic Block Arrays Some FPGAs use multiplexers as the basic block Any combinational logic can be implemented using multiplexers alone e.g. a 4-to-1 multiplexer can generate any twoinput function If inverted inputs can be provided, the same multiplexer can generate any three-input function Edward Gatt VHDL 87

88 Programmable Interconnects Interconnects in Symmetric Arrray FPGAs General Purpose Interconnect: Switch Matrices provide interconnections between routing wires connected to the switch matrix Edward Gatt VHDL 88

89 Programmable Interconnects Interconnects in Symmetric Arrray FPGAs Direct Interconnects: Many FPGAs provide special connections between adjacent logic blocks. These interconnects are fast as they do not go through the routing matrix Edward Gatt VHDL 89

90 Programmable Interconnects Interconnects in Symmetric Arrray FPGAs Global Lines: For purposes like high fan-out and low-skew clock distribution, most FPGAs provide routing lines that span the entire width of the device/height of the device Interconnects in Row-Based FPGAs: In devices that are row based, there are rows of logic blocks and there are channels of switches to enable connections between logic blocks Edward Gatt VHDL 90

91 Programmable I/O Blocks The I/O pads are connected to programmable input/output blocks, which facilitate connecting the signals from FPGA logic blocks to the external world in desired forms and formats I/O blocks on modern FPGAs allow use of the pin as input and/or output, in direct (combinational) or latched forms, in tristate true or inverted forms and with a variety of I/O standards Edward Gatt VHDL 91