Image Courtesy CS250 Section 3. Yunsup Lee 9/11/09

Transcription

1 CS250 Section 3 Image Courtesy Yunsup Lee 9/11/09

2 Announcements Lab 2: Write and Synthesize a Two-Stage SMIPSv2 Processor is out Lab 2 due on September 24th (Thursday) before class Four late days you can use Tutorial 3: Build, Run, and Write SMIPS Programs Talks about using the SMIPS assembler / compiler / linker Tutorial 4: Simulating Verilog RTL using Synopsys VCS Uses SMIPSv1 as an example Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler Uses SMIPSv1 as an example Next week s (September 18th) office hour is 1pm - 2pm

3 Infrastructure Tool Servers ilinux[1-3].eecs cory353-[(2*n)l].eecs (Notice that l is the lower case of L ) NX server installed on all servers except ilinux[2,3].eecs License Servers Two license servers (Take a look at ~cs250/tools/cs250.bashrc) SVN Server Notice that you need to commit the directory that current-* points

4 Infrastructure Please take care of your tracks... Logout your NX session after done Make sure that you don t have any tools running I will you twice a week if You have a NX session running You have a tool running It s going to be an automated script So if you are actually running something just ignore

5 Lab 1 Feedback Clock constraints change build/dc-syn/constraints.tcl change src/testharness.v always #<clock cycle/2> clk = ~clk; Timing constraints met at synthesis but not after place and route Adding more buffers (e.g., clock buffers) Model is more accurate with extracted parasitics for wires Iterate between synthesis and place and route, topographical mode Min & Max power are the same Circuit too small

6 Lab 1 Feedback Post Synthesis Area dc-syn/current-dc/reports/*.area.rpt Post Synthesis Power dc-syn/current-dc/reports/*.power.rpt Post Place+Route Area icc-par/current-icc/reports/chip_finish_icc.sum UTILIZATION RATIOS / Core Area Total Cell Count / DFFX* Cell Count icc-par/current-icc/reports/chip_finish_icc.sum MASTER INSTANTIATION INFORMATION

7 Lab 1 Feedback Average Power (min, max) pt-pwr/current-pt/reports/vcdplus.power.avg.{min,max}.report Peak Power (min, max) pt-pwr/current-pt/reports/vcdplus.power.time.{min,max}.report

8 Questions Any questions about lab 1?

9 Question 1 Tell me about the toolflow. Big picture What s the order you should go through the build directory?

10 Question 2 What s the difference between the following? vcs-sim-behav vcs-sim-rtl vcs-sim-gl-syn vcs-sim-gl-par Why do we do all these simulations?

11 Question 3 What s the difference between the following? icc-par/current-iccdp icc-par/current-icc

12 Question 4 What else does PrimeTime analyze?

13 Question 5 I want to see the layout of standard cells. What should I do?

14 Lab 2: SMIPSv2 Processor smipstestharness testrig_tohost testrig_fromhost smipsproc imemreq_bits_addr imemreq_val imemresp_bits_data Magic Dual Port Memory dmemreq_bits_rw dmemreq_bits_addr dmemreq_bits_data clk reset dmemreq_val dmemresp_bits_data clk reset

15 Lab 2: Things you need to do Write Verilog smipsproc.v, smipsprocctrl.v smipsprocdpath.v add more modules: for example, register file and ALU Run SMIPSv2 test assembly programs and benchmarks Globally installed stuff ~cs250/install/{smips-tests, smips-bmarks} Local stuff ~cs250/lab2/v-smipsv2-2stage/{smips-tests, smips-bmarks} Complete the multiply benchmark Take a look at vcs-sim-rtl/makefile

16 Lab 2: Things you need to do Stuff that matters in your build directory vcs-sim-rtl, dc-syn, vcs-sim-gl-syn Write two assembly tests and two benchmarks We will run your programs on other people s pipeline Optimize your design We will synthesize your processor with 2ns time constraint Measure your IPC for benchmarks Bonus question - Build your own branch predictor We will post results on the course homepage

17 Lab 2: dc-syn is tricky pc+4 branch jump jr pc_sel PC val +4 Instruction Mem nop killf PC+4 IR ir[15:0] ir[25:0] ir[25:21] ir[20:16] ir[10:6] (shamt) ir[15:0] ir[15:0] Branch TargGen Jump TargGen Reg File Zero Extend Sign Extend rd0 rd1 Branch CondGen 16 zero? eq? neg? alu_fun ALU addr rdata wdata rw val testrig_fromhost wb_sel 31 ir[20:16] ir[15:11] Reg File Data Mem tohost wa_sel rf_wen tohost_en testrig_tohost Decoder Control Signals Fetch Stage Execute Stage

18 Lab 2: dc-syn is tricky Core = Processor + Memory Two makefiles exist Makefile.combinational Synthesizes smipsproc Use this makefile for vcs-sim-gl-syn Makefile.dummy Synthesizes smipscore_synth Use this makefile for critical path analysis Use this makefile for area analysis

19 Lab 2: dc-syn is tricky pc+4 branch jump jr pc_sel PC val +4 Instruction Mem nop killf PC+4 IR ir[15:0] ir[25:0] ir[25:21] ir[20:16] ir[10:6] (shamt) ir[15:0] ir[15:0] Branch TargGen Jump TargGen Reg File Zero Extend Sign Extend rd0 rd1 Branch CondGen 16 zero? eq? neg? alu_fun ALU addr rdata wdata rw val testrig_fromhost wb_sel 31 ir[20:16] ir[15:11] Reg File Data Mem tohost wa_sel rf_wen tohost_en testrig_tohost Decoder Control Signals Fetch Stage Execute Stage

20 Lab 2: dc-syn is tricky pc+4 branch jump jr pc_sel PC +4 Instruction Buffer Mem Delays val Functionally Incorrect! nop killf PC+4 IR ir[15:0] ir[25:0] ir[25:21] ir[20:16] ir[10:6] (shamt) ir[15:0] ir[15:0] Branch TargGen Jump TargGen Reg File Zero Extend Sign Extend rd0 rd1 Branch CondGen 16 zero? eq? neg? alu_fun ALU Reg File addr Data wdata Buffer rdata Mem rw val testrig_fromhost wb_sel 31 ir[20:16] ir[15:11] Delays tohost wa_sel rf_wen tohost_en testrig_tohost Decoder Control Signals Fetch Stage Execute Stage

21 Lab 2: Adding more modules build/vcs-sim-rtl/makefile vclibsrcs vsrcs build/dc-syn/makefile vclibsrcs vsrcs not build/vcs-sim-gl-syn/makefile why?

22 Lab 2: Adding more test programs build/vcs-sim-rtl/makefile global_asm_tests global_bmarks local_asm_tests local_bmarks build/vcs-sim-gl-syn/makefile global_asm_tests global_bmarks local_asm_tests local_bmarks

23 Lab 2: SMIPS Compiler After you compile, first run it on the funcational simulator to make sure it is running as intended to make sure it doesn t have any instructions that aren t SMIPSv2 The Compiler might generate some instructions that aren t SMIPSv2 Keep your memory accesses aligned Make sure you don t use arithmetic that aren t defined e.g., multiply, divide

24 Lab 2: IPC for benchmarks build/vcs-sim-rtl make run-bmarks-perf Bonus question - Build your branch predictor why would this make your IPC better?

25 Lab 2: Misc LAB2_ROOT=`pwd` Notice you should use ` instead of A Latex weirdness - does anyone know how to fix it?