CSE140: Components and Design Techniques for Digital Systems

Transcription

1 CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing

2 Announcements and Outline Check webct grades, make sure everything is there and is correct Pick up graded d homework at TA s or my assistant s t office Discussion session this week on Thursday during class time no prof. office hrs from Wed-Sunday this week due to travel Final exam Tuesday, June th, at 3pm, same location as the class Everything covered in lectures, whole book & all handouts Format: Problems similar to HW and previous exams Multiple choice and/or T/F questions on the assigned reading Discussion session will go over the previous year s final Today s topic: Review and CPU design 2

3 CSE4: Components and Design Techniques for Digital Systems Single Cycle CPU Design Tajana Simunic Rosing 3

4 4 MIPS Single-Cycle Datapath & Control PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend [5-] CONTROL 4

5 CPU Components Combinational logic: Boolean equations, logic gates Multiplexors and decoders : executes arithmetic /logical operations 5

6 2-input, 32-bit Selects one input as the output S I I I 3 M U O 3 I 3 X I M 3 M U O 3 U 32 O I implementation 3 X X S I M U O I 6 X

7 Decoder 2 input, 2 2 = 4 outputs I I 2-to-4 DECODER O O O2 O3 I implementation Translates input into binary number B and turns on output B I I I O3 O2 O O O O O2 O3 7

8 Full 32-bit OP CODE A 32 CarryIn Performs: AND, OR, NOT, ADD, SUB, Overflow Detection, GTE B bit 32 Result Overflow CarryOut 8

9 MSB OP Binvert CarryIn A3 B3 + ADD GTEin = If GTEout =, A B CarryOut xor result GTEout xor 9 overflow

10 Design Example S2 S S Function B-A A-B A+B A xor B A or B A and B

11 CPU Components Combinational logic: Boolean equations, logic gates Multiplexors and decoders : executes arithmetic /logical operations Sequential logic: The clock Storage (memory) elements Counters

12 Determining Clock Frequency 5.4 Frequency limited by longest register-to-register delay Known as critical path If clock is any faster, incorrect data may be stored into register Longest path on right is 2 ns Ignoring wire delays, and register setup and hold times, skew clk a 2 ns delay + c b 2

13 A Circuit May Have Numerous Paths s a Combinational logic d 8 8 c tot_ld tot_clr ld clr tot tot_lt_s n (c) 8 n tot_lt_s 8-bit < 8-bit adder 8 clk s s State register (b) Datapath (a) 3

14 Memory elements: D-Latch Sets SR-latch (Q) to value of D when clock (C) is high; otherwise last Q retained D C Reset Set stores stores C R: reset nor Q Stored state value S: set nor Q D 4

15 Memory elements: Flip-Flop Stores new value of D in Q when C falls, otherwise current stored value of Q is retained: falling edge-triggered clocking methodology C (clock) D (data) C D Q D LATCH Q C2 Q2 D LATCH 2 D2 Q2 Q Q 5

16 Read/Write Register File Input Read Reg #. selects Q for that t set of FFs as output t Input Write Reg # and Value. Write Value goes to each FF. Write Reg # turns on C to only FF, where Value is stored. Clock D E C O D E R O C FF Q D Reg C FF Q Write O Reg # (5 bits) Write Value O3 D Reg C FF Q D Reg 3 3 M U X Read Reg # (5 bits) Read Value 6

17 2-bit Reset/Inc Falling Edge Counter clock inc reset + C Q Bit BIT BIT FF D Q C Q Bit + FF D Q 7

18 CPU Components Combinational logic: Boolean equations, logic gates Multiplexors and decoders : executes arithmetic /logical operations Sequential logic: The clock Storage (memory) elements Counters Datapath and Control: logic block that executes machine language instructions 8

19 Control and Datapath Execute Instruction Set Processor Control Datapath PC R E G I S T E R S Main Memory DEVICES IN PUT OUT PUT Control takes program as input; it interprets each instruction and tells the Datapath to operate on data via, memory and registers 9

20 CPU Components Single Cycle Execution Assumptions: Every machine language instruction happens in Clock Cycle MIPS architecture Microprocessor without interlocked pipeline stages reg-reg architecture: all operands must be in registers (total 24) 3 Instruction Types; each instruction 32 bits long. R-type: all data in registers (most arithmetic and logical) e.g. add $s, $s2, $s3 2. J-type: jumps and calls e.g. j Label; 3. I-type: branches, memory transfers, constants e.g. beq $s, $s2, Label; lw $s, 32($s2) add $s, $s, $s

21 4 PC [3-] When an assembly language program is run: [3-26] REG_DST BRANCH CON TROL Is assembled, REG_ linked, loaded into instruction MEM_,MEM_ memory _SRC _OP PC initialized to the address of the first instruction [25-2] EM_TO_REG REGISTER [2-6] the PC is really a 32-bit register REGISTER 2 ZERO INST[5-] REGISTERS by separate adders counting is done REGISTER << 2 rest of clock cycle used to fetch/execute I, update PC ME [5-] Sign Extend [5-] CONTROL 2

22 R-type Instruction: reg-reg ops (e.g. add, and) Tells operation to be performed Tells specific variant of operation (e.g. add/sub have same opcode) R-type Instruction OPCODE = RS shamt RT RD FUNCT = 32 or ADD $S, $S2, $S3 ADD RD, RS, RT Source Register (attached to Read Register input) Source Register 2 (attached dt to Read Register 2 input) Shift amount (for sll, srl etc.) Destination Register (attached to Write Register input) 22

23 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step (R-type): Fetch instruction and advance PC [5-] CONTROL 23

24 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step 2 (R-type): Read two registers and set control signals [5-] CONTROL 24

25 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step 3 (R-type): Perform the operation [5-] CONTROL 25

26 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step 4 (R-type): Write result to register [5-] CONTROL 26

27 I-Type: Store Instruction Tells operation to be performed Store Instruction OPCODE = 35 or 43 RS RT OFFSET Base Address Register (attached to Read Register input) SW $S, 32($S2) SW RT, #(RS) Source register whose value will be stored to memory (attached to Read Register 2 input) Constant offset (added to the base address in RS) Note: same as x86 MOV [ebx+32], eax 27

28 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step (store): Fetch instruction and advance PC [5-] CONTROL 28

29 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step 2 (store): Read register values and set control signals [5-] CONTROL 29

30 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step 3 (store): Compute the address [5-] CONTROL 3

31 4 << 2 [3-] [3-26] [25-2] [2-6] INST[5-] PC REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step 4 (store): Write the value to memory [5-] CONTROL 3

32 I-Type: Conditional Branch BEQ/BNE Instruction OPCODE =4or5 RS RT BRANCH TARGET S OFFSET Source Register Source register 2 (attached to Read (attached to Read Register input) Register 2 input) BEQ Source, Source2, Offset BEQ $S, $S2, = AL = ML (in binary) Word Offset, which we multiply by 4 (via <<2) to get Bit Offset, then add to PC+4 to get the address of the instruction to which we branch if RS = RT) PC-relative address 32

33 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend [5-] Step (beq): Fetch instruction and advance PC CONTROL 33

34 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend Step 2 (beq): Read register values and set control signals [5-] CONTROL 34

35 4 PC << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH MEM_,MEM_ ME EM_TO_REG [5-] Sign Extend [5-] Step 3 (beq): Compare registers, calculate branch target, and choose new PC CONTROL 35

36 J-Type: Unconditional Branch JMP/JAL Instruction OPCODE BRANCH TARGET =2or J Offset J = AL 2 25 = ML (in binary) Actual Address (in words) which we multiply by 4 (<<2) to get 28-Bit Address, then concatenate to upper 4 bits of PC+4 to get the 32-bit addresss of instruction to which we branch unconditionally 36

37 4 PC+4 [3-28] JMP [3-] PC I[25-] JMP [25-] << 2 << 2 [3-] [3-26] [25-2] [2-6] INST[5-] REG_DST REGISTER REGISTER 2 REGISTER REG_ REGISTERS 2 CON TROL _SRC _OP ZERO BRANCH JUMP MEM_,MEM_ MEM M_TO_REG [5-] Sign Extend Single-Cycle Datapath with Support for the Jump Instruction [5-] CONTROL 37