CS 61C: Great Ideas in Computer Architecture Control and Pipelining
|
|
- Gyles Foster
- 6 years ago
- Views:
Transcription
1 CS 6C: Great Ideas in Computer Architecture Control and Pipelining Instructors: Vladimir Stojanovic and Nicholas Weaver
2 Datapath Control Signals ExtOp: zero, sign ALUsrc: regb; immed ALUctr: ADD, SUB, OR MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder Adder Inst Address npc_sel & Equal Mux PC clk RegDst RegWr busw 32 Rd clk Imm6 Rt Rs 5 5 Rw Ra Rb RegFile 6 ExtOp Rt 5 Extender busa busb ALUSrc ALUctr Data In clk ALU 32 MemWr 32 WrEn Adr Data Memory MemtoReg 2
3 inst Summary of the Control Signals (/2) Register Transfer add R[rd] R[rs] + R[rt]; PC PC + 4 ALUsrc=RegB, ALUctr= ADD, RegDst=rd, RegWr, npc_sel= +4 sub R[rd] R[rs] R[rt]; PC PC + 4 ALUsrc=RegB, ALUctr= SUB, RegDst=rd, RegWr, npc_sel= +4 ori R[rt] R[rs] + zero_ext(imm6); PC PC + 4 ALUsrc=Im, Extop= Z, ALUctr= OR, RegDst=rt,RegWr, npc_sel= +4 lw R[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4 ALUsrc=Im, Extop= sn, ALUctr= ADD, MemtoReg, RegDst=rt, RegWr, npc_sel = +4 sw MEM[ R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4 ALUsrc=Im, Extop= sn, ALUctr = ADD, MemWr, npc_sel = +4 beq if (R[rs] == R[rt]) then PC PC + sign_ext(imm6)] else PC PC + 4 npc_sel = br, ALUctr = SUB 3
4 Summary of the Control Signals (2/2) See func We Don t Care :-) Appendix A op RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr<2:> add sub ori lw sw beq jump x Add x Subtract Or Add x x Add x x x Subtract x x x? x x R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump 4
5 Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw npcsel = beq Jump = jump ExtOp = lw + sw ALUctr[] = sub + beq (assume ALUctr is ADD, SUB, OR) ALUctr[] = or Where: rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op ~op, ori = ~op 5 ~op 4 op 3 op 2 ~op op lw = op 5 ~op 4 ~op 3 ~op 2 op op sw = op 5 ~op 4 op 3 ~op 2 op op beq = ~op 5 ~op 4 ~op 3 op 2 ~op ~op jump = ~op 5 ~op 4 ~op 3 ~op 2 op ~op How do we implement this in gates? add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func ~func sub = rtype func 5 ~func 4 ~func 3 ~func 2 func ~func 5
6 Controller Implementation opcode func AND logic add sub ori lw sw beq jump OR logic RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr[] ALUctr[] 6
7 P&H Figure 4.7 7
8 Summary: Single-cycle Processor Five steps to design a processor:. Analyze instruction set à datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements Processor Control Datapath Memory 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Input Output 8
9 Single Cycle Performance Assume time for actions are ps for register read or write; 2ps for other events Clock period is? Instr Instr fetch Register read ALU op Memory access Register write Total time lw 2ps ps 2ps 2ps ps 8ps sw 2ps ps 2ps 2ps 7ps R-format 2ps ps 2ps ps 6ps beq 2ps ps 2ps 5ps Clock rate (cycles/second = Hz) = /Period (seconds/cycle) 9
10 Single Cycle Performance Assume time for actions are ps for register read or write; 2ps for other events Clock period is? Instr Instr fetch Register read ALU op Memory access Register write Total time lw 2ps ps 2ps 2ps ps 8ps sw 2ps ps 2ps 2ps 7ps R-format 2ps ps 2ps ps 6ps beq 2ps ps 2ps 5ps What can we do to improve clock rate? Will this improve performance as well? Want increased clock rate to mean faster programs
11 Machine Interpretation Levels of Representation/Interpretation High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g., MIPS) Assembler Machine Language Program (MIPS) Hardware Architecture Description (e.g., block diagrams) Architecture Implementation temp = v[k]; v[k] = v[k+]; v[k+] = temp; lw $t, ($2) lw $t, 4($2) sw $t, ($2) sw $t, 4($2) Anything can be represented as a number, i.e., data or instructions Logic Circuit Description (Circuit Schematic Diagrams)
12 No More Magic! Application (ex: browser) Operating Compiler System Software Assembler (Mac OSX) Instruction Set Architecture Hardware Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors CS6A CS6B CS6C CS6C CS6C CS6C ç CS6C EE4 Phys 7B 2
13 Administrivia Project 2-2 due 23:59:59 (Tue) Guerrilla Sessions: MIPS CPU Wed 3/ Cory Sat 3/ Soda 3
14 Gotta Do Laundry Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and put away Washer takes 3 minutes A B C D Dryer takes 3 minutes Folder takes 3 minutes Stasher takes 3 minutes to put clothes into drawers 4
15 Sequential Laundry 6 PM AM T a s k O r d e r A B C D Time Sequential laundry takes 8 hours for 4 loads 5
16 Pipelined Laundry 2 2 AM 6 PM T a s k O r d e r A B C D Pipelined laundry takes 3.5 hours for 4 loads! Time 6
17 Pipelining Lessons (/2) T a s k O r d e r 6 PM A B C D Time Pipelining doesn t help latency of single task, it helps throughput of entire workload Multipletasks operating simultaneously using different resources Potential speedup = Number pipe stages Time to fill pipeline and time to drain it reduces speedup: 2.3x (8/3.5) v. 4x (8/2) in this example 7
18 Pipelining Lessons (2/2) T a s k O r d e r 6 PM A B C D Time Suppose new Washer takes 2 minutes, new Stasher takes 2 minutes. How much faster is pipeline? Pipeline rate limited by slowest pipeline stage Unbalanced lengths of pipe stages reduces speedup 8
19 Execution Steps in MIPS Datapath ) IFtch: Instruction Fetch, Increment PC 2) Dcd: Instruction Decode, Read Registers 3) Exec: Mem-ref: Calculate Address Arith-log: Perform Operation 4) Mem: Load: Read Data from Memory Store: Write Data to Memory 5) WB: Write Data Back to Register 9
20 Single Cycle Datapath PC instruction memory rd rs rt registers ALU Data memory +4 imm. Instruction Fetch 2. Decode/ 3. Execute 4. Memory Register Read 5. Write Back 2
21 Pipeline registers PC instruction memory rd rs rt registers ALU Data memory +4 imm. Instruction Fetch 2. Decode/ 3. Execute 4. Memory Register Read 5. Write Back Need registers between stages To hold information produced in previous cycle 2
22 More Detailed Pipeline 22
23 IF for Load, Store, 23
24 ID for Load, Store, 24
25 EX for Load 25
26 MEM for Load 26
27 WB for Load Oops! Wrong register number! 27
28 Corrected Datapath for Load 28
29 Pipelined Execution Representation Time IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Every instruction must take same number of steps, so some stages will idle e.g. MEM stage for any arithmetic instruction 29
30 Graphical Pipeline Diagrams PC MUX +4 instruction memory rd rs rt imm Register File ALU Data memory. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Write Back Use datapath figure below to represent pipeline: IF ID EX Mem WB ALU I$ Reg D$ Reg 3
31 Graphical Pipeline Representation RegFile: left half is write, right half is read Time (clock cycles) I n I$ Reg D$ Reg s Load t I$ Reg D$ Reg r Add O r d e r Store Sub Or ALU I$ ALU Reg I$ ALU Reg I$ D$ ALU Reg Reg D$ ALU Reg D$ Reg 3
32 Pipelining Performance (/3) Use T c ( time between completion of instructions ) to measure speedup Equality only achieved if stages are balanced (i.e. take the same amount of time) If not balanced, speedup is reduced Speedup due to increased throughput Latency for each instruction does not decrease 32
33 Pipelining Performance (2/3) Assume time for stages is Instr ps for register read or write 2ps for other stages Instr fetch Register read ALU op Memory access Register write Total time lw 2ps ps 2ps 2ps ps 8ps sw 2ps ps 2ps 2ps 7ps R-format 2ps ps 2ps ps 6ps beq 2ps ps 2ps 5ps What is pipelined clock rate? Compare pipelined datapath with single-cycle datapath 33
34 Pipelining Performance (3/3) Single-cycle T c = 8 ps f =.25GHz Pipelined T c = 2 ps f = 5GHz 34
35 Clicker/Peer Instruction Logic in some stages takes 2ps and in some ps. Clk-Q delay is 3ps and setup-time is 2ps. What is the maximum clock frequency at which a pipelined design can operate? A: GHz B: 5GHz C: 6.7GHz D: 4.35GHz E: 4GHz 35
Working on the Pipeline
Computer Science 6C Spring 27 Working on the Pipeline Datapath Control Signals Computer Science 6C Spring 27 MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder
More informationCS 110 Computer Architecture Single-Cycle CPU Datapath & Control
CS Computer Architecture Single-Cycle CPU Datapath & Control Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides
More informationCS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)
CS335B Computer Architecture Winter 25 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza www.csd.uwo.ca/courses/cs335b [Adapted from lectures on Computer Organization and Design,
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2
CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs6c/ Review:
More informationLecture #17: CPU Design II Control
Lecture #7: CPU Design II Control 25-7-9 Anatomy: 5 components of any Computer Personal Computer Computer Processor Control ( brain ) This week ( ) path ( brawn ) (where programs, data live when running)
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures The Internet is broken?! The Clean Slate team at Stanford wants to revamp the Internet, making it safer (from viruses), more reliable
More informationFull Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI
CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked
More informationCS 61C: Great Ideas in Computer Architecture Lecture 12: Single- Cycle CPU, Datapath & Control Part 2
CS 6C: Great Ideas in Computer Architecture Lecture 2: Single- Cycle CPU, Datapath & Control Part 2 Instructor: Sagar Karandikar sagark@eecs.berkeley.edu hbp://inst.eecs.berkeley.edu/~cs6c Midterm Results
More informationCSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content
3/6/8 CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Today s Content We have looked at how to design a Data Path. 4.4, 4.5 We will design
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control 27-3-2 Exhausted TA Ben Sussman www.icanhascheezburger.com Qutrits Bring Quantum Computers Closer:
More informationCOMP303 Computer Architecture Lecture 9. Single Cycle Control
COMP33 Computer Architecture Lecture 9 Single Cycle Control A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationCS 110 Computer Architecture. Pipelining. Guest Lecture: Shu Yin. School of Information Science and Technology SIST
CS 110 Computer Architecture Pipelining Guest Lecture: Shu Yin http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides based on UC Berkley's CS61C
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU
More informationCS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic
CS 61C: Great Ideas in Computer Architecture Datapath Instructors: John Wawrzynek & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/fa15 1 Components of a Computer Processor Control Enable? Read/Write
More informationMIPS-Lite Single-Cycle Control
MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Single cycle
More information361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control
36 control. EECS 36 Computer Architecture Lecture 9: Designing Single Cycle Control Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm6 3 3 26 2 6 op rs rt rd
More information361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationThe Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath
The Big Picture: Where are We Now? EEM 486: Computer Architecture Lecture 3 The Five Classic Components of a Computer Processor Input Control Memory Designing a Single Cycle path path Output Today s Topic:
More informationThe Processor: Datapath & Control
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the
More informationCpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 34 Single Cycle CPU Control I 24-4-16 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia 1.5 Quake?! NBC movie on May 3 rd. Truth stranger
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1 Guest Lecturer: Sagar Karandikar hfp://inst.eecs.berkeley.edu/~cs61c/ http://research.microsoft.com/apps/pubs/default.aspx?id=212001!
More informationEEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control
EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2 An Abstract View of the Implementation Ideal Address Net Address PC
More informationCPU Design Steps. EECC550 - Shaaban
CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select set of datapath components & establish clock methodology. 3. Assemble datapath meeting the
More informationCS3350B Computer Architecture Quiz 3 March 15, 2018
CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.
More informationECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath
ECE468 Computer Organization and Architecture Designing a Single Cycle Datapath ECE468 datapath1 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath
More informationComputer Architecture. Lecture 6.1: Fundamentals of
CS3350B Computer Architecture Winter 2015 Lecture 6.1: Fundamentals of Instructional Level Parallelism Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and
More informationCPU Organization (Design)
ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 Single Cycle CPU Datapath CPS today! 2005-10-31 There is one handout today at the front and back of the room! Lecturer PSOE, new dad
More informationSingle Cycle CPU Design. Mehran Rezaei
Single Cycle CPU Design Mehran Rezaei What does it mean? Instruction Fetch Instruction Memory clk pc 32 32 address add $t,$t,$t2 instruction Next Logic to generate the address of next instruction The Branch
More informationECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations
ECE7 Computer Architecture Single Cycle Control Review: 3a: Overview of the Fetch Unit The common operations Fetch the : mem[] Update the program counter: Sequential Code: < + Branch and Jump: < something
More informationCS359: Computer Architecture. The Processor (A) Yanyan Shen Department of Computer Science and Engineering
CS359: Computer Architecture The Processor (A) Yanyan Shen Department of Computer Science and Engineering Eecuting R-type Instructions 7 Instructions ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate:
More informationMajor CPU Design Steps
Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected
More informationLecture 6 Datapath and Controller
Lecture 6 Datapath and Controller Peng Liu liupeng@zju.edu.cn Windows Editor and Word Processing UltraEdit, EditPlus Gvim Linux or Mac IOS Emacs vi or vim Word Processing(Windows, Linux, and Mac IOS) LaTex
More informationInstructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #18. Warehouse Scale Computer
/29/3 CS 6C: Great Ideas in Computer Architecture Building Blocks for Datapaths Instructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs6c/fa3 /27/3 Fall 23 - - Lecture #8 So5ware Parallel Requests Assigned
More informationUniversity of California College of Engineering Computer Science Division -EECS. CS 152 Midterm I
Name: University of California College of Engineering Computer Science Division -EECS Fall 996 D.E. Culler CS 52 Midterm I Your Name: ID Number: Discussion Section: You may bring one double-sided pages
More informationOutline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath
Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates
More informationReview. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU
CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review
More informationinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 19 CPU Design: The Single-Cycle II & Control !
inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture 9 CPU Design: The Single-Cycle II & Control 2-7-22!!!Instructor Paul Pearce! Dell may have shipped infected motherboards! Dell is warning
More informationDesigning a Multicycle Processor
Designing a Multicycle Processor Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras Multicycle-
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 25 CPU Design: Designing a Single-cycle CPU Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia T-Mobile s Wi-Fi / Cell phone
More informationinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability!
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I CS61C L18 CPU Design: The Single-Cycle I (1)! 2010-07-21!!!Instructor Paul Pearce! Nasty new windows vulnerability!
More informationCPS104 Computer Organization and Programming Lecture 19: Pipelining. Robert Wagner
CPS104 Computer Organization and Programming Lecture 19: Pipelining Robert Wagner cps 104 Pipelining..1 RW Fall 2000 Lecture Overview A Pipelined Processor : Introduction to the concept of pipelined processor.
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs61c/ Review
More informationCSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade
CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4
More informationIf you didn t do as well as you d hoped
7/3/5 CS 6C: Great Ideas in Computer Architecture Midterm Results Lecture 2: Single- Cycle CPU, path & Control Part 2 ructor: Sagar Karandikar sagark@eecsberkeleyedu hfp://insteecsberkeleyedu/~cs6c You
More informationMidterm I March 3, 1999 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Midterm I March 3, 1999 CS152 Computer Architecture and Engineering Your Name: SID
More informationCS 152 Computer Architecture and Engineering. Lecture 10: Designing a Multicycle Processor
CS 152 Computer Architecture and Engineering Lecture 1: Designing a Multicycle Processor October 1, 1997 Dave Patterson (http.cs.berkeley.edu/~patterson) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/
More informationHow to design a controller to produce signals to control the datapath
ECE48 Computer Organization and Architecture Designing Single Cycle How to design a controller to produce signals to control the datapath ECE48. 2--7 Recap: The MIPS Formats All MIPS instructions are bits
More informationChapter 4. The Processor. Computer Architecture and IC Design Lab
Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS
More informationRecap: The MIPS Subset ADD and subtract EEL Computer Architecture shamt funct add rd, rs, rt Single-Cycle Control Logic sub rd, rs, rt
Recap: The MIPS Subset EEL-47 - Computer Architecture Single-Cycle Logic ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm 2 rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits
More informationCO Computer Architecture and Programming Languages CAPL. Lecture 18 & 19
CO2-3224 Computer Architecture and Programming Languages CAPL Lecture 8 & 9 Dr. Kinga Lipskoch Fall 27 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be
More informationCS 110 Computer Architecture Review Midterm II
CS 11 Computer Architecture Review Midterm II http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides based on UC Berkley's CS61C 1 Midterm II Date:
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More informationCS61C : Machine Structures
CS 61C L path (1) insteecsberkeleyedu/~cs61c/su6 CS61C : Machine Structures Lecture # path natomy: 5 components of any Computer Personal Computer -7-25 This week Computer Processor ( brain ) path ( brawn
More informationLecture 7 Pipelining. Peng Liu.
Lecture 7 Pipelining Peng Liu liupeng@zju.edu.cn 1 Review: The Single Cycle Processor 2 Review: Given Datapath,RTL -> Control Instruction Inst Memory Adr Op Fun Rt
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationCS 61C: Great Ideas in Computer Architecture Pipelining and Hazards
CS 61C: Great Ideas in Computer Architecture Pipelining and Hazards Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Pipelined Execution Representation Time
More informationEECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction
EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement
More informationCENG 3420 Lecture 06: Datapath
CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference
More informationCh 5: Designing a Single Cycle Datapath
Ch 5: esigning a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s Topic:
More informationPipeline: Introduction
Pipeline: Introduction These slides are derived from: CSCE430/830 Computer Architecture course by Prof. Hong Jiang and Dave Patterson UCB Some figures and tables have been derived from : Computer System
More informationCPSC614: Computer Architecture
CPSC614: Computer Architecture E.J. Kim Texas A&M University Computer Science & Engineering Department Assignment 1, Due Thursday Feb/9 Spring 2017 1. A certain benchmark contains 195,700 floating-point
More informationEECS 151/251A Fall 2017 Digital Design and Integrated Circuits. Instructor: John Wawrzynek and Nicholas Weaver. Lecture 13 EE141
EECS 151/251A Fall 2017 Digital Design and Integrated Circuits Instructor: John Wawrzynek and Nicholas Weaver Lecture 13 Project Introduction You will design and optimize a RISC-V processor Phase 1: Design
More informationCENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu
CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified
More informationCOMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined
More informationCS152 Computer Architecture and Engineering Lecture 10: Designing a Single Cycle Control. Recap: The MIPS Instruction Formats
CS52 Computer Architecture and Engineering Lecture : Designing a Single Cycle February 7, 995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson
More informationELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control
ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
More informationCS 61C Fall 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control)
CS 61C Fall 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control) 1) If this exam were a CPU, you d be halfway through the pipeline (Sp15 Final) We found that the instruction fetch and memory stages
More informationThe MIPS Processor Datapath
The MIPS Processor Datapath Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath
More informationEECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer
EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM
More informationPipeline design. Mehran Rezaei
Pipeline design Mehran Rezaei How Can We Improve the Performance? Exec Time = IC * CPI * CCT Optimization IC CPI CCT Source Level * Compiler * * ISA * * Organization * * Technology * With Pipelining We
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationCS 61C Summer 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control)
CS 61C Summer 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control) 1) If this exam were a CPU, you d be halfway through the pipeline (Sp15 Final) We found that the instruction fetch and memory stages
More informationMidterm I October 6, 1999 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 6, 1999 CS152 Computer Architecture and Engineering Your Name: SID
More informationLecture 3. Pipelining. Dr. Soner Onder CS 4431 Michigan Technological University 9/23/2009 1
Lecture 3 Pipelining Dr. Soner Onder CS 4431 Michigan Technological University 9/23/2009 1 A "Typical" RISC ISA 32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero, DP take pair)
More informationChapter 4 The Processor 1. Chapter 4A. The Processor
Chapter 4 The Processor 1 Chapter 4A The Processor Chapter 4 The Processor 2 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2. Clk
3/3/5 CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU path & Control Part 2 ructors: Krste Asanovic & Vladimir Stojanovic hip://inst.eecs.berkeley.edu/~cs6c/ Review:
More informationCOMP303 - Computer Architecture Lecture 10. Multi-Cycle Design & Exceptions
COP33 - Computer Architecture Lecture ulti-cycle Design & Exceptions Single Cycle Datapath We designed a processor that requires one cycle per instruction RegDst busw 32 Clk RegWr Rd ux imm6 Rt 5 5 Rs
More informationELCT 501: Digital System Design
ELCT 501: Digital System Lecture 8: Pipelining Dr. Mohamed Abd El Ghany, Pipelining: Its Natural! Laundry Example Ann, brian, cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationCS61c Final Review Fall Andy Carle 12/12/2004
CS61c Final Review Fall 24 Andy Carle 12/12/24 Topics Before Midterm C& Malloc Memory Management MIPS Number Representation Floating Point CAL Topics Since Midterm Digital Logic Verilog State Machines
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationGuerrilla Session 3: MIPS CPU
CS61C Summer 2015 Guerrilla Session 3: MIPS CPU Problem 1: swai (Sp04 Final): We want to implement a new I- type instruction swai (store word then auto- increment). The operation performs the regular sw
More informationadd rd, rs, rt Review: A Single Cycle Datapath We have everything Lecture Recap: Meaning of the Control Signals
CS6C L27 Single-Cycle CPU Control () inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control 27-3-2 Ehausted TA Ben Sussman www.icanhascheezburger.com Qutrits
More informationOutline Marquette University
COEN-4710 Computer Hardware Lecture 4 Processor Part 2: Pipelining (Ch.4) Cristinel Ababei Department of Electrical and Computer Engineering Credits: Slides adapted primarily from presentations from Mike
More informationLecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices
More informationCOMP2611: Computer Organization. The Pipelined Processor
COMP2611: Computer Organization The 1 2 Background 2 High-Performance Processors 3 Two techniques for designing high-performance processors by exploiting parallelism: Multiprocessing: parallelism among
More informationMidterm I March 12, 2003 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm I March 2, 2003 CS52 Computer Architecture and Engineering Your Name: SID Number:
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single Cycle MIPS CPU
CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single Cycle MIPS CPU ructors: Randy H Katz David A PaGerson hgp://insteecsberkeleyedu/~cs6c/sp Spring 2 - - Lecture #8 Parallel Requests
More informationPipelining. Maurizio Palesi
* Pipelining * Adapted from David A. Patterson s CS252 lecture slides, http://www.cs.berkeley/~pattrsn/252s98/index.html Copyright 1998 UCB 1 References John L. Hennessy and David A. Patterson, Computer
More informationModern Computer Architecture
Modern Computer Architecture Lecture2 Pipelining: Basic and Intermediate Concepts Hongbin Sun 国家集成电路人才培养基地 Xi an Jiaotong University Pipelining: Its Natural! Laundry Example Ann, Brian, Cathy, Dave each
More informationChapter 5 (a) Overview
Chapter 5 (a) Overview (a) The principles of pipelining (a) A pipelined design of SRC (b) Pipeline hazards (b) Instruction-level parallelism (ILP) Superscalar processors Very Long Instruction Word (VLIW)
More informationSystems Architecture
Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software
More informationPage 1. Pipelining: Its Natural! Chapter 3. Pipelining. Pipelined Laundry Start work ASAP. Sequential Laundry A B C D. 6 PM Midnight
Pipelining: Its Natural! Chapter 3 Pipelining Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes A B C D Dryer takes 40 minutes Folder
More informationComputer Systems Architecture Spring 2016
Computer Systems Architecture Spring 2016 Lecture 01: Introduction Shuai Wang Department of Computer Science and Technology Nanjing University [Adapted from Computer Architecture: A Quantitative Approach,
More informationLecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1
Lecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1 Introduction Chapter 4.1 Chapter 4.2 Review: MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions small number
More information