Speaker:Kuan-Te Wu. Advanced Reliable System Lab.

Transcription

1 Speaker:Kuan-Te Wu 1

2 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Using Complier Controls Verilog Operators RTL Modeling 2

3 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Using Complier Controls Verilog Operators RTL Modeling 3

4 Physical Compiler/ Magma Blast Fusion Spec. System Level MATLAB/ C/ C++/ System C/ ADS/ Covergen (MaxSim) Memory Generator RTL Level Verilog/ VHDL NC-Verilog/ ModelSim Debussy (Verdi)/ VCS Syntest Logic Synthesis Conformal/ Formality Design/ Power Compiler Design for Test DFT Compiler/ TetraMAX Gate Level NC-Verilog/ ModelSim Debussy (Verdi)/ VCS Layout Level Post-Layout Verification SOC Encounter GDS II DRC/ LVS (Calibre) PVS: Calibre xrc/ NanoSim (Time/ Power Mill) Tape Out

5 A high-level programming language with special constructs to model the function of hardware logic circuits Describe the connectivity of the circuit Describe the functionality of a circuit Describe a circuit at various levels of abstraction Behavior Function Structure Describe the timing of a circuit Express concurrency 5

6 Verilog is a hardware description language Verilog models digital electronic systems Verilog lets you model at various levels of abstraction Verilog les you develop tests to verify the functionality of the devices you model 6

7 Behavioral Describes a system by the flow of data between its functional blocks Schedules assignments at functional boundaries only when necessary Register Transfer Level (RTL) or Functional Describe a system by the flow of data and control signals within and between functional blocks Defines the model in terms of cycles, based on a defined clock Gate Level (Structural) Models components by connecting primitives or low-level components (gates) for greater accuracy, especially in timing 7

8 Describe the design without implying any specific internal architecture Use high level constructs case, if, repeat, wait, while) Usually use behavioral construct in testbench Synthesis tools accept only a limited subset of these module SMUX(out, a, b, sel); output out; input a,b,sel; wire out; assign out = (sel)? a : b ; module a b? sel SMUX out 8

9 Describe the design in sufficient detail that synthesis tools can construct the circuit module SMUX(out, a, b, sel); output out; input a,b,sel; reg out; or b or sel)begin if (sel) out=a; else out=b; module a b sel SMUX out 9

10 Synthesis tools produce a purely structural design description b SMUX sel Sel_n t2 t1 out a module SMUX(out, a, b, sel); output out; input a,b,sel; wire sel_n,t1,t2; not U0(sel_n,sel); and U1(t1,a,sel); and U2(t2,b,sel_n); or U3(out,t1,t2); module 10

11 Circuit Description module ALU(s,cout,ctr,a,b,cin); input a,b,cin; module Test bench module text_bench; reg a,b,cin; module Verilog Simulator Verilog Parser Simulator Engine User Interface Graphic Simulation Results Text Mode Simulation Results 11

12 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Using Complier Controls Verilog Operators RTL Modeling 12

13 Template // // Header // module module_name( port_names ); Port declaration //comment Data type declaration //comment Task & function declaration Module functionality or structure Timing Specification module // // This is sample code. // The function is ALU. // module ALU(a,b,sel,out); //Port declarations input [7:0] a,b; //Data in output[7:0]out; //Data out input [2:0]sel; //Control select //Data type declaration reg [7:0]out; wire //Module functionality or structure module 13

14 Make sure your code is Readable, Modifiable, and Reusable. Good coding style helps to achieve the best compile times and synthesis results. Testability Performance Simplification of static timing analysis Gate-level circuit behavior that matches that of the original RTL code 14

15 Simple and regular Use simple constructs and simple clocking schemes Consistent coding style, consistent naming and state machines Regular partitioning scheme Easy to understand by comments and meaningful names. No hard coded number 15

16 Naming Conventions Use lowercase letters for all signal names, and port names, versus uppercase letters for names of constants and user-defined types. Use meaningful names. For active low signals, the signal name with an underscore followed by a lowercase character (e.g., rst_ or rst_n) Recomm using bus[x:0] for multi-bit signals. 16

17 Include Headers in Source Files and Comments Regular 17

18 Indentation Port Maps and Generic Maps Always use explicit mapping for ports and generics, using named association rather than positional association 18

19 Use Functions or Tasks: Which Instead of repeating the same sections of code 19

20 Template module testbench; Data type declaration Instantiate modules Applying stimulus Monitor signals module Compare this with your design! // // This is testbench of sample code. // The function is ALU. // module test_alu; reg [7:0] A,B; reg[2:0]sel; wire[7:0] OUT; ALU U0(.a(A),.b(B),.sel(SEL),.out(OUT)); always #5 B=~B; Initial begin A=0;B=0;SEL=0; #10 A=0;SEL=1; #10 SEL=0;.. #10 SEL=1; #10 $finish; initial $monitor($time,"a=%b b=%b sel=%b out=%b",a,b,sel,out); initial begin $fsdbdumpfile("alu.fsdb"); $fsdbdumpvars; module 20

21 Simulation Related Tasks Terminate simulation $finish; Text-based output $monitor($time,"a=%b b=%b sel=%b out=%b",a,b,sel,out); $display("time=%d clk=%b out=%b",$time,clk,out); Graphic waveform dump initial begin $fsdbdumpfile("file_name.fsdb"); $fsdbdumpvars; 21

22 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Verilog Operators Using Complier Controls RTL Modeling 22

23 Single-line comments begin with "//" and with a new-line character Multiple-line comments start with "/*" and "*/" // // This is sample code. // The function is ALU. // module ALU(a,b,sel,out); //Port declarations input [7:0] a,b; //Data in output[7:0]out; //Data out input [2:0]sel; //Control select //Data type declaration reg [7:0]out; wire //Module functionality or structure always@(...)begin module 23

24 Integers can be sized or unsized. Sized integers are represented as <size> <base><value> Value Description 8 b bit binary 64 hff01 64-bit hexadecimal 4 d12 Decimal 20 bz01x Z-exted to 20 bits 3 b bit number, truncated to 3 b001 9 o17 9-bit octal 24

25 Verilog is case sensitive. For example, sel and SEL are different identifiers The "$" sign denotes Verilog system tasks and functions Ex: $finish, $fsdbdumpvars, etc The pound sign(#) character denotes the delay specification 25

26 The `define compiler directive provides a simple text-substitution facility `define <macro_name> <macro_text> `define STATE_A 4 b0000; `define STATE_B 4 b0001; if(pr_state == `STATE_A)begin else if(pr_state == `STATE_B)begin module 26

27 Parameter parameter <macro_name> = <macro_text> parameter STATE_A = 4 b0000; parameter STATE_B = 4 b0001; if(pr_state == STATE_A)begin else if(pr_state == STATE_B)begin module 27

28 Use the `include complier directive to insert the contents of an entire files `include "alu.v" `include "../../lib/mem.v" You can use `include to: Include global or commonly used definitions, such as text macros Include tasks without encapsulating repeated code within module boundaries 28

29 `timescale compiler directive declares the time unit and precision `timescale <time_unit>/<time_precision> `timescale 1ns/100ps 29

30 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Using Complier Controls Verilog Operators RTL Modeling 30

31 Verilog Logic Values The underlying data representation allows for any bit to have one of four values 1, 0, x (unknown), z (high impedance) x one of: 1, 0, z, or in the state of change z the high impedance output of a tri-state gate What basis do these have in reality? 0,1 no question z A tri-state gate drives either a zero or one on its output and if it s not doing that, its output is high impedance (z) Tri-state gates are real devices and z is a real electrical affect x not a real value There is no real gate that drives an x on to a wire x is used as a debugging aid x means the simulator can t determine the answer and so maybe you should worry! All values in a simulation start as x 31

32 4-value logic system in Verilog 32

33 Input A Logic with multi-level logic values Logic with these four values make sense Nand anything with a 0, and you get a 1. This includes having an x or z on the other input. That s the nature of the nand gate Nand two x s and you get an x makes sense! Note: z treated as an x on input Their rows and columns are the same If you forget to connect an input it will be seen as an z At the start of simulation, everything is an x Input B A B NAND 0 1 x z x x x 1 x x x z 1 x x x A 4-valued truth table for a Nand gate with two inputs 33

34 There are three major data type classes in Verilog: Nets: (default data type:wire, ) Represent physical connection between devices Registers: (data type: reg, integer, ) Represent abstract storage elements Parameters: (default data type:parameter) Are run-time constants 34

35 Nets are continuous driven by the devices that drive them These devices include gates and modules Verilog automatically propagates a new value onto a net when the drivers on the net change value This means that whatever value is on the or gate will be automatically driven onto net out b SMUX sel Sel_n t2 t1 out a 35

36 A register holds its value until a new value is assigned to it Registers are used extensively in behavioral modeling and in applying stimuli Use behavioral constructs to apply values to registers 36

37 Net declaration: <net_type> [range] <net_name>[, net_name]* Register declaration: <reg_type> [range] <reg_name>[, reg_name]* EX: wire [4:0] a,b; reg [7:0]bus_in; reg sel_a,sel_b; 37

38 Module Boundary of DUT Input port Output port net/register net net/register net net Inout port module top; wire y; reg a,b; DUT U1(.Y(y),.A(a),B(b)); initial begin a=0;b=0; #5 a=1; module net module DUT(Y,A,B); input A,B; output Y; wire Y,A,B; and(y,a,b); module 38

39 You make a procedural assignment to a signal that you either declared as a net or you forgot to declare This is an illegal assignment You connect an output from an instance to a signal declared as a register You declare a signal as module input and as a register These are incompatible declarations 39

40 Use parameters to declare run-time constants You can use a parameter anywhere that you can use a literal Parameter is local, known only to the module in which they are defined EX: module mod1(a,b,c); parameter WIDTH = 5; wire [WIDTH-1:0] w1; module module mod1_test; parameter cycle= 10; always #(cyc) clk = ~clk; module 40

41 An array if the datatype reg is often called a memory reg [15:0] MEM [0:1023] //1K x 16-bit memory array reg [7:0] MEM [0:1023] //1K x 8-bit memory array parameter WORD_SIZE=16; parameter MEM_SIZE=1024; reg[word_size-1:0] MEM[MEM_SIZE-1:0]; 41

42 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Verilog Operators Using Complier Controls RTL Modeling 42

43 Simulators Verilog-XL, NC Verilog, Altera Quartus, ModelSim and etc. Synthesizers Design vision, Ambit, and etc Debugger and verification tools Debussy, nwave, nlint, and etc nlint can check the correctness of your code s syntax 43

44 //alu.v /* This is sample code. The function is ALU. */ module ALU( a, b, sel, out ); input [7:0] a,b; //Data in output[7:0]out; //Data out input [2:0]sel; //Control select reg [7:0]out; wire module //t_alu.v /* This is testbench of sample code. The function is ALU. */ module test_alu; reg [7:0] A,B; reg[2:0]sel; wire[7:0] OUT; ALU U0(.a(A),.b(B),.sel(SEL),.out(OUT)); always #5 B=~B; initial begin A=0;B=0;SEL=0; #10 A=0;SEL=1; #10 SEL=0;.. #10 SEL=1; #10 $finish; initial begin $fsdbdumpfile("alu.fsdb"); $fsdbdumpvars; module 44

45 Method 1: verilog alu.v t_alu.v ncverilog alu.v t_alu.v +access+r Method 2: Using additional file alu.f alu.v t_alu.v verilog -f alu.f ncverilog -f alu.f +access+r Method 3: Using additional description `include "module_file" 45

46 //alu.v /* This is sample code. The function is ALU. */ module ALU( a, b, sel, out ); input [7:0] a,b; //Data in output[7:0]out; //Data out input [2:0]sel; //Control select reg [7:0]out; wire module `include "alu.v" //t_alu.v /* This is testbench of sample code. The function is ALU. */ module test_alu; reg [7:0] A,B; reg[2:0]sel; wire[7:0] OUT; ALU U0(.a(A),.b(B),.sel(SEL),.out(OUT)); always #5 B=~B; initial begin A=0;B=0;SEL=0; #10 A=0;SEL=1; #10 SEL=0;.. #10 SEL=1; #10 $finish; initial begin $fsdbdumpfile("alu.fsdb"); $fsdbdumpvars; module 46

47 Using nwave or Debussy nwave& debussy& Open the fsdb file Select "Signal" -> "Get Signal" From the design hierarchy tree, select the signal names and then "Apply" or "OK" to show the waveform Press "L" to reload after a new simulation 47

48 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Using Complier Controls Verilog Operators RTL Modeling 48

49 Bitwise Operators OP Usage Description ~ ~m Invert each bit of m & m&n AND each bit of m with each bit of n m n OR each bit of m with each bit of n ^ m^n Exclusive OR each bit of m with n ~^ or ^~ m~^n or m^~n Exclusive NOR each bit of m with n Unary Reduction Operators OP Usage Description & &m AND all bits in m together (1-bit result) ~& ~&m NAND all bits in m together (1-bit result) m OR all bits in m together (1-bit result) ~ ~ m NOR all bits in m together (1-bit result) ^ ^m Exclusive OR all bits in m (1-bit result) ~^ or ^~ ~^m or ^~m Exclusive NOR all bits in m (1-bit result) 49

50 Arithmetic Operators OP Usage Description + m + n Add n to m - m - n Subtract n from m - -m Negate m (2's complement) * m * n Multiply m by n / m / n Divide m by n % m % n Modulus of m / n Logical Operators OP Usage Description!!m Is m not true? (1-bit True/False result) && m && n Are both m and n true? (1-bit True/False result) m n Are either m or n true? (1-bit True/False result) 50

51 Equality Operators (compares logic values of 0 and 1) OP Usage Description == m == n Is m equal to n? (1-bit True/False result)!= m!= n Is m not equal to n? (1-bit True/False result) Relational Operators OP Usage Description < m < n Is m less than n? (1-bit True/False result) > m > n Is m greater than n? (1-bit True/False result) <= m <= n Is m less than or equal to n? (True/False result) >= m >= n Is m greater than or equal to n? (True/False result) 51

52 Logical Shift Operators << m<< n Shift m left n-times >> m >> n Shift m right n-times Misc Operators OP Usage Description? : sel?m:n If sel is true, select m: else select n {} {m,n} Concatenate m to n, creating larger vector {{}} {n{m}} Replicate m n-times 52

53 Overview of Verilog HDL Sample Design Lexical Conventions in Verilog Data Types and Logic System Using Complier Controls Verilog Operators RTL Modeling 53

54 Combination circuits: ALU, decoder, MUX, etc Combinational circuit Sequential circuits: Memory ex:latch, Flip-flop, Register Counter Finite state machine Combinational circuit Combinational circuit clk 54

55 The RTL modeling style is a subset of the behavioral modeling style Behavioral modeling enables you to describe the system at a high level of abstraction Behavioral modeling in Verilog is described by specifying a set of concurrently active procedural blocks Data DFF Q Qb At every positive edge of clk If rst is not low Set Q to the value of Data Set Qb to inverse of Data rst clk Whenever rst goes low Set Q to 0 Set Q to 1 55

56 initial begin begin Initial procedural blocks execute only once begin initial begin Always procedural blocks execute in a loop Procedural blocks have the following components: Procedural assignment statement High level constructs(loops, conditional statements) Timing controls 56

57 Assignments made inside procedural blocks are called procedural assignments module adder(out,a,b,cin); input a,b,cin; output [1:0]out; wire a,b,cin; reg half_sum; reg [1:0]out; or b or cin)begin half_sum=a^b^cin; //OK half_carry=a&b a&!b&cin!a&b&cin ;//error out={half_carry,half_sum}; module Edge sensitive timing control At here, all signals on left-hand side must be a register data type(reg). half_carry is not declared, and defaults to a 1-bit wire The right-hand side of a procedural assignment can be any valid expression. The data types used here are not restricted If you forget to declare a signal, it defaults to type wire. If you make a procedural assignment to a wire, it is an error 57

58 Using timing control for combinational or sequential models at the RTL and behavioral levels. You can qualify signal sensitivity with the negedge or posedge keywords, and you can wait for changes on multiple signals by using the or keyword module adder_1(out,a,b,clk); input [2:0]a,b; Input clk; output [3:0]out; positive edge reg [3:0]sum; reg [3:0]out; always@(a or b)begin //When any change occurs on a or b sum=a+b; always@(negedge clk)begin //at every negative edge of clk out=sum; module negative edge 58

59 Combinational logic: If event-expression doesn t contain posedge or negedge Flip-flops: If event-expression contains posedge or negedge Latches: A variable assigned within an block that is not fully specified 59

60 D-type latch: module latch_d(enable, D, Q); input Enable, D; output Q; reg Q; or D) if (Enable) Q = D; module D-type flip-flop: module D_FF_SR(clock, reset, D, Q); input clock, reset, D; output Q; reg Q; clock) begin if (reset == 1 b1) Q <= 1 b0; // reset else Q <= D; module 60

61 //synchronous reset clock) if (rst) begin. //asynchronous reset clock or negedge reset) if (!rst) begin. 61

62 Synchronous Mixed Clock Edges D Q CBL D Q D Q CBL D Q clk clk Combination Feedback Gated Clocks CBL D Q D Q clk 62

63 A blocking procedural assignment(=) is executed before the next statement in the sequential blocks is scheduled A nonblocking procedural assignment(<=) does not block the procedural flow, so as soon as the assignment is read by the simulator and scheduled, the next assignment can be read When all assignments in a procedural block are nonblocking, the assignments occur in two steps: The simulator evaluates all the RHS expressions, stores the resulting values, and schedules the assignments to take place at the time specified by timing control After each delay expired, the simulator executes the assignment by assigning the stored values to the LHS expression 63

64 Nonblocking EX: clk)begin x<= a; y<= x; z<= y; a x y z Blocking EX: always@(posedge clk)begin x= a; y= x; z= y; a z 64

65 If and if-else statements: In nested if sequences, else is associated with the closest previous if To ensure proper readability and proper association, use begin block statements.. or shift_en or dir)begin if(shift_en==1)begin if(dir)begin out=a>>1; else begin out=a<<1; else begin out=a;.. 65

66 module mux4to1(out,a,b,c,d,sel); input [2:0]a,b,c,d; input [1:0]sel; output [2:0]out; reg [2:0]out; or b or c or d or sel)begin if(sel==2 b00)begin out = a; else if(sel==2 b01)begin out =b; else if(sel==2 b10)begin out =c; else begin out =d; module 66

67 Case statements: The case statement is a special multi-way conditional statement that test whether the expression matches one of a number of other expressions branch accordingly.. always@(a or b or c or d or sel)begin case(sel) 2 b00:begin out=a; 2 b01:begin out=b; 2 b10:begin out=c; 2 b11:begin out=d; default:begin out=1 bz; case.. 67

68 If-else statement Priority-encoded logic For speed critical path Case statement Balanced logic For complex decoding 68

69 You can model combinational logic with continuous assignment, instead of using gates or interconnect nets Use continuous assignment outside of a procedural block. They are considered the lowest level construct in behavioral modeling Use a continuous assignment to drive onto a net In a continuous assignment, the LHS is updated at any change in the RHS expression 69

70 Ex: wire out1, out1_b,out2; assign out1=a&b; (OK) assign out1_b=~(a&b); (OK) assign out2=a^b; (error) module MUX4to1(out,a,b,c,d,sel); input [2:0] a,b,c,d; input [1:0]sel; output[2:0]out; assign out =(sel==2 b00)? a : (sel==2 b01)? b : (sel==2 b10)? c : d; module You can also use case and if-else statements. 70

71 Verilog Basis parameter declarations wire, wand, wor declarations reg declarations input, output, inout continuous assignment module instructions gate instructions always blocks task statement function definitions for, while loop Synthesizable Verilog primitives cells and, or, not, nand, nor, xor, xnor bufif0, bufif1, notif0, notif1 71

72 Operators Concatenation ( { }, {{}} ) Unary reduction (!, ~, &,, ^ ) 2 s complement arithmetic ( +, -, *) Logic shift ( >>, << ) Relational ( >, <, >=, <= ) Equality ( ==,!= ) Binary bit-wise ( &,, ^, ~^ ) Logical ( &&, ) Conditional (?: ) highest precedence lowest 72

73 Either non-synthesizable or incorrect after synthesis initial block is forbidden (non-synthesizable) Multiple assignments (multiple driving sources) (non-synthesizable) Mixed blocking and non-blocking assignment or src2 or inc) begin des = src1 + src2; inc <= src1-4; always@(src1 or src2) result = src1 + src2; always@(inc1 or inc2 or offset) result = inc1 + inc2 + offset; 73

74 delay initial repeat wait fork join event deassign force release primitive User defined primitive time triand, trior, tri1, tri0,trireg noms, pmos, cmos, rnmos, rpmos, rcmos pullup, pulldown rtran, tramif0, tranif1, rtranif0, rtranif1 case identity and not identity operators division and modules operation ===,!== forever Ex: wire out=(!en)?in: hz (replace trior ) in en out 74

75 No initial in the RTL code FFs are preferred Avoid unnecessary latches Avoid combinational feedback For sequential blocks, use no-blocking statements For combinational blocks, use blocking statements Coding state machines Two procedure blocks: one for the sequential and one for the combinational Keep FSM logic and non-fsm logic in separate modules Assign a default state 75

76 Combinational Blocks (d) begin case (d) 2'b00: z=1'b1; 2'b01: z=1'b0; default : z=1'b0; case (a or x_temp) begin if (a) begin x= x_temp+1 b1; else begin x= x_temp; Sequential Blocks (posedge clk ) begin if (a) begin z<=1 b1; else begin z<=1 b0; 76

77 Avoid Combinational Feedback (a or x)begin if (a) begin x= x+1 b1; else begin x= x; (posedge clk) begin x<=x_temp; (a or x)begin if (a) begin x_temp= x+1 b1; else begin x_temp= x; 77

78 Blocking Assignment (posedge clk) begin b=a; c=b; Non-Blocking Assignment (posedge clk) begin b<=a; c<=b; Just like a=c; Just like shift register a D Q b c a b c D Q D Q clk clk 78

79 Avoid Latches (d) begin case (d) 2'b00: z=1'b1; 2'b01: z=1'b0; default : z=1'b0; case (d)begin if (a) begin... else begin... (d) begin x=1 b0; z=1 b0; case (d) 2'b00: begin z=1'b1; x=1 b1; 2'b01: begin z=1'b0; default : begin z=1'b0; case (posedge clk )begin if (a) begin z<=1b1; else begin z<=1 b0; 79

80 Sensitivity List (d) begin case (d) 2'b00: z=1'b1; 2'b01: z=1'b0; default : z=1'b0; case (a or b or c or d)begin if (a) begin... else begin if (b)begin z=c; else begin z=d; 80

81 Syntax error for Verilog Simulation Mixed edge-triggered and level-sensitive control in an always block or posedge clk) begin 81

82 Key: The multiplexer is a faster circuit. If the priority-encoding structure is not required, we recomm using the case statement Using a conditional assignment to infer a Mux assign out = sel? a : b ; 82

83 Omit the Wait for XX ns Statement Do not use #XX; Omit the...after XX ns or Delay Statement Do not use assign #XX Q=0; Omit Initial Values Do not use initial sum = 1 b0; 83

84 If statement vs. Case statement If statement Priority-encoded logic For speed critical path Case statement Balanced logic For complex decoding 84

85 Case statements ( sel or a or b or c or d)begin case (sel) 2'b00:out=a; 2'b01:out=b; 2'b10:out=c; 2'b11:out=d; case a b c d out if else statements ( sel or a or b or c or d) begin if (sel==2'b00) out=a; else if (sel==2'b01) out=b; else if (sel==2'b10) out=c; else out=d; sel d c b a out sel 85

86 Explicit FSM design parameter S0 = 2 b00; parameter S1 = 2 b01; always@(state or in) begin case (state) S0: if (in) next_state = S1; else next_state = S0; S1: always@(posedge clk) if(~reset) state <= S0; else state <= next_state; 86

87 Resource Sharing Simplified Register Using ( ) to describe complex circuits. Timescale 87

88 Operations can be shared if they lie in the same always block (sel or a or b or c ) begin if (sel) z=a+b; else z=a+c; b b a z c z c sel sel a 88

89 cnt+1 cnt+2 Take away control signals from the register if there are many control signals to control the register (posedge clk or posedge rst)begin if (rst) begin cnt = 3 d0; else if(a)begin cnt = cnt+3 d1; clk rst a b cnt out else if(b)begin cnt = cnt+3 d2; else begin cnt = cnt; adder

90 cnt_in (posedge clk or posedge rst)begin if (rst) begin cnt <= 3 d0; else begin cnt <= cnt_in; always@(a or b or cnt)begin if(a)begin cnt_in = cnt+3 d1; else begin cnt_in = cnt+3 d2; else begin cnt_in = cnt; Smaller area!!! clk rst cnt adder a b out

91 out=a+b+c+d+e; a b c out=((a+(b+c))+(d+e)); c b a d e d e out out 91

92 FSM Moore machine Mealy machine 92

93 Moore machine Present state Next state Input 0 Input 1 Output Y S0 S2 S1 0 S1 S0 S2 0 S2 S1 S0 1 93

94 Moore machine module moore(rst, clk, x, y); input rst, clk, x; output y; reg y; reg[4:0] ps,ns; parameter s0=5 d0; parameter s1=5 d1; parameter s2=5 d2; case(ps) s0: begin if (x == 0) ns = s2; else ns = s1; y = 0; s1: begin if (x == 0) ns = s0; else ns = s2; y = 0; case always@(posedge clk or posedge rst)begin if (reset)begin ns <= s0; else begin ps <= ns; module 94

95 Mealy machine Present state Next state output X=0 X=1 X=0 X=1 S0 S2 S1 0 0 S1 S0 S2 0 0 S2 S1 S

96 Mealy machine module mealy(reset, clk, x, y); input reset, clk, x; output y; reg y; reg [4:0] ps, ns; `define s0 5 d0; `define s1 5 d1; `define s2 5 d2; always@(ps)begin case(ps) `s0: begin if (x == 0) ns = `s2; else ns = `s1; if (x == 0) y = 0; else y = 0; case always@(posedge clk or posedge reset)begin if(reset)begin ps<=0; else begin ps <= ns; module 96

97 Using nlint to check your syntax: nlint gui Identifiers & syntax Data type(reg or wire?) Incompletely sensitive list Combinational loops Non-blocking and blocking Latchs? Etc. al. 97

98 Your RTL design Functional verification by some high-level language Also, the code coverage of your test benches should be verified (i.e. VN) Coding style checking (i.e. n-lint) Good coding style will reduce most hazards while synthesis Better optimization process results in better circuit performance Easy debugging after synthesis Constraints The area and timing of your circuit are mainly determined by your circuit architecture and coding style There is always a trade-off between the circuit timing and area In fact, a super tight timing constraint may be worked while synthesis, but failed in the Place & Route (P&R) procedure Area Better Cycle Time 98

99 1. Verilog Training Manual, CIC 2. Logic Synthesis with Design Complier, CIC 3. "Modeling Synthesis, and Rapid Prototyping with the Verilog HDL", Ciletti 4. "Reuse Methodology Manual", Michael Keating and Pierre Bricaud 5. Introduction to VLSI course lecture, NCUEE, Jin-Fu Li 6. Design and Verification Methodology for SoC course lecture, NCUEE, Chien-Nan Liu 7. VLSI Design course lecture, NCUEE, Pei-Yun Tsai 99