Building Bigger Systems: Hardware Threads

Transcription

1 ! uilding igger Systems: Hardware Threads Lecture L dvanced igital esign ECE epartment Many elements on Thomas, 2014, used with permission with credit to G. Larson

2 Today We build on our knowledge of FSMs Want to make more complex systems - Stuff that "Computes" How should they be organized? How should we think about them? This material often not taught in igital esign Class 2

3 Sequential Systems Every synchronous sequential design can be classified as a finite-state machine - all that really means is that it has a finite number of flip-flop/ registers in the design Intel Itanium2 has more than 2 27 state bits and more than 2 (2^27) distinguishable states - No. There is not a gigantic state-transition diagram somewhere - Yes. There are control FSMs (the way you understand FSMs now) may be many tens of states in the largest ones more complicated control exists as many cooperating FSMs - The majority of the logic is in the datapath very stylistic usage of state and logic a very different way of design 3

4 Motivation: serial adder example dd two N-bit numbers in serial - unsigned numbers appear (i, i) - 1 bit per cycle (LS first) starting after reset - assert done, Cout and sum when the computation is finished Reset...i...i N done Cout sum Clk How many different states does this FSM need? 4

5 reset If you don t know any better init 1,1 "1+1" 0,0 1,0 0,1 "1+0" "0+0" "0+1" 0,0 0,1 1,1 "00+ 10" "01+ 01" 1,0 0,0 0,1 "01+ 00" "00+ 01" "00+ 00" 0,0 " " 1,1 "01+1 1" 1,0 "01+ 10" "00+1 1" 1, " 1,0 0, " " " This could work, but obviously not recommended

6 better idea: datapath + control Much of the functionality can be built with pieces you already know how to use (Full dder, FFs)..a i..b i ci co Full dder s sum Still need something to control the system Use a FSM for control - at reset, carry flip flop gets cleared (perhaps also the sum bits) - you need to count from 0 to N-1 after reset - when FSM is N-1, you need to signal done - only N states and log2 N state bits!! 6

7 These are called datapaths atapaths - ata is stored in the registers - Flows along the lines - Is transformed or selected by the combinational components e.g., adder, mux - Loaded into another register What can this datapath do? - increment: sum = sum + 1 ld_l=0, cl_l=1, sel=1 - add_input: sum = sum + input ld_l=0, cl_l=1, sel=0 - synchronous clear of sum, cl_l=0 Inputs sel, ld_l, cl_l are called control points ld_l clock cl_l sel Input dder Sum Q Mux 6 6'b1 6

8 Computations In combinational logic, (think oolean algebra here) - sum = a b cin, and - cout = a b + a cin + b cin - all the variables are 1-bit values In register-transfer level systems, we say - a = b + c (addition!) don t think oolean algebra here, think C or SystemVerilog - oh, and by the way: they re all 37-bit numbers, the add occurs in FSM state 17 the result is stored in a register containing a bunch of FFs collectively called a The difference: the level of abstraction - We re describing computations, the order and FSM state they occur in, what components registers, LUs they use - It looks a little like programming 8

9 What can this circuit do? Three supported RTs - sum = sum + input - sum = 0 - sum = sum What is sum in this case? The state of a computation dder Input With proper sequencing we can do a computation: sum=0; for (i=0, i<2; i++) sum += Input; ld_l clock cl_l Q 16 What provides the proper sequencing? - Finite State Machine 9

10 FSM sequencing reset_l ld_l = 1 cl_l = 0 16 Input ld_l = 0 cl_l = 1 control datapath dder 16 ld_l C ld_l = 0 cl_l = 1 clock cl_l Q 16 sum=0; for (i=0, i<2; i++) sum += Input; It clears Q to zero and then adds input in each successive state 10

11 Tracing the state changes C ld_l=1,cl_l=0 ld_l=0,cl_l=1 ld_l=0,cl_l=1 16 Input sum=0 sum += input sum += input reset_l dder C Q 16 ld_l = 1 cl_l = 0 Clk Clk Q ld_l clock cl_l Q 16 ld_l = 0 cl_l = 1 Clk Q C reset_l C ld_l = 0 cl_l = 1 11

12 Generalize on what we just did FSM- finite state machine with a datapath - The finite state machine is what we ve been studying - datapath is combinational logic and registers that can do computation (sometimes spelled data-path, or data path) - What senses and controls the computation? The FSM FSM- is often called a Hardware Thread inputs outputs FSM atapath clock reset 12

13 What s this Look Like in SysVerilog? module top #(parameter W = 16) (input logic [W-1:0] input, input logic clock, rst_l); no connection 16 Input logic cl_l, ld_l; logic [W-1:0] sum, addout; adder #(W) a1 (input, sum, 1'b0, addout, ); regload #(W) r1 (addout, ld_l, cl_l, clock, rst_l, sum); ld_l clock dder 16 fsm endmodule: top c1 (clock, rst_l, ld_l, cl_l); cl_l Q 16 The module def s: module regload (d, ld_l, cl_l, clk, reset_l, q); module adder (,, Cin, Sum, Cout); 13

14 How about the FSM Module? module fsm (input logic clk, rst_l, output logic ld_l, cl_l); enum logic [2:0] {=3'b100, =3'b010, C=3'b001} ns, cs; always_comb unique case (cs) : begin //load zero ns = ; cl_l = 0; ld_l = 1; end : begin //add input ns = C; cl_l = 1; ld_l = 0; end C: begin //add input ns = ; cl_l = 1; ld_l = 0; end endcase clk, negedge rst_l) if (~rst_l) cs <= ; else cs <= ns; reset_l ld_l = 1 cl_l = 0 ld_l = 0 cl_l = 1 C ld_l = 0 cl_l = 1 endmodule: fsm 14

15 Termination Our solution doesn't exactly match our specification - i.e. the code snippet sum=0; for (i=0, i<2; i++) sum += Input; When complete, our FSM loops to do it again If we care, then go to a "finish" state and stay there reset_l ld_l = 1 cl_l = 0 Computes eternally reset_l ld_l = 1 cl_l = 0 Computes once Holds answer eternally ld_l = 0 cl_l = 1 ld_l = 0 cl_l = 1 C ld_l = 0 cl_l = 1 C ld_l = 0 cl_l = 1 Stop ld_l = 1 cl_l = 1 1

16 Thorough Example Problem statement - When the d_in_ready signal is asserted, read the 30-bit input word (d_in), count the number of bits in it that are set to one, make this -bit number available at the d_out output, assert the d_out_ready signal, and wait for the next d_in_ready signal d_in_ready What components do we need? - To store the input word? 30-bit shift register d_in clock reset Ones Counter FSM atapath d_out_ready d_out - To count the number of ones? -bit up counter - To count the number of bits examined? -bit up-counter - To determine when we are done? Comparator (count to 30) 16

17 Example: atapath Components TW, this is but one approach to this datapath problem load_l shift_l 30 Shift Register lowbit We ll load this register when the d_in_ready signal is asserted. Then we ll shift it right 30 times, each time looking at the low-order output bit (bit 0) clr_l clr_l inc_l Shift Count Register inc_l Ones Count Register 'd30 This register will count the number of 1s we see on the low order bit of the shift register This register will count from zero to 30. The comparator will tell us when we re done comparator eq done 17

18 Start Piecing the System Together atapath inputs and outputs d_in 30 clr_l load_l inc_l Ones Count Register shift_l Shift Register d_in_ ready lowbit d_out clr_l clock reset FSM inc_l done Shift Count Register comparator 'd30 d_out_ ready 18

19 Start Piecing the System Together atapath control points - Inputs to the datapath used by FSM to control the datapath d_in 30 clr_l load_l inc_l Ones Count Register shift_l Shift Register d_in_ ready lowbit d_out clr_l clock reset FSM inc_l done Shift Count Register comparator 'd30 d_out_ ready 19

20 Start Piecing the System Together atapath status points - Values in datapath used by the FSM on state transitions d_in 30 clr_l load_l inc_l Ones Count Register shift_l Shift Register d_in_ ready lowbit d_out clr_l clock reset FSM inc_l done Shift Count Register comparator 'd30 d_out_ ready 20

21 Start Piecing the System Together Hook up the rest of the inputs and outputs d_in 30 clr_l load_l inc_l Ones Count Register shift_l Shift Register d_in_ ready lowbit d_out clr_l clock reset FSM inc_l done Shift Count Register comparator 'd30 d_out_ ready 21

22 The FSM state by state Reset ~ d_in_ready d_in_ready / Cclr_L, Sload_L, Oclr_L Cclr_L Cinc_L done Shift Count Register SC comparator 30 'd30 Sload_L Sshift_L Shift Register lowbit When we get to this state, what will be the values in the registers? Oclr_L Oinc_L Ones Count Register Note: we re only showing the output signals asserted in each state 22

23 FSM arc by arc Reset ~ d_in_ready d_in_ready / Cclr_L, Sload_L, Oclr_L Cclr_L Cinc_L done Shift Count Register SC comparator 30 'd30 lowit & (~ done) / Oinc_L, Cinc_L, Sshift_L Sload_L Sshift_L Shift Register lowbit If the low bit is 1, and the shift count is not 30, increment the counters and shift Oclr_L Oinc_L Ones Count Register 23

24 FSM arc by arc Reset ~ d_in_ready d_in_ready / Cclr_L, Sload_L, Oclr_L Cclr_L Cinc_L done Shift Count Register SC comparator 30 'd30 lowit & (~ done) / Oinc_L, Cinc_L, Sshift_L Sload_L Sshift_L Shift Register lowbit ~lowit & (~ done) / Cinc_L, Sshift_L Oclr_L Oinc_L Ones Count Register If the low bit is 0 and the shift count is not 30, inc the shift counter and shift. on t enable One s Count 24

25 nd a final arc Reset done / _out_ready ~ d_in_ready d_in_ready / Cclr_L, Sload_L, Oclr_L Cclr_L Cinc_L done Shift Count Register SC comparator 30 'd30 Sload_L Sshift_L Shift Register lowit & (~ done) / Oinc_L, Cinc_L, Sshift_L lowbit ~lowit & (~ done) / Cinc_L, Sshift_L When the shift count is 30, signal _out_ready Oclr_L Oinc_L Ones Count Register 2

26 Specify the Main Module module OnesCount #(parameter w = 30) (input logic input logic output logic d_in_ready, clock, reset, d_out_ready, d_in, input logic [w-1:0] output logic [$clog2(w)-1:0] d_out); // ceiling of log2 of w $clog2(i) is a system function (indicated by the $ ) that calculates the ceiling of log2(i) //instantiate FSM and atapath components here endmodule: OnesCount Ones Counter d_in_ready d_in d_out_ready d_out FSM atapath clock reset 26

27 FSM SystemVerilog: State module fsm #( ) (clock, reset, ); enum logic { = 1'b0, = 1'b1} cur_state, n_state; always_comb begin case (cur_state) : begin //State n_state = d_in_ready? : ; Cclr_L = d_in_ready? 0 : 1; Sload_L = d_in_ready? 0 : 1; Oclr_L = d_in_ready? 0 : 1; Sshift_L = 1; Cinc_L = 1; Oinc_L = 1; dor = 0; // _out_ready end : begin //State end endcase end clock, posedge reset) if (reset) cur_state <= ; else cur_state <= n_state; Reset done / _out_ready ~lowit & (~ done) / Cinc_L, Sshift_L ~ d_in_ready d_in_ready / Cclr_L, Sload_L, Oclr_L lowit & (~ done) / Oinc_L, Cinc_L, Sshift_L endmodule: fsm 27

28 FSM SystemVerilog: State module fsm #( ) (clock, reset, ); enum logic { = 1'b0, = 1'b1} cur_state, n_state; always_comb begin case (cur_state) : begin //State : begin //State n_state = (done)? : ; dor = (done)? 1 : 0; Cclr_L = 1; Sload_L = 1; Oclr_L = 1; Cinc_L = (done)? 1 : 0; Sshift_L = (done)? 1 : 0; Oinc_L = (done)? 1:~lowit; end endcase end endmodule: fsm Reset done / _out_ready ~lowit & (~ done) / Cinc_L, Sshift_L ~ d_in_ready d_in_ready / Cclr_L, Sload_L, Oclr_L lowit & (~ done) / Oinc_L, Cinc_L, Sshift_L 28

29 More module OnesCount #(parameter w = 30) (input logic d_in_ready, clock, reset, input logic [w-1:0] d_in, output logic dor, output logic [$clog2(w)-1:0] d_out); logic lowit, done, Cclr_L, Cinc_L; logic Sload_L, Sshift_L, Oclr_L; logic Oinc_L, dor; logic [$clog2(w)-1:0] SC; fsm #(w) control (.*); ShiftReg_PISO_Right #(w) sr (lowit, d_in, clk, Sload, Sshift); counter #($clog2(w)) sc (clock, Cclr_L, Cinc_L, SC); compare #($clog2(w)) cmp (, done,, SC, 'd30); counter #($clog2(w)) oct (clock, Oclr_L, Oinc_L, d_out); endmodule: OnesCount module fsm #(parameter w = 30) (input logic clock, reset, done, input logic d_in_ready, lowit, input logic [$clog2(w):0] SC, output logic Cclr_L, Cinc_L, Sload_L, Sshift_L, Oclr_L, Oinc_L, dor); enum logic { = 1'b0, = 1'b1} cur_state, n_state; always_comb begin case (cur_state) : begin //State endcase end clock, posedge reset) begin if (reset) cur_state <= ; else cur_state <= n_state; end endmodule: fsm

30 Trace a Transition CLK dinready Reset ~ d_in_ready Cclr_L Sload Oclr_L SC? 0 done / _out_ready d_in_ready / Cclr_L, Sload_L, Oclr_L OC? 0 ShiftReg? input lowit Oinc_L? lowit & (~ done) / Oinc_L, Cinc_L, Sshift_L ~lowit & (~ done) / Cinc_L, Sshift_L 30

31 n lternate pproach Reset d_in_ready / Cclr_L, Sload_L, Oclr_L ~ d_in_ready Lose the Shift Count Reg/Comp - Let s just have 30 states where we do the shifting and then just return to the state - I got tired, and didn t draw all 30 of them! 30 Sload_L Sshift_L Shift Register ~lowit / Sshift_L lowit / Oinc_L, Sshift_L lowbit C Oclr_L Oinc_L Ones Count Register ~lowit / Sshift_L lowit / Oinc_L, Sshift_L etc OC 31

32 How ifferent Will This e? Pick a state encoding - How about = 00000, = 00001, C = 00010, = 00011, E = 00100, - How would our design be different? 32

33 Two pproaches These two state transition diagrams suggest two ways of envisioning a controller - Exclude all of the states where you are just counting from the FSM Treat the counter as something else to control and monitor for when it s done - Include all of the states, i.e. ones where you re just counting, in the FSM This was our second approach Comparison - Excluding the counter states Smaller, simpler FSM to design functional partitioning Give the synthesis tool a smaller thing to design - Including all of the states igger, more complex FSM to design Let a synthesis tool wrestle with a state encoding 33

34 Cooperating FSMs Turns out, they re about the same One view: Cooperating FSMs - Control FSM + shift-count FSM two separate FSMs each with simple-to-think-about control sequences compose them to form the more elaborate control sequences 34

35 More lternates on t use a shift register - Use a register called IN to hold the input data - Put a 32-to-1 mux on the output of IN - Use the old shift count (now called Count) to select one of the bits to feed to the FSM Cclr_L Cinc_L it Count Register load_l Oclr_L Oinc_L 30 IN Register Ones Count Register OC 30 done 'd30 Count comparator sel 32-to-1 MUX selected bit to FSM lowit 3

36 Here s nother Who needs a state machine? - Just build up a big combinational network of adders - Load the IN register, and several gate delays later you ll have the answer Comparison - The all combinational version of these circuits are generally fewer cycles but require more gates (no reuse) - The all combinational may not be faster if clock frequency goes way down load_l IN Register big combinational circuit of adders to add up all of the bits

37 nd nother How might you write the loop in software? Sload_L Sshift_L 30 Shift Register for (Ocount = 0, ShiftReg = in; ShiftReg!= 0; ShiftReg >> 1) 30'd0 30 Q lowbit if (ShiftReg & 1) Ocount++; - Like before, no loop counter, but end when shift-reg has no 1 s left Observations - Many software alternates apply Some S/W, some H/W - Hardware faster, a two state machine - ut you couldn t have used the all combinational string of adders in software - Evaluation functions for hardware and software differ Oclr_L Oinc_L comparator eq ShiftReg!= 0 Ones Count Register OC 37

38 nother: 1-13 atalab Way V = d_in; for (onescount = 0; V; onescount++) { // clear the least significant bit set V &= V - 1; } 2-to-1 MUX 30 d_in load_l This one loops only once for each set bit value and that value -1 differ only from the least significant set bit down value That value -1 30'd0 comparator eq done Register 30 30'd1 Subtracter 30 N gates Only different here Sometimes known as "rian Kernighan's way" 38

39 n exercise for the student unsigned int v; // count the number of bits set in v unsigned int c; // c accumulates the total bits set in v // option 1, for at most 14-bit values in v: c = (v * 0x ULL & 0x ULL) % 0xf; // option 2, for at most 24-bit values in v: c = ((v & 0xfff) * 0x ULL & 0x ULL) % 0x1f; c += (((v & 0xfff000) >> 12) * 0x ULL & 0x ULL) % 0x1f; // option 3, for at most 32-bit values in v: c = ((v & 0xfff) * 0x ULL & 0x ULL) % 0x1f; c += (((v & 0xfff000) >> 12) * 0x ULL & 0x ULL) % 0x1f; c += ((v >> 24) * 0x ULL & 0x ULL) % 0x1f; Thanks to: graphics.stanford.edu/~seander/bithacks.html 39

40 Reviewing the Parts inputs outputs FSM atapath clock reset next state and output logic inputs outputs outputs inputs LUs, MUXes, comparators, etc. State FFs Registers clock reset clock reset 40

41 Notes on Hardware Thread esign esign the computational machinery (datapath) separate from the control (FSM) machinery - Keep control points and status points straight - Make sure the FSM inputs status points and outputs control points atapath should be structured as RTL - Registers hold values - t clock edges, values are transferred from a register, through combinational circuitry, into a (usually different) register - Might even list transformations during design as: Register Register Register C + Register Register C Think of transformations using standard components whenever possible When datapath definition is complete, then develop FSM to drive it

42 Summary RTL level systems - FSM- finite state machine and datapath - Hardware Thread - escribed in terms of the functional units datapath and controller(s) - Generally multibit ops we re describing computations We ve now seen Mealy and Moore implementations - Plenty of alternate implementations - Software background can help suggest alternates - ut software and hardware implementations are very different What s good for one isn t necessarily good for the other 42