ECEN 468 Advanced Digital System Design

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1 ECEN 468 Advanced Digital System Design Lecture 23: Verilog Finite State Machines ECEN468 Lecture 23

Moore Machine Next state Combinational logic Register

2 Finite State Machines input Mealy Machine Next state and output Combinational logic Register output clock input Moore Machine Next state Combinational logic Register Output Combinational logic output clock ECEN468 Lecture 23 2

Explicit Finite State Machines 1 module FSM_style1 ( ); input ; output ; parameter size = ; reg [size-1:0] state; wire [size-1:0] next_state; assign outputs = ; // function of state and

3 Explicit Finite State Machines 1 module FSM_style1 ( ); input ; output ; parameter size = ; reg [size-1:0] state; wire [size-1:0] next_state; assign outputs = ; // function of state and inputs assign next_state = ; // function of state and inputs ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; module ECEN468 Lecture 23 3

Explicit Finite State Machines 2 module FSM_style2 ( ); input ; output ; parameter size = ; reg [size-1:0] state, next_state; assign outputs = ; // function of state and inputs always @ ( state or

4 Explicit Finite State Machines 2 module FSM_style2 ( ); input ; output ; parameter size = ; reg [size-1:0] state, next_state; assign outputs = ; // function of state and inputs ( state or inputs ) begin // decode for next_state with case or if statement ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; module ECEN468 Lecture 23 4

Explicit Finite State Machines 3 module FSM_style3 ( ); input ; output ; parameter size = ; reg [size-1:0] state, next_state; always @ ( state or inputs ) begin // decode for next_state with case or

5 Explicit Finite State Machines 3 module FSM_style3 ( ); input ; output ; parameter size = ; reg [size-1:0] state, next_state; ( state or inputs ) begin // decode for next_state with case or if statement ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else begin state <= next_state; outputs <= some_value ( inputs, next_state ); module ECEN468 Lecture 23 5

6 Summary of Explicit FSM v States are defined explicitly v FSM_style1 o Minimum behavioral description v FSM_style2 o Use behavioral to define next state, easier to use v FSM_style3 o Output synchronized with clock ECEN468 Lecture 23 6

7 FSM Example: Speed Machine a = 1, b = 0 low b = 1 stopped b = 1 a: accelerator b: brake a = 1, b = 0 b = 1 accelerator brake clock speed medium b = 1 high a = 1, b = 0 a = 1, b = 0 ECEN468 Lecture 23 7

Verilog Code for Speed Machine // Explicit FSM style module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] state, next_state;

accelerator or brake ) if ( brake == 1`b1 ) case ( state ) stopped: next_state <= stopped; s_low: next_state <= stopped; s_medium: next_state <= s_low; s_high: next_state <= s_medium; default:

8 Verilog Code for Speed Machine // Explicit FSM style module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] state, next_state; parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; assign speed = state; ( posedge clock ) state <= next_state; ( state or accelerator or brake ) if ( brake == 1`b1 ) case ( state ) stopped: next_state <= stopped; s_low: next_state <= stopped; s_medium: next_state <= s_low; s_high: next_state <= s_medium; default: next_state <= stopped; case else if ( accelerator == 1`b1 ) case ( state ) stopped: next_state <= s_low; s_low: next_state <= s_medium; s_medium: next_state <= s_high; s_high: next_state <= s_high; default: next_state <= stopped; case else next_state <= state; module ECEN468 Lecture 23 8

Implicit Finite State Machine module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed;

<= `stopped; `low: speed <= `stopped; `medium: speed <= `low; `high: speed <= `medium; default: speed <= `stopped; case else if ( accelerator == 1`b1 ) case (

9 Implicit Finite State Machine module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 ( posedge clock ) if ( brake == 1`b1 ) case ( speed ) `stopped: speed <= `stopped; `low: speed <= `stopped; `medium: speed <= `low; `high: speed <= `medium; default: speed <= `stopped; case else if ( accelerator == 1`b1 ) case ( speed ) `stopped: speed <= `low; `low: speed <= `medium; `medium: speed <= `high; `high: speed <= `high; default: speed <= `stopped; case module ECEN468 Lecture 23 9

Another Implicit FSM Example module speed_machine3 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01

10 Another Implicit FSM Example module speed_machine3 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 ( posedge clock ) case ( speed ) `stopped: if ( brake == 1`b1 ) speed <= `stopped; else if ( accelerator == 1`b1 ) speed <= `low; `low: if ( brake == 1`b1 ) speed <= `stopped; else if ( accelerator == 1`b1 ) speed <= `medium; `medium: if ( brake == 1`b1 ) speed <= `low; else if ( accelerator == 1`b1 ) speed <= `high; `high: if ( brake == 1`b1 ) speed <= `medium; default: speed <= `stopped; case module ECEN468 Lecture 23 10

11 Tasks and Functions v Sub-programs that encapsulate and organize a description o Tasks create a hierarchical organization of the procedural statements o Functions substitute for an expression ECEN468 Lecture 23 11

12 Tasks v Declared within a module v Referenced in a behavior o In module where the task is declared o From any module through hierarchical de-referencing v All arguments to the task are passed by value, not pointer v Parameters can be passed to a task, variables and parameters within the parent module of a task are visible to the task v A task may not be used within an expression v Statements in a task may contain delay and event control v A task can call itself ECEN468 Lecture 23 12

Example of Task module bit_counter (data, count); input [7:0] data; output [3:0] count; reg [3:0] count; always @(data) t(data, count); task t; input

13 Example of Task module bit_counter (data, count); input [7:0] data; output [3:0] count; reg [3:0] count; t(data, count); task t; input [7:0] a; output [3:0] c; reg [3:0] c; reg [7:0] tmp; begin c = 0; tmp = a; while (tmp) begin c = c + tmp[0]; tmp = tmp >> 1; task module ECEN468 Lecture 23 13

14 Functions v Implement only combinational behavior v Compute and return a value for given parameters v Have no timing/event control v May call other functions, not itself v Can be referenced anywhere an expression can exist v May not declare any output or inout port v Must have at least one input port ECEN468 Lecture 23 14

15 Example of Function module word_aligner (w_in, w_out); input [7:0] w_in; output [7:0] w_out; assign w_out = align (w_in); function [7:0] align; input [7:0] word; begin align = word; if (align!= 0) while (align[7] == 0) align = align << 1; function module ECEN468 Lecture 23 15

16 Handshaking Server Client data_out 8 data_in server_ready client_ready server_ready client_ready ECEN468 Lecture 23 16

17 Algorithm State Machine (ASM) Chart s_idle / SR = 0 # s_wait / SR = 1 c_idle / CR = 0 # c_wait / CR = 1 CR 0 SR 0 1 # 1 # s_serve / SR = 1 c_client / CR = 1 # # s_done / SR = 0 c_done / CR = 0 1 CR 0 # 1 SR 0 # ECEN468 Lecture 23 17

18 Verilog Code for Handshaking module server ( d_out, s_ready, c_ready ); output [3:0] d_out; output s_ready; input c_ready; reg s_ready; reg [3:0] d_out; task pause; reg [3:0] delay; begin delay = $random; if ( delay == 0 ) delay = 1; #delay; task always forever begin s_ready = 0; pause; s_ready = 1; wait ( c_ready ) pause; d_out = $random; pause; s_ready = 0; wait (!c_ready ) pause; module module client ( d_in, s_ready, c_ready ); input [3:0] d_in; input s_ready; output c_ready; reg c_ready; reg [3:0] data_reg; task pause; reg [3:0] delay; begin delay = $random; if ( delay == 0 ) delay = 1; #delay; task always begin c_ready = 0; pause; c_ready = 1; forever begin wait ( s_ready ) pause; data_reg = d_in; pause; c_ready = 0; wait (!s_ready ) pause; c_ready = 1; module ECEN468 Lecture 23 18

19 Polling Circuit Each client cannot be served for 2 consecutive cycles Server client1 client2 client3 clock reset Polling circuit 3 2 service request service code Highest priority ECEN468 Lecture 23 19

20 State Transition Graph for Polling Circuit 100 Service request Client Client2 000 None 000 Client Service code 01- ECEN468 Lecture 23 20

Verilog Code for Polling Circuit module polling ( s_request, s_code, clk, rst ); `define client1 2`b01 `define client2 2`b10 `define client3 2`b11 `define none 2`b00 input [3:1] s_request; input clk,

= present_client; always @ ( present_client or s_request ) begin poll_them ( present_client, s_request, next_client ); task poll_them; input [1:0] present_client; input [3:1] s_request; output [1:0]

21 Verilog Code for Polling Circuit module polling ( s_request, s_code, clk, rst ); `define client1 2`b01 `define client2 2`b10 `define client3 2`b11 `define none 2`b00 input [3:1] s_request; input clk, rst; output [1:0] s_code; reg [1:0] next_client, present_client; ( posedge clk or posedge rst ) begin if ( rst ) present_client = `none; else present_client = next_client; assign s_code[1:0] = present_client; ( present_client or s_request ) begin poll_them ( present_client, s_request, next_client ); task poll_them; input [1:0] present_client; input [3:1] s_request; output [1:0] next_client; reg [1:0] conter; integer N; begin: poll conter = `none; next_client = `none; for ( N = 3; N >= 1; N = N 1 ) begin: decision if ( s_request[n] ) begin if ( present_client == N ) conter = present_client; else begin next_client = N; disable poll; if (( next_client == `none ) && ( conter )) next_client = conter; task module ECEN468 Lecture 23 21

Test Bench for Polling Circuit moduel test_polling; reg [3:1] s_request; reg clk, rst; wire [1:0] s_code; wire sreq3 = M1.s_request[3]; wire sreq2 = M1.s_request[2]; wire sreq1 = M1.

present_client; wire [3:1] s_req = s_request; wire [1:0] s_cd = s_code; polling M1 ( s_request, s_code, clk, rst ); initial begin clk = 0; forever #10 clk = ~clk; initial #400 finish; initial begin

22 Test Bench for Polling Circuit moduel test_polling; reg [3:1] s_request; reg clk, rst; wire [1:0] s_code; wire sreq3 = M1.s_request[3]; wire sreq2 = M1.s_request[2]; wire sreq1 = M1.s_request[1]; wire [1:0] NC = M1.next_client; wire [1:0] PC = M1.present_client; wire [3:1] s_req = s_request; wire [1:0] s_cd = s_code; polling M1 ( s_request, s_code, clk, rst ); initial begin clk = 0; forever #10 clk = ~clk; initial #400 finish; initial begin rst = 1`bx; #25 rst = 1; #75 rst = 0; initial begin #20 s_request = 3`b100; #20 s_request = 3`b010; #20 s_request = 3`b001; #20 s_request = 3`b100; #40 s_request = 3`b010; #40 s_request = 3`b001; initial begin #180 s_request = 3`b111; #60 s_request = 3`b101; #60 s_request = 3`b011; #60 s_request = 3`b111; #20 rst = 1; module ECEN468 Lecture 23 22

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date: Design of Datapath Controllers and Sequential Logic Lecturer: Date: 2009.03.18 ACCESS IC LAB Sequential Circuit Model & Timing Parameters ACCESS IC LAB Combinational Logic Review Combinational logic circuits