Reset, Interrupts, Exceptions, and Break ECE 3534

Transcription

1 Reset, Interrupts, Exceptions, and Break ECE

2 Reset, Interrupts, Exceptions, Break These topics are closely related Both software and hardware aspects of a processor are involved On the MicroBlaze, the facilities to handle them are quite similar All of these refer to mechanisms for altering the normal execution of a program Usual purpose: get the processor s attention for something that can t wait Reading: relevant parts of Chapter 1 in MBlaze 2

3 For the MicroBlaze, these things are prioritized: Reset ( highest priority) Hardware Exception Non-maskable Break Breaks Interrupts User Vectors (Exceptions) (Yes, the Xilinx terminology is a little confusing at first) 3

4 Interrupts and Exceptions These concepts are closely related, and the terminology is sometimes blurred (An interrupt is often considered to be a type of exception!) Deviation in normal sequence of actions For our purposes, An interrupt is asynchronous, traditionally generated by some external hardware device An exception is synchronous, resulting directly from the most recent instruction (example: divide-by-zero) 4

5 Typical sequence of actions (1/2) A triggering event occurs CPU finishes executing the current instruction CPU may save the state of the processor (PC, MSR, other registers) CPU may update status registers CPU branches to service routine (the MBlaze does this through its vector table ) 5

6 Vector Table in MicroBlaze 6

7 Typical sequence of actions (2/2) The CPU executes instructions in the appropriate service routine The service routine terminates with the appropriate instruction: rtid rted rtbd (return from interrupt) (return from exception) (return from break) By executing this instruction, the CPU may update status registers the CPU changes the PC No return from a reset! 7

8 Notice... A service routine is often called a handler A service routine should be quick and efficient To a reasonable extent, a service routine should not disrupt normal program execution Servicing an interrupt/exception/etc. is ideally totally transparent to the process that is executing when the event occurs If the service routine alters any registers, then typically it should preserve and restore them For larger systems, a service routine is usually considered part of the operating system 8

9 Reset Most microprocessors have an input pin that causes a reset to occur If asserted for 16 clock cycles or longer: PC 0 MSR 0 EAR 0 ESR 0 9

10 Interrupts Hardware support for getting CPU s attention Traditionally, an interrupt occurs in response to a request from an external hardware device The device sends its request to a physical input pin of the processor This pin is often called IRQ ( interrupt request ) The external device simply drives this signal to the logic ON state when it needs to be serviced On many systems, internal devices (e.g., timers) can also cause interrupts 10

11 Interrupts The interrupt service routine/handler ( ISR ) behaves much like a subroutine that is initiated by hardware In general, nested interrupts are possible; a new interrupt can occur while an interrupt handler is already executing Asynchronous, and typically unrelated to currently executing process 11

12 Interrupts Execution process: R14 PC PC 0x MSR[IE] 0 Special return instruction: rtid ra, IMM PC (ra) + sext(imm) allow following instruction to complete execution MSR[IE] 1 12

13 Interrupts The MicroBlaze will ignore an interrupt request, at least temporarily,... if MSR[IE] is 0 if MSR[BIP] is 1 (Break In Progress) 13

14 Nonmaskable interrupt Most interrupt requests can be serviced, denied or deferred Nonmaskable interrupts (NMI) are those that cannot be denied or deferred Examples Low-voltage interrupt detector response would be to perform orderly shutdown High temperature detector XMD seizing control of your processor 14

15 Prioritized Interrupt More than one level of interrupt possible Prioritize High level serviced sooner Example disk service routine to capture and transfer the data from the disk Medium level serviced in acceptable time Example keyboard where data may be held for 200ms Low level serviced as processing allows Example continue adding data to printer output buffer 15

16 Vectored Interrupts (1) Identify the requesting device Simple processors typically only have a single IRQ* input pin Interrupt Service Routine may need to poll the devices capable of asserting interrupt to determine who generated the request 16

17 Vectored Interrupts (2) IACK output pin on many common processors (x86, PowerPC, etc.) When asserted, requesting device places identification code (number) on bus Processor (in supervisory mode) branches to correct routine to service peripheral Many desktop processors support both vectored and non-vectored interrupts 17

18 Exceptions Synchronous: immediate result of most recent instruction often represents a hardware error condition Features are common to a subroutine call In practice an exception is effectively a call to the operating system Bridge three components of microprocessor Hardware Application software Operating system 18

19 Example hardware error exception Trying to read from a memory address not populated Example software exceptions Should never happen: Illegal op code Deliberate: Termed a TRAP can be used to create new instructions Ex: floating point 19

20 MicroBlaze Hardware Exceptions Unaligned Data Access Illegal Opcode Instruction Bus Error Data Bus Error Divide by Zero Floating Point Errors (underflow, overflow, divide by zero, invalid operation, denormalized operand) 20

21 Exception Causes (1/2) Unaligned Data Access Word with A30:A31!= 0 or Half Word with A31!= 0 Illegal Opcode Exception Opcode (bits 0-5 of the instruction) don t map to MicroBlaze s capabilities 21

22 Exception Causes (2/2) Instruction Bus Exception Something asserted the instruction bus OPB_errAck signal Data Bus Exception Something asserted the data bus OPB_errAck signal Divide by Zero FPU Exception 22

23 Exceptions Execution process: r17 PC PC 0x MSR[EE] 0 MSR[EIP] 1 ESR[DS] exception in delay slot ESR[EC] exception specific value ESR[ESS] exception specific value EAR exception specific value FSR exception specific value 23

24 Exceptions Special return instruction: rted ra, IMM PC (ra) + sext(imm) allow following instruction to complete execution MSR[EE] 1 MSR[EIP] 0 ESR 0 24

25 Exception Status Register (ESR) 25

26 Exception Specific Status (ESS) 26

27 Breaks Execution process (for hardware breaks): R16 PC PC 0x MSR[BIP] 1 Special return instruction: rtbd ra, IMM PC (ra) + sext(imm) allow following instruction to complete execution MSR[BIP] 0 Also, interrupts are disabled while a break is in progress, although MSR[IE] is not affected 27

28 Hardware Breaks A hardware break occurs when an external device asserts 1 of the 2 external break signals A normal hardware break (the Ext_BRK input port) is only handled when there is no break in progress (i.e MSR[BIP] is set to 0). The Break In Progress flag disables interrupts. A non-maskable break (the Ext_NM_BRK input port) will always be handled immediately. The BIP bit in the MSR is automatically cleared when executing the RTBD instruction. 28

29 Software Breaks The BRK or BRKI instruction is inserted by software at the point where a breakpoint is desired. Like a BRILD instruction, but BIP set, and returned by RTBD. 29

30 Software Breaks 30

31 User Exceptions These are exceptions that are actually called by the user: BRALID R15,0x8 A useful mechanism in operating systems. Not too meaningful to MicroBlaze since there is no concept of privilege separation. Refer to Wiki definition of Trap 31

32 SUMMARY Reset Hardware Exception Non-maskable Break Breaks Interrupts User Vectors (Exceptions) 32