MB96300 SERIES. 16-bit MICROCONTROLLER. List of functional limitations CI E-V21-MB96300_List_of_functional_limitations.

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1 CI E-V21-MB96300_List_of_functional_limitations.pdf 16-bit MICROCONTROLLER MB96300 SERIES List of functional limitations European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany File: DesignDifferences16FX.doc

2 European MCU Design Centre CI E-V21 Revision History Version Date Remark Initial version Revised 16FXFL Added 16FXFL0022, 16FXFL Added 16FXFL0024, 16FXFL0025 Improved part number information in list of affected devices of all individual functional limitation description and list of functional limitations Added MB96V300BRB Added 16FXFL FXFL0031. Updated 16FXFL0024 to rev Changed wording in 16FXFL Added 16FXFL0032, 16FXFL0033, 16FXFL Added 16FXFL0035, 16FXFL0036, 16FXFL Added 16FXFL0038, 16FXFL0039, 16FXFL0040. Added MB96385B and moved MB96385A to list of outdated devices Added 16FXFL0041, 16FXFL0042, 16FXFL0043, 16FXFL0044, 16FXFL0045, 16FXFL0046 Removed column Issue in Table 2 and Table Added MB96F31x, MB96F353, MB96F355 Page 2 of 185

3 European MCU Design Centre CI E-V21 Table of contents Overview FXFL0001: Power-on debug feature FXFL0002: Peripheral access during debug mode FXFL0003: CANbus 3 output enable register FXFL0004: Guarded access break after conditional branch FXFL0005: Data value break on byte access FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources FXFL0007: Bit positions in Real Time Clock register WTCKSR FXFL0008: Synchronous start of Programmable Pulse Generators FXFL0009: Embedded debug support data value break FXFL0010: Embedded debug support data write protection FXFL0011: EDSU USART Transmit Interrupt FXFL0012: DMA stop when CLKB > CLKP1/ FXFL0013: LCD prescaler FXFL0014: CLKP2 divider setting FXFL0015: Wake-up by RTC from timer mode FXFL0016: Interrupt while MOVS/MOVSW is executing FXFL0017: Flash read buffer after programming FXFL0018: NMI relocation lock FXFL0019: Phantom wake-up from timer or sleep mode FXFL0020: Read value of PDR/EPSR FXFL0021: Initial state of external interrupt flag FXFL0022: Permitted settings for the Flash configuration registers FXFL0023: Usage of Flash read buffer FXFL0024: Side effect of disabled DMA controller channels FXFL0025: Increased current consumption FXFL0026: Feature emulation FXFL0027: Trace function limitation FXFL0028: Stuck on SW instruction break FXFL0029: Limitation in using Operand break points as trace triggers FXFL0030: Limitation in using Pass Count of Operand break points of DSU FXFL0031: Wrong instruction execution detection of DSU FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time FXFL0033: FLASH Reset Page 3 of 185

4 European MCU Design Centre CI E-V21 16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/ FXFL0036: EDSU2 register not available on all devices (INT9 source selection) FXFL0037: Initial value of some I/O timer registers not correct FXFL0038: Watchdog detection during debugging is not correct FXFL0039: Low voltage detector threshold levels differ from datasheet specification FXFL0040: Limitation in using P13_5 and P13_7 as input FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt152 16FXFL0042: Failure of String Instructions and WBTC/WBTS Instructions FXFL0043: Limitations for IRQ clearing of LIN-USART and RTC FXFL0044: Limitation when using LCD segment FXFL0045: USB: STALL response release specification limitation of endpoint FXFL0046: USB: Specification of limitation on isochronous transfer Page 4 of 185

5 European MCU Design Centre CI E-V21 Overview For some devices a shortcut name was used as in the table below: Page 5 of 185

6 European MCU Design Centre CI E-V21 Table 1: Relation of device shortcut to product name. Device shortcut Product name MB9638X MB96384RSA, MB96384RWA, MB96384YSA, MB96384YWA, MB96385RSA, MB96385RWA, MB96385YSA, MB96385YWA MB9638XB MB96384RSB, MB96384RWB, MB96384YSB, MB96384YWB, MB96385RSB, MB96385RWB, MB96385YSB, MB96385YWB MB96F32X MB96F326ASA, MB96F326AWA, MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWA MB96F32XB MB96F326ASB, MB96F326AWB, MB96F326RSB, MB96F326RWB, MB96F326YSB, MB96F326YWB MB96F33x MB96F336USA, MB96F336UWA, MB96F338RSA, MB96F338RWA, MB96F338YSA, MB96F338YWA, MB96F338USA, MB96F338UWA MB96F348H/T MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA MB96F348H/TB MB96F348CSB, MB96F348CWB, MB96F348HSB, MB96F348HWB, MB96F348TSB, MB96F348TWB MB96F348H/TC MB96F348CSC, MB96F348CWC, MB96F348HSC, MB96F348HWC, MB96F348TSC, MB96F348TWC MB96F34XY/R MB96F346ASA, MB96F346AWA, MB96F346RSA, MB96F346RWA, MB96F346YSA, MB96F346YWA, MB96F347ASA, MB96F347AWA, MB96F347RSA, MB96F347RWA, MB96F347YSA, MB96F347YWA, MB96F348ASA, MB96F348AWA, MB96F348RSA, MB96F348RWA, MB96F348YSA, MB96F348YWA MB96F34XY/RB MB96F346ASB, MB96F346AWB, MB96F346RSB, MB96F346RWB, MB96F346YSB, MB96F346YWB, MB96F347ASB, MB96F347AWB, MB96F347RSB, MB96F347RWB, MB96F347YSB, MB96F347YWB, MB96F348ASB, MB96F348AWB, MB96F348RSB, MB96F348RWB, MB96F348YSB, MB96F348YWB MB96F35X MB96F356ASA, MB96F356AWA, MB96F356RSA, MB96F356RWA, MB96F356YSA, MB96F356YWA MB96F35XB MB96F356ASB, MB96F356AWB, MB96F356RSB, MB96F356RWB, MB96F356YSB, MB96F356YWB MB96F37X MB96F378HSA, MB96F378HWA, MB96F378TSA, MB96F378TWA, MB96F379RSA, MB96F379RWA, MB96F379YSA, MB96F379YWA MB96F38(8/9) MB96F388HSA, MB96F388HWA, MB96F388TSA, MB96F388TWA, MB96F389RSA, MB96F389RWA, MB96F389YSA, MB96F389YWA MB96F3(8/9)5 MB96F385RSA, MB96F385RWA, MB96F385YSA, MB96F385YWA, MB96F395RSA, MB96F395RWA, MB96F395YSA, MB96F395YWA MB96F38X MB96F386RSA, MB96F386RWA, MB96F386YSA, MB96F386YWA, MB96F387RSA, MB96F387RWA, MB96F387YSA, MB96F387YWA MB96F38XB MB96F386RSB, MB96F386RWB, MB96F386YSB, MB96F386YWB, MB96F387RSB, MB96F387RWB, MB96F387YSB, MB96F387YWB Page 6 of 185

7 European MCU Design Centre CI E-V21 Device shortcut MB9634(5/6) MB96F918 MB96F3(1/5)5 MB96F3(1/5)x Product name MB96345RSA, MB96345RWA, MB96345YSA, MB96345YWA, MB96346RSA, MB96346RWA, MB96346YSA, MB96346YWA MB96F918TSA, MB96F918HSA, MB96F918TWA, MB96F918HWA MB96F313RSA, MB96F313RWA, MB96F313YSA, MB96F313YWA, MB96F315RSA, MB96F315RWA, MB96F315YSA, MB96F315YWA, MB96F353RSA, MB96F353RSA, MB96F353RWA, MB96F353RWA, MB96F353YSA, MB96F353YSA, MB96F353YWA, MB96F353YWA, MB96F355RSA, MB96F355RSA, MB96F355RWA, MB96F355RWA, MB96F355YSA, MB96F355YSA, MB96F355YWA, MB96F355YWA MB96F313RSA, MB96F313RWA, MB96F313YSA, MB96F313YWA, MB96F315RSA, MB96F315RWA, MB96F315YSA, MB96F315YWA, MB96F353RSA, MB96F353RSA, MB96F353RWA, MB96F353RWA, MB96F353YSA, MB96F353YSA,MB96F353YWA, MB96F353YWA, MB96F355RSA, MB96F355RSA, MB96F355RWA, MB96F355RWA, MB96F355YSA, MB96F355YSA, MB96F355YWA, MB96F355YWA An overview of the functional limitation and the list of affected devices is given below. This table is showing most recent devices only, which are recommended for new designs. For the list of functional limitations for outdated devices, please refer to Table 3. Page 7 of 185

8 European MCU Design Centre CI E-V21 Table 2: List of functional limitations and affected devices (most recent devices recommended for new designs). Functional limitation 16FXFL0024: Side effect of disabled DMA controller channels Page MB96V300BRB MB96F3(1/5)5 MB96F3(1/5)x MB96F32XB MB96F33x MB96F348H/TC 88 F F F MB96F34XY/RB MB96F35XB MB96F37X MB96F38(8/9) MB96F3(8/9)5 MB96F38XB MB96F38(6/7/8/9) MB9634(5/6) MB9638XB MB96F918 16FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time 116 F F F F 16FXFL0033: FLASH Reset 120 F F F F 16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion 16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3 16FXFL0036: EDSU2 register not available on all devices (INT9 source selection) 124 F F F F F F F 130 F 133 F F F 16FXFL0037: Initial value of some I/O timer registers 136 F F F F F F F 16FXFL0038: Watchdog detection during debugging is not correct 16FXFL0039: Low voltage detector threshold levels differ from datasheet specification 16FXFL0040: Limitation in using P13_5 and P13_7 as input 140 D D D D F D F 144 D 147 F F F F F Page 8 of 185

9 European MCU Design Centre CI E-V21 Functional limitation 16FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt 16FXFL0042: Failure of String Instructions and WBTC/WBTS Instructions 16FXFL0043: Limitations for IRQ clearing of LIN- USART and RTC Page MB96V300BRB MB96F3(1/5)5 MB96F3(1/5)x MB96F32XB MB96F33x MB96F348H/TC MB96F34XY/RB MB96F35XB 152 F F F F F F F F F F F F F F 157 F F F F F F F F F F F F F F F 166 F F F F F F F F F F F F F F F 16FXFL0044: Limitation when using LCD segment F F F F F F F MB96F37X MB96F38(8/9) MB96F3(8/9)5 MB96F38XB MB96F38(6/7/8/9) MB9634(5/6) MB9638XB MB96F918 16FXFL0045: USB: STALL response release 180 F specification limitation of endpoint0 1) 16FXFL0046: USB: Specification of limitation on 184 F isochronous transfer 1) 1) Only valid for devices with USB controller The following table shows the functional limitations of outdated devices. It is not recommended to start new designs with these devices. Page 9 of 185

10 European MCU Design Centre CI E-V21 Table 3: List of functional limitations and affected outdated devices (not recommended for new designs) Functional limitation 16FXFL0001: Power-on debug feature 15 D 16FXFL0002: Peripheral access during debug mode 18 D 16FXFL0003: CANbus 3 output enable register 21 D 16FXFL0004: Guarded access break after conditional branch 24 D 16FXFL0005: Data value break on byte access 27 D 16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources 30 D 16FXFL0007: Bit positions in Real Time Clock register WTCKSR 33 D 16FXFL0008: Synchronous start of Programmable Pulse Generators 37 D 16FXFL0009: Embedded debug support data value break 40 D 16FXFL0010: Embedded debug support data write protection 43 D 16FXFL0011: EDSU USART Transmit Interrupt 46 D 16FXFL0012: DMA stop when CLKB > CLKP1/2 49 D 16FXFL0013: LCD prescaler 52 D 16FXFL0014: CLKP2 divider setting 55 D 16FXFL0015: Wake-up by RTC from timer mode 58 D 16FXFL0016: Interrupt while MOVS/MOVSW is executing 61 D D 16FXFL0017: Flash read buffer after programming 66 D 16FXFL0018: NMI relocation lock 69 D D 16FXFL0019: Phantom wake-up from timer or sleep mode 72 D D 16FXFL0020: Read value of PDR/EPSR 75 D D 16FXFL0021: Initial state of external interrupt flag 78 D D 16FXFL0022: Permitted settings for the Flash configuration registers 81 D 16FXFL0023: Usage of Flash read buffer 85 D 16FXFL0024: Side effect of disabled DMA controller channels 88 D D D D Page MB96V300RB MB96F32X MB96F348H/T MB96F348H/TB MB96F34XY/R MB96F35X MB9638X MB96F38(6/7/8/9) Page 10 of 185

11 European MCU Design Centre CI E-V21 Functional limitation 16FXFL0025: Increased current consumption 92 D 16FXFL0026: Feature emulation 95 D 16FXFL0027: Trace function limitation 99 D 16FXFL0028: Stuck on SW instruction break 102 D 16FXFL0029: Limitation in using Operand break points as trace triggers 105 D 16FXFL0030: Limitation in using Pass Count of Operand break points of DSU 108 D 16FXFL0031: Wrong instruction execution detection of DSU 111 D 16FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time 116 D D D 16FXFL0033: FLASH Reset 120 D D D D D D 16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion 124 D D D D D D D 16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3 130 D D 16FXFL0036: EDSU2 register not available on all devices (INT9 source selection) 133 D D D D 16FXFL0037: Initial value of some I/O timer registers 136 D D D D D D 16FXFL0038: Watchdog detection during debugging is not correct 140 D D D D D D 16FXFL0039: Low voltage detector threshold levels differ from datasheet specification 144 D D D D 16FXFL0040: Limitation in using P13_5 and P13_7 as input 147 D D D 16FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt 152 F F F F F F F F 16FXFL0042: Failure of String Instructions and WBTC/WBTS Instructions 157 F F F F F F F F 16FXFL0043: Limitations for IRQ clearing of LIN-USART and RTC 166 F F F F F F F F 16FXFL0044: Limitation when using LCD segment F F F Page MB96V300RB MB96F32X MB96F348H/T MB96F348H/TB MB96F34XY/R MB96F35X MB9638X MB96F38(6/7/8/9) Page 11 of 185

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13 FUJITSU SEMICONDUCTOR Power-on debug feature 16FX functional limitation 16FXFL0001 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

14 European MCU Design Centre 16FXFL0001 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 14 of 185

15 European MCU Design Centre 16FXFL0001 ver. 2 16FXFL0001: Power-on debug feature 1. Description of functional limitation The Power-on debug feature is not available. 2. List of affected Devices MB96V300RB 3. Detailed explanation The Power-on debug feature enables debugging the application right after powering up. This is implemented by separating the power supply for the application part and the debug support logic part of 16FX EVA chips. This feature is not available on the affected devices. 4. Possible workaround None. 5. Fujitsu countermeasure Future 16FX EVA chips will support the Power-on debug feature. Page 15 of 185

16 FUJITSU SEMICONDUCTOR Peripheral access during debug mode 16FX functional limitation 16FXFL0002 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

17 European MCU Design Centre 16FXFL0002 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 17 of 185

18 European MCU Design Centre 16FXFL0002 ver. 2 16FXFL0002: Peripheral access during debug mode 1. Description of functional limitation When the EVA chip is in debug mode and the feature is used to stop the peripheral clocks CLKP1/CLKP2 while being in debug mode, any read/write access to peripherals in clock domain CLKP1 or CLKP2 will freeze the MCU. 2. List of affected Devices MB96V300RB 3. Detailed explanation 16FX EVA chips offer the feature to stop peripheral clocks CLKP1 and CLKP2 while being in debug mode. This feature prevents that for example timers continue counting while the application is stopped by the user for inspection. If the counters would continue operation, they may overflow and the application would have to handle according interrupts directly after leaving the debug mode. However, since CLKP1 and CLKP2 are stopped when this feature is chosen, the debug system freezes when the user tries to read or write to registers in the CLKP1 or CLKP2 domain. 4. Possible workaround Memory content can be read or written as long as no registers in CLKP1 or CLKP2 domain are referenced. Avoid reading/writing to registers in CLKP1 and CLKP2 domain while in debug mode. 5. Fujitsu countermeasure Future 16FX EVA chips will enable to read register contents in CLKP1 and CLKP2 domain while being in debug mode, even when CLKP1 and CLKP2 are stopped. Write access to registers in CLKP1 or CLKP2 domain will be ignored. Page 18 of 185

19 FUJITSU SEMICONDUCTOR CANbus 3 output enable register 16FX functional limitation 16FXFL0003 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

20 European MCU Design Centre 16FXFL0003 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 20 of 185

21 European MCU Design Centre 16FXFL0003 ver. 2 16FXFL0003: CANbus 3 output enable register 1. Description of functional limitation CANbus channel 3 Output Enable Register COER3 has different offset than at other CANbus channels. It is 0xABE. It should be 0xACE. 2. List of affected Devices MB96V300RB 3. Detailed explanation The register layout of all CANbus controllers is the same, so that drivers can make use of a base address for each CANbus and constant offsets to address each register of the CANbus controller with the given base address. However, CANbus controller 3 has register COER3 on another offset than the other CANbus controllers. 4. Possible workaround Do not use CAN base address and register offset scheme, but individual register addresses as defined in 16FX C-header file. 5. Fujitsu countermeasure Future 16FX chips having CANbus controller channel 3 will have COER3 at address 0xACE. Page 21 of 185

22 FUJITSU SEMICONDUCTOR Guarded access break after conditional branch 16FX functional limitation 16FXFL0004 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

23 European MCU Design Centre 16FXFL0004 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 23 of 185

24 European MCU Design Centre 16FXFL0004 ver. 2 16FXFL0004: Guarded access break after conditional branch 1. Description of functional limitation Debug Support: If a guarded access area is defined directly behind a conditional branch instruction, the guarded access break is activated even when the conditional branch is taken. 2. List of affected Devices MB96V300RB 3. Detailed explanation See above. 4. Possible workaround None. 5. Fujitsu countermeasure Future 16FX EVA chips will not have this limitation. Page 24 of 185

25 FUJITSU SEMICONDUCTOR Data value break on byte access 16FX functional limitation 16FXFL0005 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

26 European MCU Design Centre 16FXFL0005 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 26 of 185

27 European MCU Design Centre 16FXFL0005 ver. 2 16FXFL0005: Data value break on byte access 1. Description of functional limitation Debug Support: Data value break on byte access can not be used. 2. List of affected Devices MB96V300RB 3. Detailed explanation Data value break on byte access can not be used. The byte on the other byte lane is not masked correctly (only lower bit is masked, not complete byte). Operand break (w/o data value break feature) is working without restriction on byte size and word size operands. 4. Possible workaround None. Do not use data value break on byte size. Use only data value break on words. 5. Fujitsu countermeasure Future 16FX EVA chips will not have this limitation. Page 27 of 185

28 FUJITSU SEMICONDUCTOR Wake-up from sleep mode by CLKP2 clock domain resources 16FX functional limitation 16FXFL0006 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

29 European MCU Design Centre 16FXFL0006 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 29 of 185

30 European MCU Design Centre 16FXFL0006 ver. 2 16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources 1. Description of functional limitation Resources in CLKP2 domain (like CANbus, Sound Generator) can not wake-up the device from sleep mode. 2. List of affected Devices MB96V300RB 3. Detailed explanation 4. Possible workaround All CANbus RX pins also have an external interrupt. External interrupts are located in the CLKP1 domain, which is not affected. Hence, for wake-up by CANbus, it is possible to use the external interrupt on the RX pin to wake-up the MCU from any low power mode. However, the wake-up event will always occur when the external interrupt detects a sensitive event on the RX/INT 5. Fujitsu countermeasure Future 16FX chips will not have this limitation. Page 30 of 185

31 FUJITSU SEMICONDUCTOR Bit positions in Real Time Clock register WTCKSR 16FX functional limitation 16FXFL0007 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

32 European MCU Design Centre 16FXFL0007 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 32 of 185

33 European MCU Design Centre 16FXFL0007 ver. 2 16FXFL0007: Bit positions in Real Time Clock register WTCKSR 1. Description of functional limitation RTC: bit position for write access of register WTCKSR:[CKSEL1:CKSEL0] should be bit [9:8], but is [1:0]. 2. List of affected Devices MB96V300RB 3. Detailed explanation INTE4 INT4 WTCER R/W R/W Initial value X X X X X X CKSEL1 CKSEL0 WTCKSR R/W R/W Initial value X X X X X X 0 0 Registers WTCER and WTCKSR are located at the lower and upper byte of a 16-bit word. At 16-bit read access, WTCER:INT4 and WTCER:INTE4 are located at bits 1 and 0, and bits WTCKSR:CKSEL1 and WTCKSR:CKSEL0 are located at bit 9 and 8, respectively. However, at 16-bit write access, WTCER:INT4 and WTCER:INTE4 are located at bits 1 and 0, but bits WTCKSR:CKSEL1 and WTCKSR:CKSEL0 are also located at bit 1 and 0, respectively. Hence, 1. when writing a 16-bit word to {WTCKSR, WTCER} the value on bit position 1 and 0 is written into WTCER:INTE4 and WTCER:INT4, and also into WTCKSR:CKSEL1 and WTCKSR:CKSEL0. 2. when writing a 8-bit word to WTCER the value on bit position 1 and 0 of WTCER is also written into WTCKSR:CKSEL1 and WTCKSR:CKSEL0. Read access to these register is not affected. Page 33 of 185

34 European MCU Design Centre 16FXFL0007 ver Possible workaround Do not use byte access to write the content of WTCER, because it will overwrite former content of WTCKSR:CKSEL1 and WTCKSR:CKSEL0. To set the content of {WTCKSR, WTCER} to the binary value XXXX.XXab.XXXX.XXcd, use the following procedure: Step 1. Make sure the RTC interrupt is disabled as by initial value of the Interrupt Control Register ICR for the interrupt vector of the RTC. 2. Write the content of {WTCKSR, WTCER} by 16-bit access, value = XXXX.XXab.XXXX.XXcd 3. Write the content of WTCKSR by 8-bit access, value = XXXX.XXab 4. Continue as usual, i. e. enable interrupts etc. Content of WTCKSR:INTE4, INT4 Initial value Content of WTCER:CKSEL1,CKSEL0 Initial value c, d c, d a, b c, d 5. Fujitsu countermeasure Future 16FX chips will not have this limitation. Page 34 of 185

35 FUJITSU SEMICONDUCTOR Synchronous start of Programmable Pulse Generators 16FX functional limitation 16FXFL0008 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

36 European MCU Design Centre 16FXFL0008 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 36 of 185

37 European MCU Design Centre 16FXFL0008 ver. 2 16FXFL0008: Synchronous start of Programmable Pulse Generators 1. Description of functional limitation For the Programmable Pulse Generators, the synchronous start of multiple channels by external trigger is not ensured. There may be a difference in start time by one CLKP1 cycle. 2. List of affected Devices MB96V300RB 3. Detailed explanation See above. 4. Possible workaround None. 5. Fujitsu countermeasure Future 16FX chips will not have this limitation. Page 37 of 185

38 FUJITSU SEMICONDUCTOR Embedded debug support data value break 16FX functional limitation 16FXFL0009 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

39 European MCU Design Centre 16FXFL0009 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 39 of 185

40 European MCU Design Centre 16FXFL0009 ver. 2 16FXFL0009: Embedded debug support data value break 1. Description of functional limitation The Embedded Debug Support which can be built with the memory patch function, features a data value break. The data value break can generate phantom breaks. 2. List of affected Devices MB96V300RB 3. Detailed explanation When using the data value break of the Embedded Debug Support implemented by the Memory Patch function, a break condition can be generated though the condition was not met. 4. Possible workaround None. Do not use data value break function in the embedded debug support of the memory patch unit or check in the interrupt handler, that the data value has matched. 5. Fujitsu countermeasure Future 16FX chips will not have this limitation. Page 40 of 185

41 FUJITSU SEMICONDUCTOR Embedded debug support data write protection 16FX functional limitation 16FXFL0010 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

42 European MCU Design Centre 16FXFL0010 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 42 of 185

43 European MCU Design Centre 16FXFL0010 ver. 2 16FXFL0010: Embedded debug support data write protection 1. Description of functional limitation The memory patch unit s embedded debug support does not feature data write protection. 2. List of affected Devices MB96V300RB 3. Detailed explanation The data patch function allows superseding the values read from a memory location by a value stored in the memory patch function. This is implemented by redirecting read accesses to the memory patch function. The memory location to be patched is not selected. However, write accesses to the memory location are not redirected. 4. Possible workaround None 5. Fujitsu countermeasure Future 16FX chips feature also write access redirection to the memory patch function. By this, it is possible to implement a write protection. Page 43 of 185

44 FUJITSU SEMICONDUCTOR EDSU USART Transmit Interrupt 16FX functional limitation 16FXFL0011 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

45 European MCU Design Centre 16FXFL0011 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 45 of 185

46 European MCU Design Centre 16FXFL0011 ver. 2 16FXFL0011: EDSU USART Transmit Interrupt 1. Description of functional limitation The register EDSU does not allow to map the transmit interrupt of the USART, which is selected by EDSU:SEL1, EDSU:SEL0, to the INT9 interrupt. However, performance of a debug system can be increased by offering the possibility to map the selected USART s transmit interrupt to the INT9 interrupt. 2. List of affected Devices MB96V300RB 3. Detailed explanation See above. 4. Possible workaround None 5. Fujitsu countermeasure Future 16FX chips EDSU register feature the bits EDSU:TIE and EDSU:TINT to map the selected USART s transmit interrupt to the INT9 interrupt. Page 46 of 185

47 FUJITSU SEMICONDUCTOR DMA stop when CLKB > CLKP1/2 16FX functional limitation 16FXFL0012 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

48 European MCU Design Centre 16FXFL0012 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 48 of 185

49 European MCU Design Centre 16FXFL0012 ver. 2 16FXFL0012: DMA stop when CLKB > CLKP1/2 1. Description of functional limitation DMA may stop after data transfer has completed when CLKB > CLKP. After this, no more DMA transfers can be done. 2. List of affected Devices MB96V300RB 3. Detailed explanation See above. 4. Possible workaround None. Do not use DMA on CLKP1 domain devices, when CLKB > CLKP1. Do not use DMA on CLKP2 domain devices, when CLKB > CLKP2. 5. Fujitsu countermeasure Future 16FX MCUs will be fixed to allow usage of DMA when CLKB > CLKP1 and CLKB > CLKP2.. Page 49 of 185

50 FUJITSU SEMICONDUCTOR LCD prescaler 16FX functional limitation 16FXFL0013 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

51 European MCU Design Centre 16FXFL0013 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 51 of 185

52 European MCU Design Centre 16FXFL0013 ver. 2 16FXFL0013: LCD prescaler 1. Description of functional limitation The LCD prescaler values do not allow operation of LCD w/ sub-clock/rc clock within frequency limits (frame rate < 90Hz). 2. List of affected Devices MB96V300RB 3. Detailed explanation See above. 4. Possible workaround None 5. Fujitsu countermeasure Future 16FX MCUs will offer different prescaler seetings in the LCR register. Old setting of LCR:FP1,FP0: FP1 FP0 When peripheral clock CLKP1 is selected When sub clk CLKSC or RC clock CLKRC is selected 0 0 F CLKP1 /(2 13 X N) F CLKP1 /(2 3 X N) 0 1 F CLKP1 /(2 14 X N) F CLKP1 /(2 4 X N) 1 0 F CLKP1 /(2 15 X N) F CLKP1 /(2 5 X N) 1 1 F CLKP1 /(2 16 X N) F CLKP1 /(2 6 X N) New setting of LCR:FP1,FP0: FP1 FP0 When peripheral clock CLKP1 is selected When sub clk CLKSC or RC clock CLKRC is selected 0 0 F CLKP1 /(2 13 X N) F CLKP1 /(2 8 X N) 0 1 F CLKP1 /(2 15 X N) F CLKP1 /(2 9 X N) 1 0 F CLKP1 /(2 17 X N) F CLKP1 /(2 10 X N) 1 1 F CLKP1 /(2 19 X N) F CLKP1 /(2 11 X N) Page 52 of 185

53 FUJITSU SEMICONDUCTOR CLKP2 divider setting 16FX functional limitation 16FXFL0014 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

54 European MCU Design Centre 16FXFL0014 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 54 of 185

55 European MCU Design Centre 16FXFL0014 ver. 2 16FXFL0014: CLKP2 divider setting 1. Description of functional limitation CLKP2 divider setting as defined by CKFCR:PC2D[3:0] = 0001 can only be used for frequency of: CLKS2 <= 26MHz (1.8V core voltage) CLKS2 <= 28MHz (1.9V core voltage) 2. List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation See above. 4. Possible workaround For CLKS2 <= 26/28MHz there is no restriction on the setting of CKFCR:PC2D[3:0]. For CLKS2 > 26/28MHz, use other settings for CLKP2, like 1:3, 1:4, 5. Fujitsu countermeasure Future 16FX MCUs will not have this limitation. Page 55 of 185

56 FUJITSU SEMICONDUCTOR Wake-up by RTC from timer mode 16FX functional limitation 16FXFL0015 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

57 European MCU Design Centre 16FXFL0015 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 57 of 185

58 European MCU Design Centre 16FXFL0015 ver. 2 16FXFL0015: Wake-up by RTC from timer mode 1. Description of functional limitation The real-time clock can not wake-up the MCU from timer mode 2. List of affected Devices MB96V300RB 3. Detailed explanation See above. 4. Possible workaround None. 5. Fujitsu countermeasure Future 16FX MCUs will not have this limitation. Page 58 of 185

59 FUJITSU SEMICONDUCTOR Interrupt while MOVS/MOVSW is executing 16FX functional limitation 16FXFL0016 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

60 European MCU Design Centre 16FXFL0016 ver. 4 Revision History Version Date Remark Initial version Improved description, added workarounds, added that Fujitsu will offer modified Assembler that enables workaround by commandline switch -@movs_16fx Added list of affected library functions Improved part number information in list of affected devices Page 60 of 185

61 European MCU Design Centre 16FXFL0016 ver. 4 16FXFL0016: Interrupt while MOVS/MOVSW is executing 1. Description of functional limitation When MOVSI, MOVSD, MOVSIW or MOVSDW instruction is executed and the source start address is an odd address (address not dividable by 2) and an interrupt is accepted by the CPU, then the fetched interrupt vector is invalid and the application crashes. 2. List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation When MOVSI, MOVSD, MOVSIW or MOVSDW instruction is executed and the source start address is an odd address (address not dividable by 2) and an interrupt is accepted by the CPU, then the fetched interrupt vector is invalid and the application crashes. When memory model small or medium (Data address space 16bit), the instructions MOVSI, MOVSD, MOVSIW or MOVSDW are used by the Softune C-compiler for the following C-language constructs: C-language construct Example Passing an argument of type struct or typedef struct { union to a function int len; The object which is passed as argument must start at an odd address Passing a return value of a function of type struct or union or double. Initializing a local variable of type struct or union char buf[20]; } my_type; void procedure_a(my_type); my_type my_struct; procedure_a(my_struct); // Problem, if my_struct has odd address typedef struct { int len; char buf[20]; } my_type; my_type my_struct; my_type procedure_b(void); my_struct = procedure_b(); // Problem, if return value of procedure_b // is on odd address. struct { int len; char buf[20] } my_struct = { 6, Hello! }; // Problem, if my_struct is on odd address. Copy variables of type struct or union or double struct { int len; char buf[20] } my_struct_a, my_struct_b; my_struct_a = my_struct_b; Page 61 of 185

62 European MCU Design Centre 16FXFL0016 ver. 4 C-language construct Example // Problem, if my_struct_b is on odd address Passing an argument to a function which is the return value of a previous function call of type double Sign inversion of a variable of type double double fabs(double); double sin(double); double x; x = fabs(sin(x)); double x, y; y = -x; // Problem if x is on odd address. The following table lists the library functions that are using the MOVSI, MOVSD, MOVSIW or MOVSDW instruction in certain memory models: Library function Memory model name LARGE COMPACT SMALL MEDIUM acos yes yes yes yes asin yes yes yes yes atan yes yes yes yes atan2 yes yes yes yes div yes yes yes yes ldiv yes yes yes yes log yes yes yes yes log10 yes yes yes yes pow yes yes yes yes tan yes yes yes yes atof yes yes ceil yes yes cos yes yes cosh yes yes exp yes yes floor yes yes fmod yes yes fprintf yes yes fscanf yes yes modf yes yes printf yes yes scanf yes yes sin yes yes sinh yes yes sprintf yes yes sscanf yes yes strtod yes yes tanh yes yes vfprintf yes yes vprintf yes yes vsprintf yes yes Page 62 of 185

63 European MCU Design Centre 16FXFL0016 ver Possible workaround Workarounds rely on exclusion of one of the three conditions of this limitation. Hence: 3. Avoid using MOVSI, MOVSD, MOVSIW or MOVSDW instruction. You can do by avoiding using above mentioned C-language constructs. Or you can only use memory model Large or Compact. 4. Avoid odd addresses for variables of type struct, union or double. When MOVSI, MOVSD, MOVSIW or MOVSDW is used with variables on even addresses, there is no limitation. 5. Avoid accepting interrupts while MOVSI, MOVSD, MOVSIW or MOVSDW is executing. This can be performed by the following modification of the assembly language code, which disables interrupts before executing MOVSI and re-enables it after MOVSI finishes: MOVSI DTB, ADB Original code PUSHW PS AND CCR, #0x0BF MOVSI DTB, ADB POPW PS Modified code 5. Fujitsu countermeasure 1. By November 30, 2006, Fujitsu will offer a modified version of 16LX/16FX Assembler tool. The new Assembler tool will have two new command line switches: Switch Call example Effect -@movs_16fx fasm907s -cpu MB96V300RB -@movs_16fx Special code will be generated in which interrupts are disabled during execution of MOVSI, MOVSD, MOVSIW or MOVSDW Ignore -@movs_16fx option (default behavior) 2. By November 30, 2006, Fujitsu will offer a library compiled with the modified Assembler tool with the command line switch to apply the workaround activated. 3. Future MCUs will not have this limitation. Page 63 of 185

64 FUJITSU SEMICONDUCTOR Flash read buffer after programming 16FX functional limitation 16FXFL0017 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

65 European MCU Design Centre 16FXFL0017 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 65 of 185

66 European MCU Design Centre 16FXFL0017 ver. 2 16FXFL0017: Flash read buffer after programming 1. Description of functional limitation During programming the Flash, the Flash Code and Data read buffer content becomes invalid. 2. List of affected Devices MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation See above. 4. Possible workaround Before programming, disable Flash read buffers by programming MFMCS:CRBE, DRBE, SFMCS:CRBE, DRBE. 5. Fujitsu countermeasure Future MCUs will not have this limitation. Page 66 of 185

67 FUJITSU SEMICONDUCTOR NMI relocation bit lock 16FX functional limitation 16FXFL0018 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

68 European MCU Design Centre 16FXFL0018 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 68 of 185

69 European MCU Design Centre 16FXFL0018 ver. 2 16FXFL0018: NMI relocation lock 1. Description of functional limitation Even when NMI is enabled, it is possible to relocate the NMI function to the NMI_R pin or vice versa by changing the value of PRRR7:NMI_R. By this, the NMI function can be deactivated or issued, depending on the state of the NMI and NMI_R pins. 2. List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation See above. 4. Possible workaround None. 5. Fujitsu countermeasure Future MCUs will not have this limitation. The bit PRRR7:NMI_R is locked when the NMI function is enabled. Page 69 of 185

70 FUJITSU SEMICONDUCTOR Phantom wake-up from timer- or sleep mode 16FX functional limitation 16FXFL0019 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

71 European MCU Design Centre 16FXFL0019 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 71 of 185

72 European MCU Design Centre 16FXFL0019 ver. 2 16FXFL0019: Phantom wake-up from timer or sleep mode 1. Description of functional limitation A phantom wake-up from timer mode or sleep mode can be generated. 2. List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation See above. 4. Possible workaround After wake-up, application should check for wake-up cause and return to sleep/timer mode if no wake-up cause was found. 5. Fujitsu countermeasure Future MCUs will not have this limitation. Page 72 of 185

73 FUJITSU SEMICONDUCTOR Read value of PDR/EPSR 16FX functional limitation 16FXFL0020 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

74 European MCU Design Centre 16FXFL0020 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 74 of 185

75 European MCU Design Centre 16FXFL0020 ver. 2 16FXFL0020: Read value of PDR/EPSR 1. Description of functional limitation When the general purpose ports PDR/EPSR are read, the read value is not the value at the time, the read is executed, but the value at the last time of a read or write access to any resource of clock domain CLKP1. 2. List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation See above. 4. Possible workaround Read the PDR/EPSR register twice and use last value. 5. Fujitsu countermeasure Future MCUs will not have this limitation. Page 75 of 185

76 FUJITSU SEMICONDUCTOR Initial state of external interrupt flag 16FX functional limitation 16FXFL0021 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

77 European MCU Design Centre 16FXFL0021 ver. 2 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Page 77 of 185

78 European MCU Design Centre 16FXFL0021 ver. 2 16FXFL0021: Initial state of external interrupt flag 1. Description of functional limitation The initial state of the external interrupt flags EIRRn:ER[7:0] have initial value 1 instead of required value List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation See above. 4. Possible workaround Do not rely on initial value of EIRR. 5. Fujitsu countermeasure Future MCUs will not have this limitation. Page 78 of 185

79 FUJITSU SEMICONDUCTOR Permitted settings for the Flash configuration registers 16FX functional limitation 16FXFL0022 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

80 European MCU Design Centre 16FXFL0022 ver. 3 Revision History Version Date Remark Initial version Revised header, 16FXFL number, formatting of tables Improved part number information in list of affected devices Page 80 of 185

81 European MCU Design Centre 16FXFL0022 ver. 3 16FXFL0022: Permitted settings for the Flash configuration registers 1. Description of functional limitation Not all settings of the Flash configuration registers described in the Hardware Manual are allowed. In certain cases this leads to a higher number of wait cycles. 2. List of affected Devices MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation Not all features of the Flash interface are supported by the affected devices. Hence some of the recommended settings in the HWM do not apply for these devices. Instead the Flash interface must be configured as described in the next chapter. 4. Possible workaround The MFMTC0:ADS and SFMTC0:ADS bits must always be set to 1. The MFMTC0:CLKBW and SFMTC0:CLKBW bits must always be set to 1. If the CLKB frequency is lower than the CLKS1 frequency (CLKB divider setting CKFRC:BCD not 0000 ), disable the code and data read buffer (Set MFMCS:DRBE, CRBE and SFMCS:DRBE,CRBE to 0 ). Recommended settings for Synchronous reading: Max CLKS1 frequency 25MHz 50MHz 56MHz CKFCR:BCD setting FMTC setting (number of Wait States) Code/data read buffer Div1 Enabled or 0239h (1WS) disabled Div2 Div16 Disabled Div1 Enabled or 223Ah (2WS) disabled Div2 Disabled Div3 Div h (1WS) Disabled Div1 4B3B (3WS) Enabled or disabled Div2, Div3 4B3A (2WS) Disabled Div4 Div16 4B39 (1WS) Disabled Page 81 of 185

82 European MCU Design Centre 16FXFL0022 ver. 3 Recommended settings for Synchronous reading and writing: Max CLKS1 frequency 20MHz 56MHz CKFCR:BCD setting Div1 Div2 Div16 Div1 Div2 Div16 FMTC setting (number of Wait States) 223Ah (2WS) 4B3D (5WS) Code/data read buffer Enabled or disabled Disabled Enabled or disabled Disabled Recommended settings for Asynchronous reading/writing: Max CLKS1 frequency 5MHz CKFCR:BCD setting Div1 Div2 Div16 FMTC setting (number of Wait States) 0231h (1WS) Code/data read buffer Enabled or disabled Disabled 5. Fujitsu countermeasure Future MCUs will not have this limitation. Page 82 of 185

83 FUJITSU SEMICONDUCTOR Usage of Flash Read buffer 16FX functional limitation 16FXFL0023 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

84 European MCU Design Centre 16FXFL0023 ver. 3 Revision History Version Date Remark Initial version Revised header Improved part number information in list of affected devices Page 84 of 185

85 European MCU Design Centre 16FXFL0023 ver. 3 16FXFL0023: Usage of Flash read buffer 1. Description of functional limitation The Flash read buffer cannot be used in all operation modes. 2. List of affected Devices MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA 3. Detailed explanation The Flash read buffer cannot be used in the following two cases: A divided CLKB clock is used (CLKS1 frequency higher than CLKB frequency) During Flash programming and erasing In both cases, invalid data could be read from the Flash. 4. Possible workaround Usage of a divided CLKB clock: Disable all read buffer by setting MFMCS:DRBE, CRBE and SFMCS:DRBE,CRBE to 0 before writing to the CKFCR:BCD bits. Flash programming and erasing: Disable all read buffer by setting MFMCS:DRBE, CRBE and SFMCS:DRBE,CRBE to 0 before submitting the program/erase command. The read buffer can be enabled again after termination of the program/erase algorithm. 5. Fujitsu countermeasure Future MCUs will not have this limitation. Page 85 of 185

86 FUJITSU SEMICONDUCTOR Side effect of disabled DMA controller channels 16FX functional limitation 16FXFL0024 European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen, Germany

87 European MCU Design Centre 16FXFL0024 ver. 4 Revision History Version Date Remark Initial version Improved part number information in list of affected devices Extended list of affected devices: MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA (as already in chapter Overview ) Extended list of devices: B versions of MB9634x and MB9638x. Page 87 of 185

88 European MCU Design Centre 16FXFL0024 ver. 4 16FXFL0024: Side effect of disabled DMA controller channels 1. Description of functional limitation A DMA controller channel that is not enabled can affect the operation of a DMA controller channel that is enabled, when the content of the DISEL register of both channels is the same. 2. List of affected Devices MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HWA, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348TSA, MB96F348TWA, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB, MB96V300RB-ES 3. Detailed explanation A DMA controller channel x that is not enabled (DER:ENx = 0), for which the content of the DISEL register is the same as the content of the DISEL register of a DMA controller channel y, that is enabled (DER:ENy = 1), can affect the operation of the DMA controller channel y. The effect is that if DMA controller channel y is receives an interrupt, it performs the data transfer correctly, but the interrupt is not filtered correctly. Instead of the interrupt being filtered as long as the Data Count register (DCT) is not 0, the interrupt is forwarded to the CPU. Hence, the DMA interrupt service routine is called at each data transfer and not only after the DMA has completed the transfer. 4. Possible workaround DISEL registers of DMA controller channels which are not intended to be used must be initialized to a value that is not used by DMA controller channels which are used. For example, all DISEL registers are initialized to a value that is never used by DMA, e. g. 12 (= delayed interrupt). Please take care not to overwrite the value of the DISEL register of disabled DMA channels later in the application. Page 88 of 185

89 European MCU Design Centre 16FXFL0024 ver Fujitsu countermeasure Type A: First countermeasure is to initialize DISEL registers at reset to a value that is never used by DMA controller channels (12 = delayed interrupt). For products of this type, please take care that the software does not override the content of the DISEL register of disabled DMA channels to a value that is used by enabled DMA channels. Type B: Second workaround is to remove the functional limitation. For these products, even when DISEL register content of a disabled channel x is the same as DISEL register content of enabled channel y, operation of channel y is not affected. Nevertheless, the content of all DISEL registers is reset to 12 at reset. The following table gives an overview of the status of different products. Product Functional Countermeasure type MB96V300RB MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA, MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB limitation present Yes Yes All other 16FX devices No Type B No countermeasure, please use software workaround Type A. Please take care not to override DISEL register of disabled channels to a value used in enabled channels. Page 89 of 185