MB ds90455-ds e-corr-x1-00. Fujitsu Microelectronics Europe GmbH

Transcription

1 Corrections of Hardware Manual MB ds90455-ds e-corr-x1-00 Fujitsu Microelectronics Europe GmbH Addendum, MB90455 Hardware Manual (DS E) This is the Addendum for the Datasheet DS E of the MB90455 microcontroller series. It describes all known discrepancies of the MB90455 microcontroller series Datasheet. Ref. Number (Internal ref. number) (Text Link) Date dd.mm.yy Version No. Chapter/Page Description/Correction DS V1.00 Typo corrected, WATCH Timer instead CLOCK Timer DS V1.01 Transition to standby mode, Standby Cancel failure behavior added ds90455-ds e-corr-x / 7

2 DS Wrong Timer name mentioned in whole Datasheet: Old: Clock Timer Correction: Watch Timer Features (page 2) Low power consumption (standby) mode Sleep mode (a mode that halts CPU operating clock) Time-base mode (a mode that operates oscillation clock, sub clock, time-base and clock only) Clock mode (a mode that operates sub clock and clock only) Timer Time-base, clock, watchdog : 1 channel Low power consumption (standby) mode Sleep mode (a mode that halts CPU operating clock) Time-base mode (a mode that operates oscillation clock, sub clock, time-base and watch only) Clock mode (a mode that operates sub clock and watch only) Timer Time-base, watch, watchdog : 1 channel PRODUCT LINEUP (page 4) Clock Timer Watch Timer 15-bit free-run counter Interrupt cycle: ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with khz sub clock) 15-bit free-run counter Interrupt cycle: ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with khz sub clock) ds90455-ds e-corr-x / 7

3 BLOCK DIAGRAM (page 13) Below Clock control circuit: Wrong Timer name mentioned CLOCK TIMER New: Watch Timer I/O Map (page 18) Address abbreviation 0000AAH WTC Clock control register Read/ Write R,R/W Resource Clock Initial value 1X001000B Address abbreviation 0000AAH WTC Watch control register Read/ Write R,R/W Resource Watch Initial value 1X001000B INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS (page 23) Interrup t source Clock Interrup t source Watch EI2OS readiness Interrupt control Interrupt vector register Number Address ICR Address B #28 1CH FFFF8CH ICR B8H*1 EI2OS readiness Interrupt control Interrupt vector register Number Address ICR Address B #28 1CH FFFF8CH ICR B8H*1 Priority *3 Priority *3 ds90455-ds e-corr-x / 7

4 PHERIPHERAL RESSOURCES (3) Watchdog Timer (page 32) The watchdog is a 2-bit counter that uses time-base or clock as count clock. If the counter is not cleared within an interval time, CPU is reset. The watchdog is a 2-bit counter that uses time-base or watch as count clock. If the counter is not cleared within an interval time, CPU is reset. Watchdog functions (page 32) The output target of a clock source is specified by the watchdog clock selection bit (WTC: WDCS) in the clock control register. Interval time of a watchdog is specified by the time-base output selection bit/clock output selection bit (WDTC: WT1, WT0) in the watchdog control register. Notes: When using the sub clock as machine clock, be sure to specify watchdog clock source selection bit (WDCS) in clock control register (WTC) at 0, selecting output of clock. The output target of a clock source is specified by the watchdog clock selection bit (WTC: WDCS) in the watch control register. Interval time of a watchdog is specified by the time-base output selection bit/watch output selection bit (WDTC: WT1, WT0) in the watchdog control register. Notes: When using the sub clock as machine clock, be sure to specify watchdog clock source selection bit (WDCS) in watch control register (WTC) at 0, selecting output of watch. Watchdog block diagram (page 31) Wrong description at the top. Clock control register (WTC) New: Watch control register (WTC) 6. Clock Timer Outline (page 38) The clock is a 15-bit free-run counter that increments in synchronization with sub clock. ds90455-ds e-corr-x / 7

5 The watch is a 15-bit free-run counter that increments in synchronization with sub clock. Interval function (page 38) In the clock, a bit corresponding to the interval time overflows (carry-over) when an interval time, which is specified by interval time selection bit, is reached. Then overflow flag bit is set (WTC: WTOF=1). If an interrupt by overflow is permitted (WTC: WTIE=1), an interrupt request is generated upon setting an overflow flag bit. Interval time of clock is selectable among the following seven choices: Interval time of clock : In the watch, a bit corresponding to the interval time overflows (carry-over) when an interval time, which is specified by interval time selection bit, is reached. Then overflow flag bit is set (WTC: WTOF=1). If an interrupt by overflow is permitted (WTC: WTIE=1), an interrupt request is generated upon setting an overflow flag bit. Interval time of watch is selectable among the following seven choices: Interval time of watch : Clock block diagram (page 39) Clock block diagram Watch block diagram Typo in block diagram: Clock counter Clock control register (WTC) Watch counter Watch control register (WTC) Typo below block diagram: Actual interrupt request number of clock is as follows : Actual interrupt request number of watch is as follows : Clock counter ds90455-ds e-corr-x / 7

6 A 15-bit up counter that uses sub clock (SCLK) as a count clock. Clock counter A 15-bit up counter that uses sub clock (SCLK) as a count clock. Counter clear circuit A circuit that clears the clock counter. A circuit that clears the watch counter. ds90455-ds e-corr-x / 7

7 DS Transition to standby mode The definition of Standby Cancel Failure is that the CPU will execute wrong instructions when an interrupt is executed during transition to Standby mode *0 at a certain time. Fujitsu can reproduce this phenomenon Fujitsu internally and has found the cause. *0:Definition of Standby mode Main sleep mode, PLL sleep mode, Sub-sleep mode Time base mode, Watch mode, Main watch mode Main stop mode, PLL stop mode, Sub-stop mode *Main watch mode is only for MB90370 series. In the following cases, no problem occurs: -Standby mode is not used -Standby mode is released only by external reset For further information refer to F2MC16-LX Standby Cancel Failure document. ds90455-ds e-corr-x / 7