Advanced Digital Verification Nathan Nipper. Cadence NCSim Demonstration John Martiney. Harris Corporation, 10/16/2007. assuredcommunications

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1 Advanced Digital Verification Nathan Nipper Cadence NCSim Demonstration John Martiney Harris Corporation, 10/16/2007 What is Verification Functional Verification is the task of verifying that the logic design conforms to specification When in Verification Complete? There is no general case solution that works in all cases most design are too complex to run all possible vector sets and get 100% verification Several Methods Logic Simulation Logic Emulation on test hardware (expensive) Formal Verification HDL Linting DVCon 2007 Trip Report - 2of 18

2 Why is Verification Important? Functional Verification is the best way to get full visibility into the workings of a design Good Verification will speed up integration and debug time in the lab Design bugs that are caught earlier in the process save money. The later a bug is found (if at all), the more it costs the project (time, labor, and money) Mediocre Verification can mean Failure for an ASIC DVCon 2007 Trip Report - 3of 18 Keynote Thoughts DVCon 2007 Trip Report - 4of 18

3 Bad News for Airbus October 2006 Virgin Atlantic Defers A380 by Four Years November 2006 FedEx Cancels Airbus A380 Order Switches to Boeing December 2006 Boeing Scores a Jumbo Coup Lufthansa orders 20 of Boeing s new stretch version of the 747, in a decision that deals a severe blow to rival giant-plane maker Airbus January 2007 UPS Airbus A380 Cancellation Imminent DVCon 2007 Trip Report - 5of 18 DVCon 2007 Trip Report - 6of 18

4 Could this happen in electronics? November 2000 Best Buy Puts Breaks on Pentium 4 This cost HP a lot of $$$ March 2006 Cingular, T-Mobile Halt RAZR Sales Due to Glitch Due to a technical glitch that causes the phone to drop calls or shut down December 2005 Microsoft Sued Over Alleged Xbox 360 Glitch Suit alleges the new video game console has a design flaw that causes it to overheat and freeze up. September 2006 Segway Recalls Scooters to Make Sure They Don t Change Course DVCon 2007 Trip Report - 7of 18 Aardvark CCA 16 x Layer Board 16 Xilinx Virtex 5 FPGAs for DSP algorithm 32,000 6-input LUTs 32,000 FFs 288 DSP Slices 250MHz internal operating freq 3560 Components Net Nodes 67 High-Speed Busses (500MHz and Up) 0.8 Terahertz aggregate data rate DVCon 2007 Trip Report - 8of 18

5 Verification Techniques Coverage Return Brute Force Stimulus Time Investment DVCon 2007 Trip Report - 9of 18 Brute Force Stimulus clk siga sigb DUT Outputs Tests very basic functionality Advantage: It s very fast to generate tests and get some quick preliminary results for small design blocks Disadvantage: Designer has to specify testcase at the waveform level DVCon 2007 Trip Report - 10 of 18

6 RTL-Generated Stimulus RTL Testbench clk siga sigb DUT Outputs VHDL/Verilog Testbench Description Advantages: Easier to generate more complicated testcases, since you now get the power of a language Can quickly make changes to generate new testcases Disadvantages: Takes some time up-front to get started Requires a good understanding of RTL DVCon 2007 Trip Report - 11 of 18 RTL Stimulus Snippets Generate a Clock clk_gen: process begin clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end process clk_gen; Generate a Reset reset_gen: process begin reset_n <= '0'; for i in 1 to 10 loop wait until clk'event and clk = '1'; end loop; reset_n <= '1'; wait; end process reset_gen; DVCon 2007 Trip Report - 12 of 18

7 RTL Stimulus Snippets Generate Signals siga <= 1 ; sigb <= 0 ; wait for 100 ns; siga <= 0 ; sigb <= 0 ; wait for 100 ns; siga <= 1 ; sigb <= 1 ; wait for 100 ns; DVCon 2007 Trip Report - 13 of 18 Command-Generated Stimulus Command Text-File Log File RTL Testbench clk siga sigb DUT Command-Driven Testbench RTL Testbench reads commands from an input file and writes results to a log Advantages: Even more complex test cases Easier to manage lots of different test cases Can change/create new test cases without recompiling Allow the testbench to check for any circuit errors Disadvantages: More time in setting up good to have a template up front DVCon 2007 Trip Report - 14 of 18

8 HVL Generated Random Stimulus Random Constraints Log File RTL Testbench clk siga sigb DUT HVL Testbench with Randomization (SystemC / System Verilog) RTL Testbench reads randomization constraints along with test parameters Results are verified against a truth model We use coverage tools to find out how much has been verified Advantages: You get very complex test sets that you would not have considered More confidence that everything will work the first time Disadvantages: Very long development cycle DVCon 2007 Trip Report - 15 of 18 PSL Assertions PSL Statements Are Placed in Comments, and begin with the keyword PSL -- psl opt_end_and_opt_valid : assert -- always ( opt_end -> opt_valid and not abort) and clk_kernel = '1' and opt_sig_clk_en = '1' ); -- abort (not reset_kernel_n); Temporal Layer always indicates that the property should always be true Also available is the never statement Also existing in the temporal layer are several operators that relate the different Boolean Equations -> is an implication operator A -> B means that if A is true, then B also must be true on the same cycle DVCon 2007 Trip Report - 16 of 18

9 Code Coverage Code Coverage is a method of determining how much of a design was verified with a particular vector set Coverage Parameters Block: Was each line of code exercised Expression: Was each branch exercised For example, both results of an if Toggle: Was every signal toggled in combinatorial expressions Paradigm shift from directed stimulus Instead of directing tests up from, we can randomize and then see how good we did DVCon 2007 Trip Report - 17 of 18 Formal Verification Formal Verification Writing Assertions and then using a formal engine to mathematically verify a design A lot of companies are using formal verification to fulfill portions of their verification plan Some are even using only formal verification at a block-level, then having only one top-level testbench Most companies in the industry seem to be using Verilog for RTL and System Verilog (SV) for verification DVCon 2007 Trip Report - 18 of 18

10 DVCon Overview About DVCon Using Hardware Design and Verification Languages Discuss the application of languages, tools and methodologies for the design and verification of electronic systems Focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and VERA Tools and methodologies include the use of testbench automation, assertion-based and formal verification, and transaction-level system design and verification. Who Attends Designers of electronic systems, ASICs and FPGAs Developers of EDA tools Presentations are highly technical in nature, and reflect real life experiences in using these languages and tools. DVCon 2007 Trip Report - 19 of 18 DVCon Troublemaker s Panel Rajeev Madhavan, CEO of Magma Design Automation Atul Sharan, CEO of Clear Shape Brett Cline, vice president of sales and marketing at Forte Jue-Hsien Chern, vice president and a division GM at Mentor Ted Vucurevich, CTO of Cadence Design Systems Vic Kulkarni, CEO of Sequence Design Gary Smith, EDA industry analyst (garysmitheda.com) John Chilton, senior vice president of marketing at Synopsys DVCon 2007 Trip Report - 20 of 18

11 The Troublemaker s Panel Cadence is definitively not going to open up its proprietary SKILL Pcell language Magma and Synopsys seem to be making up after a long legal dispute Magma s and its CEO claims it is gaining share. Video: Read the transcript here DVCon 2007 Trip Report - 21 of 18 Conclusions Verification is an incredibly important part of the design process You should have a verification plan at the beginning of a project with specific goals in mind As designs increase in complexity, advanced verification techniques are necessary to get the same amount of coverage DVCon 2007 Trip Report - 22 of 18