6 Month Certificate Program in VLSI Design & Verification" with Industry Level Projects. Tevatron Technologies Prívate Limited

Transcription

1 6 Month Certificate Program in VLSI Design & Verification" with Industry Level Projects.. : Tevatron Technologies Prívate Limited Embedded! Robotics! IoT! VLSI Design! Projects! Technical Consultancy! Education! STEM! Software! Recruitments

2 Process Flow Duration: 6 Months Total Fee: Rs (Tax Included). Internship Mode: Complete hands on sessions from experts. Working and understanding of all modules in details with different type of Projects. Understanding VLSI Project Life Cycle. Understanding VLSI Documentation. Eligibility: B.Tech/M.Tech Pass out or Last Semester. Certificate: 6 month Internship Certificate.

3 I Introduction to Program Key features of VLSI-Design + Verification Module ASIC & FPGA design Methodology Training and Internship Advanced Logic Design FPGA Architecture ASIC Verification Methodology HVL:- SystemVerilog HDL:- Verilog Assertions Based Verification UVM (Universal Verification Methodology) Three Mini Projects

4 I Introduction to Program Industry Standard Projects Industry Standard Project Scripting Language:- Perl Operating System :- Ubuntu + Windows EDA Tool:- Mentor Graphics Questa Sim, ModelSim SE and DE Xillinx ISE

5 Different Level of Projects and Areas: Industry Standard Projects AHB2APB Bridge RTL UART IP core RTL Design AHB UVC - Master agent in UVM AHB2APB Bridge verification in UVM UART IP Verification in UVM AHB UVC - Slave agent in UVM GPIO Verification in UVM AXI UVC- Master agent in UVM I2C Real Time Clock IP design AXI UVC - Slave agent in UVM SPI IP verification UVM

6 Module 1 Introduction to VLSI VLSI & FPGA Design flow RTL Design Methodology Introduction to ASIC Verification methodology ASIC & FPGA Module 2 Advanced Logic DESIGN Logic Gates overview Combinational Circuits designing Arithmetic logic circuits Latches and flip-flops

7 . Shift registers and counters Sequential logics Memories and PLDs FSM Module 3 Introduction to LINUX Components of Linux Directory Structure Utilities and commands Vi editor

8 Module 4 Verilog HDL Introduction to Verilog Application and use of HDL Levels of abstraction Modelling styles Modelling methodology Data Types Nets and registers Synthesizable and non-synthesizable constructs Arrays Memories

9 Verilog operators Logic operators Arithmetic operators Bitwise and Reduction operators Concatenation operator Conditional operators Relation operators Shift and Equality operators Assignments statements Types of assignments in verilog Continuous Assignments Timing settings

10 Procedural statements Blocking and non-blocking assignments Task and functions Mini Project Finite state machines Basics of FSM Moore vs Mealy FSM coding Styles Vending Machines designing Mini project

11 Advanced Verilog for Verification System Task Internal variable Monitoring Compiler Directives File input and output operation Mini Project Code Coverage Statement Coverage Branch Coverage Expression coverage Toggle coverage Path coverage

12 Condition coverage FSM coverage Major Project Based on Verilog HDL

13 Module 5 Static timing Analysis Introduction to STA Comparison with DTA Timing Path and Constraint Different types of clock Clock domain and variations Clock Distribution Network How to fix timing failure

14 Module 6 CMOS fundamental Non-ideal Characteristics BJT vs FET CMOS characteristics CMOS layout designing Stick Diagram CMOS fabrication Process CMOS technology current trends

15 Module 7 ASIC verification Directed vs Random Function verification process Stimulus Generation Bus functional Module Monitor and reference Module Coverage Driven verification Verification Planning and management

16 Module 8 System Verilog Introduction to system Verilog New Data Types Task and functions Interface Clocking Block OOP and randomization OOP basic Classes- object and handles Polymorphism and inheritance Randomization Constraints

17 Threads and virtual interfaces Fork join Fork join_none Fork join_any Event control statements Mailbox and Semaphores Virtual interface Transactors Building verification environment Testcases Callbacks Façade class Building Reusable Transactor

18 . Inserting callbacks Registering callbacks Functional Coverage Coverage Model Coverpoint and bins Cross coverage Regression testing Defining verification plan Creating the testbench Implementing BFMs Implementing the coverage model Defining the transactor Generating the function and code coverage reports

19 Corner cases and direct test cases. Building the regress testcases. Generating the function and code coverage reports Module 9 Assertion Based verification Introduction to ABV Immediate Assertions Simple Assertion Sequences Sequence Composition Advanced SVA features Assertion Coverage

20 Module 10 Verification Planning and management Verification plan TB Architecture Coverage Model Tracking the stimulation process Building regression testsuite Major project

21 Module 11- UVM Introduction to UVM Overview of Project UVM tb architecture Stimulus Modelling Creating UVCs and Environment UVM stimulation phases Testcases classes TLM overview Configure TB Environment UVM Sequences UVM Sequencers

22 Connecting DUT- virtual Interface Virtual sequences and sequencers TB infrastructure Building Scoreboard Module 12 Design Automation: - Perl scripting Introduction to Perl Functions and statement Number, string, quotes Variables Comments and loops

23 Module 13 FPGA Interfacing Introduction to FPGA FPGA architecture of Spartan-3E XCs500E RS232 serial (Rx & Tx) PS2 Mouse and Keyboard Character LCD interfacing VGA interfacing Buttons interfacing (DE bouncing effect) Slide Switches 7 Segment LED Display

24 Miniproject Digital Control Access Serial to LCD PWM motor controlling Vending Machine Image processing on FPGA integrated with Matlab

25 Recruitment and Placements Candidates Training are first screened is provided by according us: Resume, to the Technical candidate Ability ability. Test, Interview Periodical assessments after each module for better understanding of Technology & Tool. Project based Learning where they learn come to know about Project Life Cycle 24 * 7 live LMS Support. Monthly session by Experts about what is going in the Industry. Training on Live Projects. Preparation for the Interview Profile Sharing to selected Companies for the Interview. Note: As an organization, TEVATRON TECHNOLOGIES PRIVATE LIMITED hereafter referred as TEVATRON DOES NOT CHARGE ANY MONEY for recruiting candidates in TEVATRON TECHNOLOGIES PRIVATE LIMITED COMPANY nor does it have authorized agencies or firms to conduct recruitment on its behalf. TEVATRON TECHNOLOGIES PRIVATE LIMITED has not appoint any agents/agency/company/individual to make job offers on behalf of the company in lieu of money. Candidates need to be cautious and not trust agencies or individuals charging fees for their services while claiming to be TEVATRON s representatives. TEVATRON also requests candidates to report such instances/individual names to hr@tevatrontech.com, so that it can take necessary action tthrough the law enforcement agencies. Any offer letter can be verified by writing to hr@tevatrontech.com

26 THANKS FOR APPLYING