Overview on Hardware Optimizations for Database Engines

Transcription

1 Overview on Hardware Optimizations for Database Engines Annett Ungethüm, Dirk Habich, Tomas Karnagel, Sebastian Haas, Eric Mier, Gerhard Fettweis, Wolfgang Lehner BTW 2017, Stuttgart, Germany,

2 Interaction DB-Engine and Hardware Applications/Database Engines Well-Known Challenge: Exploit hardware technology by specific data management techniques (indexing, data storage, query & transaction processing) Main Memory CPU Modern Hardware 1e+07 memory (KByte) 1e+06 1e #cores

3 Era of Dark Silicon MOORE S LAW DARK SILICON Number of transistors in a dense integrated circuit doubles approximately every two years. 1e+07 We can no longer power the transistors that Moore is giving us #transistors (x1000) process (nm) 1e+06 1e

4 HW/SW Co-Design for DB-Engines Applications/Database Engines Challenge: HW/SW Co-Design for Database Engines Specialization of Hardware to overcome Dark Silicon Modern Hardware 4

5 Outline HARDWARE FOUNDATION INTELLIGENT DMA CONTROLLER EXTENSIONS FOR PROCESSING ELEMENTS 5

6 Hardware Foundation TOMAHAWK PLATFORM 6

7 Hardware Foundation Zoom In 7

8 Hardware Foundation Zoom In (2) Control-Plane CORE MANAGER (CM) Extended Xtensa-LX5 from Tensilica (now Cadence) 32KB for code 64KB for data PROCESSING ELEMENTS (PE) Xtensa-LX5 from Tensilica (now Cadence) 32KB for code 2x32KB for data on PE APPLICATION CORE (APP) 570T core from Tensilica (now Cadence) Control-Plane 8

9 Outline Control-Plane PART I: EXTENSIONS OF PROCESSING ELEMENTS Control-Plane 9

10 Development Flow int res= (v0 + v1 + v2) >> shift8; DEVELOPMENT OF INSTRUCTION SET EXTENSIONS WITH TENSILICA TOOLS Tensilica Instruction Extension (TIE) language C/TIE compiler Cycle accurate simulator/debugger Processor generator SYNTHESIS OF RTL CODE // shift8 -> internal state int res=add3_shift(v0, v1, v2); Synopsys Design Compiler, PrimeTime PX TSMC CMOS LP 65nm libraries 10

11 Investigated Database Primitives 2014 Bitmap Compression and Processing (AND, OR, XOR) Hashing Sorted Set Operations Primivites WAH PLWAH COMPAX Hash + Lookup Hash + Insert Hash Keys Hash Sampling CityHash32 Merge Sort Intersection Union Difference Sort-Merge Join Sort-Merge Aggregation (SUM) 11

12 General Approach for all Extensions Extended Tensilica LX5 Processor Instruction Set Data Prefetcher Basic RISC Instruction Set Application-Specific Instruction Set Instruction fetch 64 bit Local Instruction Memory Register Files Basic Registers Load-Store Unit bit Local Data Memory 0 Interconnect Application-Specific Registers Application-Specific States Load-Store Unit bit Local Data Memory 1 12

13 Bitmap Primitives BITMAPS ARE A SPECIAL KIND OF INDEX BITMAPS COMPRESSION Table T bit length equals number of tuples bitmap index OID X =0 =1 =2 = b 1 b 2 b 3 b 4 WORD-ALIGNED HYBRID (WAH) CODE Stateless compression Run-length-encoding (RLE) - run of 0 s and 1 s WAH bitmaps contain RLE - compressed fills and - uncompressed literals Bit-wise OR select * from T where X < 2 13

14 Bit-Wise OR on Compressed Bitmaps 32 bit words In hex b FFFFF... WAH b1 Bit-wise OR WAH b2 Literal 0 fill 10<runlength> Literal FFFFF 7FFFFFFF OR OR OR OR C C0001E0 3FE <runlength> 1 fill Literal Literal Logical operations (AND, OR, XOR) on two compressed bitmaps 1) Load WAH word(s) 2) Calculate output (Fill-Fill, Literal-Fill, Literal-Literal) 3) Combine output b2 7FFFFFFF 7FFFFFFF 7C0001E0 3FE

15 C-Code WHILE(XIDX!=XSIZE && YIDX!=YSIZE) { //new X or Y? Calculate new fill count if(xisfill==1 && YisFill==1) { //2 fills } if(xfillwords<yfillwords) min=xfillwords; else min=yfillwords; writefill(comprresultbi,&zidx,x[xidx] Y[Yidx],min); XfillWords-=min; YfillWords-=min; else if((xisfill==1 && YisFill==0) (XisFill==0 && YisFill==1)) { } if(xisfill==1){ XfillWords--; if((x[xidx]&0xc )==0xc ) writefill(comprresultbi, &Zidx, 0xC , 1); else { comprresultbi[zidx]=y[yidx]; Zidx++; } Fill-Fill Literal-Fill if(yisfill==1){ YfillWords--; if((y[yidx]&0xc )==0xc ) } } } else { } writefill(comprresultbi, &Zidx, 0xC , 1); result=x[xidx] Y[Yidx]; else {comprresultbi[zidx]=x[xidx]; Zidx++; } Literal-Literal if((result&0x7fffffff)==0x7fffffff) writefill(comprresultbi, &Zidx, 0xC , 1); else if((result&0x7fffffff)==0) writefill(comprresultbi, &Zidx, 0x , 1); else { comprresultbi[zidx]=x[xidx] Y[Yidx]; Zidx++; } 15

16 Processing with PE Extension Initial Load Load Prepare Store Store Memory 0 Application specific states Preprocessing Application specific states Memory 0 Operation Memory 1 Postprocessing Memory 1 M E M O R Y 0 M E M O R Y FFFFF F C C0001E0 3FE Align to 128-bit lines ldxstream() ldystream() Is word fill or Literal? -> fill -> overwrite input words Perform operation OR v => Write to output stream -> append or overwrite previous word with increased fill counter Proceed to next word (4x) 4 x WAHinst() Buffer result M E M O R Y 0/1 16

17 Bit-Wise OR on Compressed Bitmaps 32 bit words In hex b FFFFF WAH b1 Bit-wise OR WAH b2 b2 Literal 0 fill Literal FFFFF OR OR OR OR C C0001E0 3FE fill Literal Literal 7FFFFFFF 7FFFFFFF 7C0001E0 3FE00000 Code with Extension do{ ldxstream(); ldystream(); WAHinst(); WAHinst(); WAHinst(); } while(wahinst()); 17

18 Many More Extensions Bitmap Compression and Processing (AND, OR, XOR) Hashing Sorted Set Operations Extension Processor WAH PLWAH COMPAX Hash + Lookup Hash + Insert Hash Keys Hash Sampling CityHash32 Merge Sort Intersection Union Difference Sort-Merge Join Sort-Merge Aggregation (SUM) BitiX X X X HASHI X X X X X Titan3D X X X X X X X Tomahawk DBA X X X X X X 18

19 Evaluation REFERENCE PROCESSORS Tomahawk DBA Processor --> Set of different DB-Extensions for WAH-Compression, Hashing, and Sortes-Set Operations Processor Tomahawk without DBA Tomahawk with DBA Description Basic Xtensa LX5 without instruction set extensions, 1 LSU, 32-bit memory interface Set of different DB-Extensions for WAH- Compression, Hashing and Sorted-Set Operations Technology [nm] A total [mm²] f MAX [GHz] P MAX f MAX Comparison Intel i7-6500u Low-power Intel 2-core processor based on Skylake architecture, 4MB L3 cache 14 99*

20 Evaluation - Bitmaps 20

21 Outline PART 2: INTELLIGENT DMA CONTROLLER 21

22 Problem Statement T2 RISC Core T2 RISC Core T2 RISC Core 0 0xCCA 1 0x00B Local Memory t AN Cache APP APP t NA Tensilica 570T Local Memory NoC Local Memory CM CM LX4-ISA_E Local Memory t NMc t McN Memory Controller Synopsys DWC DDR2 Problem: Many round-trips for key lookups t McM t MMc Approach: Teach B-trees to the memory controller 2 0x0FA Memory 3 0x1FD Micron DDR2 SDRAM 4 0xDE1 5 0x0ED 6 0x00E 7 0xD0A t APP 22 22

23 Intelligent Main Memory Controller (idma) Core Core Core 0 0xCC6 1 0x000 Local Memory t NC t CN Cache APP Local Memory NoC Local Memory CM Local Memory t NP t PN Pointer Chaser t PMc t McP Memory Memory Memory Controller Controller Controller Synopsys DWC Synopsis DDR2 t McM t MMc Vision (and first simulations) Intelligent memory controller Is aware of the semantics of memory layout Implements core operations (e.g. lookup) Implementation (no yet in silicon) 0,183mm² PE with 200Mhz 2 0x0F0 Memory 3 0x1FD 4Micron 0xDE1 DDR2 SDRAM 5 0x0ED 6 0x00E 7 0xD0A 23 23

24 First idma Design 24

25 Evaluation using Simulator 25

26 Summary HARDWARE FOUNDATION INTELLIGENT DMA CONTROLLER EXTENSIONS FOR PROCESSING ELEMENTS 26

27 Overview on Hardware Optimizations for Database Engines Annett Ungethüm, Dirk Habich, Tomas Karnagel, Sebastian Haas, Eric Mier, Gerhard Fettweis, Wolfgang Lehner BTW 2017, Stuttgart, Germany,