Resource Efficiency of Scalable Processor Architectures for SDR-based Applications

Transcription

1 Resource Efficiency of Scalable Processor Architectures for SDR-based Applications Thorsten Jungeblut 1, Johannes Ax 2, Gregor Sievers 2, Boris Hübener 2, Mario Porrmann 2, Ulrich Rückert 1 1 Cognitive Interaction Technology Center of Excellence (CITEC), Bielefeld University 2 Heinz Nixdorf Institute, University of Paderborn

2 Motivation: Resource efficient processor architectures - Increasing complexity of mobile applications - More functionality - New communications standards (LTE Advanced: 1 GBit/s) - Multimedia applications (Video, 3-D, ) - Static hardware solutions Flexible software implementations (e.g., Software-defined radio - SDR) Powerful CPU necessary - High requirements to resource efficiency! RADCOM 2011 Slide 2

3 Motivation: VLIW architectures - RISC architectures allow for higher performance by increasing clock frequency Power consumption increases memory - Parallel architectures enable high performance at a reasonable low clock frequency FE DC RD Fetch Fetch Fetch Fetch Fetch Decode Decode Decode Decode Register Read Register Register Read Read Register Read Register Read High resource efficiency Data memory EX ME * / * / * / LD/ST LD/ST LD/ST LD/ST LD/ST ory ory ory ory ory 3... * /... n-1 * / WR Register Write Register Write Register Write Register Write Register Write - pared to superscalar architectures - VLIW (Very-Long Word)-architectures leave the scheduling to the compiler Low resource requirements RADCOM 2011 Slide 3

4 Design-space Exploration (DSE): Design flow Goal: Automated design flow! Definition of the semantic Vice-UPSLA Benchmarks Source code RTL description planned UPSLA (C-)piler RTL code Reference specification Assembler code RTL simulation Assembler RTL code Object files Synthesis Executable Linker Netlist Executable Emulator (Prototype) ASIC realization set simulator Profiling statistics Functional verification Visualization/ Profiling Resourcen efficiency RADCOM 2011 Slide 4

5 Modular VLIW-architecture memory FE DC Fetch Decode RD Register Read Bypass Data memory EX ME 0 1 * / * / LD/ST LD/ST LD/ST ory n-1 * / Condition register Register WR Register Write RADCOM 2011 Slide 5

6 Normalized Area/Power Normalized Latency Normalized number of clock cycles DSE (core level) - Trade-off between - clock cycles - clock frequency - area requirements - power consumption 1 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1 Slot 2 Slot 3 Slot 4 Slot Number of VLIW slots Number of VLIW slots RADCOM 2011 Slide 6

7 DSE (core level) - Trade-off between - clock cycles - clock frequency Cache FE DC Fetch Decode - area requirements - power consumption RD Register Read Bypass EX Data Cache LD/ST 0/2* / 0/2 LD/ST 1/3* / 1/3 Condition register ME ory Register WR Register Write The architecture 4x s 2x Multiply-accumulate 2x Division-step 2x Load/Store 31 General purpose registers 8 condition registers RADCOM 2011 Slide 7

8 VLIW-architecture: Key features Harvard architecture (LD/ST architecture) Six-staged pipeline (non-interlocked) compression 31 general purpose registers, 2x8 bit condition register 41 Base instructions 15 SIMD instructions 1-cycle-instructions, 1 cycle latency (MLA, BR, LDW: 2 cycles, DIV: 32 cycles) Parameterizable instruction alignment buffer (L0-cache) ARM-like instruction set (binary compiler) prehensive pipeline bypass 16-bit SIMD mode st cond Opcode Rn Rd Rm or immediate Bit RISC instructions RADCOM 2011 Slide 8

9 DSE (system level): Hardware accelerators (HWACC) 0: Data memory 1: Hardware extension memory Module number FE DC RD Module address Fetch Decode Register Read Bypass Data memory Address decoder EX 0 2 LD/ST 0/2* / 0/2 LD/ST 1 3 1/3* / 1/3 Condition register HWACC #1 ME ory Register HWACC #2 HWACC #3 WR Register Write RADCOM 2011 Slide 9

10 DSE (system level): Hardware accelerators (HWACC) Hardware accellerator Processing Time (Speedup) Additional hardware extensions: - UART (debugging) - Ethernet MAC - Clock counter - FIFOs - Area Requirements Power consumption CRC - 87 % (Speedup: x 8) % % x 6.8 Energy efficiency ECC - 93 % (Speedup: x 14) + 30 % + 30 % x 11.0 IEEE b - 88 % (Speedup: x 8) + 40 % + 19 % x 6.0 AES % (Speedup: x 66) + 39 % + 54 % x 43.0 RADCOM 2011 Slide 10

11 DSE (system level): Flexible integration of HWACCs SDRAM - L1-cache, external SDRAM - set extensions HWACC SDRAM Systembus Systembus Arbiter Instr.- Cache Daten- Cache Systembus CPU ISE ISE ISE - Hardware accelerators - Generic interface for external hardware extension ETH MAC MMIO CRC Lokalbusschnittstelle HWACC IEEE b EXT CRC MMIO ETH MAC ECC FPGA FPGA ASIC ETH PHY RAPTOR-System ETH PHY Host-PC RADCOM 2011 Slide 11

12 FPGA prototype based on RAPTOR system Ethernet MAC FE Fetch / L1 Cache ory DC Decode Bypass RD Register Read PHY PHY PHY PHY Condition Register EX * / * / * / * / Register ME LD/ST LD/ST LD/ST LD/ST L1 Data-Cache ory WR Register Write RADCOM 2011 Slide 12

13 Externally supplied Voltage Control µ JTAG Managment FPGA prototype based on RAPTOR system Ethernet MAC PHY PHY PHY PHY Bypass Condition Register Register FE DC RD EX ME Fetch / L1 Cache Decode Register Read * / * / * / * / LD/ST LD/ST LD/ST LD/ST L1 Data-Cache ory ory Power I2C JTAG I2C JTAG Power Subsystem Power Subsystem Configuration JTAG Xilinx Spartan-3A DSP XC3SD3400A, XC3SD1800A (compatible) x 51 Previous Module 51 High-Speed Differential I/Os DB-USRP 85 I/O RX High-Speed Differential I/Os Connector TX-DB MxFE Processor AD9862 D/A transmit signal path TX 2 x 14 two 14-Bit 128 MSPS A/D receive signal path RX 2 x 12 two 12-Bit 64 MSPS AUX ADC AUX DAC VIN 4 IOUT 4 I/O RX 16 Connector RX-DB 2 x 51 Next Module 102 WR Register Write 85 Local Bus RADCOM 2011 Slide 13

14 Externally supplied Voltage Control µ JTAG Managment FPGA prototype based on RAPTOR system Ethernet MAC PHY PHY PHY PHY Bypass Condition Register Register FE DC RD EX ME Fetch / L1 Cache Decode Register Read * / * / * / * / LD/ST LD/ST LD/ST LD/ST L1 Data-Cache ory ory Power I2C JTAG I2C JTAG Power Subsystem Power Subsystem Configuration JTAG Xilinx Spartan-3A DSP XC3SD3400A, XC3SD1800A (compatible) x 51 Previous Module 51 High-Speed Differential I/Os DB-USRP 85 I/O RX High-Speed Differential I/Os Connector TX-DB MxFE Processor AD9862 D/A transmit signal path TX 2 x 14 two 14-Bit 128 MSPS A/D receive signal path RX 2 x 12 two 12-Bit 64 MSPS AUX ADC AUX DAC VIN 4 IOUT 4 I/O RX 16 Connector RX-DB 2 x 51 Next Module 102 WR Register Write 85 Local Bus 128 MSPS A/D converter Spartan-3 ADSP FPGA for data pre-processing Modular approach 0-5 GHz transceivers RADCOM 2011 Slide 14

15 ASIC prototype in 65nm Package Test board - Standard cell implementation - 65 nm STMicroelectronics MHz mm² area requirements - 32 kb L1-Cache Die photo/layout - ~100 mw power consumption RADCOM 2011 Slide 15

16 DSE (NoC level) GigaNoC based on CPU RADCOM 2011 Slide 16

17 DSE (NoC level) GigaNoC based on CPU 2D mesh-topology Wormhole routing Highly scalable switching 5 I/O-ports per SB 750 MHz, 0.5 mm²/sb 24 Gbit/s link bandwidth RADCOM 2011 Slide 17

18 DSE (NoC level): IEEE b application Port Port Scrambling Diff. encoding Symbol mapping Scrambling Diff. encoding Symbol mapping Scrambling Diff. encoding Symbol mapping Fir-Filter (I-Part) Fir-Filter (I-Part) Port Port Fir-Filter (Q-Part) Fir-Filter (Q-Part) Synchronization RADCOM 2011 Slide 18

19 Clock cycles per Byte DSE (NoC level): IEEE b application 4000 Port Port Scrambling Diff. encoding Symbol mapping Scrambling Diff. encoding Symbol mapping Scrambling Diff. encoding Symbol mapping Fir-Filter (I-Part) Fir-Filter (I-Part) NoC (1 PE) -NoC (2 PE) -NoC (4 PE) Port Port Input data [Bytes] Fir-Filter (Q-Part) Fir-Filter (Q-Part) Synchronization RADCOM 2011 Slide 19

20 Thank you for your attention Dipl.-Ing. Thorsten Jungeblut Cognitive Interaction Technology Center of Excellence (CITEC), Bielefeld University Universitätsstraße Bielefeld Phone : Fax. : tj@cit-ec.uni-bielefeld.de RADCOM 2011 Slide 20