Do not open this exam until instructed to do so. CS/ECE 354 Final Exam May 19, CS Login: QUESTION MAXIMUM SCORE TOTAL 115

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1 Name: Solution Signature: Student ID#: Section #: CS Login: Section 2: Section 3: 11:00am (Wood) 1:00pm (Castano) CS/ECE 354 Final Exam May 19, This exam is open book/notes. 2. No calculators. 3. Write all answers on the sheet provided; show your work for partial credit! 4. You have 2 hours to complete this exam. QUESTION MAXIMUM SCORE TOTAL 115 Do not open this exam until instructed to do so.

2 1. Perform the following single precision floating point computations. Use the default rounding mode if the answer is not exactly representable. Show your work. (A)Perform the following addition: Add hidden bit, align, and subtract Already normalized, remove hidden bit xC493D400 (B) Perform the following division: Add hidden bit and divide fractions Round to 1 because greater than 1/2 lsb Subtract exponent, renormalize and round Remove hidden bit x8ec16aab Spring 2000 Page 2 of 9 Final Exam }

3 2. The IEEE single precision floating point standard defines representations for infinities. (A)Give one example of a floating point operation that produces an infinity. 1/0 (B) Give one example of a floating point operation that results in a normalized single-precision result even though one of the source operands was an infinity. 1/infinity (C) How are infinities represented in the single precision standard? E = 255, F = 0, S = 0 or 1 3. A processor with 32-bit addresses has a one-way set-associative data cache (this is also referred to as a direct-mapped cache; a given block in memory only can be stored in a specific cache line/ frame). Suppose the cache has 16 lines (frames) with 64 data bytes each. In case of a cache miss, the corresponding memory block is immediately loaded in the cache. (A)a) For a load word from address 0x0020a7f53 that hits in the cache, indicate: i) the index (i.e., the cache line/frame referenced), ii) the offset (i.e., the byte(s) accessed within that line), and iii) the tag (i.e., the contents of the line tag field). Index Offset Tag 0xD 0x13 0x0829F Spring 2000 Page 3 of 9 Final Exam

4 4. The MIPS architecture supports a 32-bit paged virtual address space. Both the virtual address space and physical memory are broken into 4096 byte pages. The CPU generates a 32-bit virtual address which is translated into a 32-bit physical address. The operating system kernel maintains an array called a page table that contains a 4-byte page table entry (PTE) for each page in virtual memory. During address translation, the virtual address is used to index the page table and find the corresponding PTE, which contains the starting physical address of the page. Virtual Address 31 0 Page Table PTE Physical Address 31 0 (A) Which bits from the virtual address are used to index into the page table? (The most significant bit is 31, the least significant bit is 0). Bits 31:12 (B) How large is the page table in bytes? 2 20 entries x 2 2 bytes/entry = 2 22 bytes = 4 megabytes (C) How does a translation lookaside buffer help during address translation? A TLB is a special-purpose cache that holds recently referenced page table entries. It accelerates address translation by eliminating the need to access main memory for every page table entry. Spring 2000 Page 4 of 9 Final Exam

5 5. Control dependences create numerous potential stall conditions in pipelined processors. One key problem is determining whether or not a branch condition will be true. Many processors use dynamic branch prediction, where a special hardware structure helps the pipeline control guess whether or not the branch was taken. If the guess is correct, there are no pipeline bubbles. If the guess is wrong, the pipeline must incur one or more bubbles while it flushes the incorrect instructions and starts over at the correct destination. Consider a pipeline that stalls for 8 cycles (i.e., 8 bubbles) whenever it mispredicts a branch. Also assume a workload that has one branch for every 6 instructions. (A) Consider Machine A which has NO branch predictor, so 50% of the branches are mispredicted. How many stall cycles per instruction (SCPI) are due to branch mispredictions? SCPI A = 1 branch/ 6 instrn * 1 mispredict/2 branches * 8 cycles/mispredict = 8 cycles / 12 instrn = 2/3 CPI (B) Consider Machine B which has a hardware dynamic branch predictor that correctly predicts the branch direction 95% of the time. How many stall cycles per instruction (SCPI) are due to branch mispredictions? SCPI B = 1 branch/ 6 instrn * 1 mispredict/20 branches * 8 cycles/mispredict = 8 cycles / 120 instrn = 1/15 CPI (C) If the overall CPI (i.e., including branch mispredicts) of Machine B is 1, what is the overall CPI of Machine A? CPI B = 1 = CPI perfect + SCPI B CPI perfect = 1 - SCPI B = 1-1/15 = 14/15 CPI A = CPI perfect + SCPI A = 14/15 + 2/3 = 24/14 = 1.6 CPI (D) What is the overall speedup achieved by adding the dynamic branch predictor to Machine A (to make Machine B)? Speedup = Time old / Time new Time/program = instructions/program * cycles/instruction * time/cycle Assuming instructions/program and time/cycle remain unchanged, Speedup = CPI old /CPI new = CPI A /CPI B = 1.6/1 = 1.6 Spring 2000 Page 5 of 9 Final Exam

6 6. (a) The MIPS kernel always returns from an exception by executing an rfe instruction followed by a jr instruction. Why would it be a bad idea to omit the rfe instruction from this return sequence? Omitting the rfe instruction would make the computer execute the user program while still in kernel mode. This would allow the user program to execute privileged instructions and have access to kernel resources such as devices. This would be a huge security hole. (b) The MIPS instructions that access the coprocessor 0 registers are called privileged instructions, because they can only be executed in kernel mode. Give one example of why would it be a bad idea to allow access to these instructions in user mode? The Status register is in coprocessor 0. Allowing a user program to write to Status would all it to switch to kernel while still executing the user program. This is the same problem as above. (c) Operating system kernels are very careful whenever a user program passes in a pointer (i.e., address). For example, consider a system call that reads a block of data from a disk and writes it to a buffer that the user specifies with a pointer. A real operating system will carefully check that this address really points to a buffer in the user s address space. Serious problems could occur if the pointer actually points to kernel space. (This is sometimes called a Trojan Horse, named for the Greek myth where the Athenians pretended to abandon their siege of Troy and left a large wooden horse to appease the Trojans. Unfortunately for Troy, it was actually full of Athenian soldiers who slipped out at night to open the gates to the returning Athenian armies). For the kernel used in this class, describe one way that a user could subvert the kernel if it did not carefully check pointers for the system call above. Suppose that the user passed in a pointer to the kernel s JumpTable so that the system call above overwrote the table with data from disk. The user could specify this data in such a way that the next exception caused the kernel to jump into the user program, rather than to the intended exception handler. Again, this allows the user to execute while in kernel mode, which breaches security. Spring 2000 Page 6 of 9 Final Exam

7 7. A MIPS processor has three peripherals (I/O devices) that share hardware interrupt 2. Each one has its own 32-bit status register, and the three of them are mapped to consecutive word addresses that start in 0xFFFE3000. Complete the following piece of TAL code, which identifies which one caused the exception (if any) and jumps to the corresponding handler. Handler addresses are stored in 0xFFFE4000 and consecutive addresses, in decreasing order. Peripherals are ready if their status register contains a 1. Otherwise, the status register content is 0. <initial exception handler code> _mfc0_ $t0,_$13_ andi $t1,$t0,_0x7c beq $t1,_$0_,k_check_int <Other code goes here> k_check_int: k_check_per: k_loop_per: k_cont: # check interrupts andi $t1,$t0, 0x0400 bne $t1,_$0_,k_check_per <Other code goes here> # check peripherials addi $t2,$0,_3_ lui $t1,0xfffe ori $t1,$t1,_0x3000 lui $t3,_0xfffe_ ori $t3,$t3,0x4000 lw $t0,_0($t1) beq $t0,_$0_,k_cont lw $t0, _8($3) jr $t0 addi _$t3_, $t3_, _ 4_ addi _$t1_, $t1_, 4 addi $t2,$t2, 1 bne $t2_,$0,k_loop_per <Other code goes here> Spring 2000 Page 7 of 9 Final Exam

8 8. Pipelined computers may have to stall when one instruction uses a value that is generated by another. (A) Indicate the (true) data dependences in the following MAL code sequence. Circle the affected registers and connect them with a line. add $t0, $t1, $t2 lw $t3, 4($t1) sub $t2, $t0, $t3 Note that the dependence exists between the add and the OR even though it may not cause a stall in a pipeline. or $t2, $t2, $t0 sw $t1, 8($t3) (B) Consider a pipeline with the following six stages. Instruction Fetch (IF) Instruction Decode (ID) Register Read (RR) Execution (EX) Memory Load/Store (MEM) Register Write (WB) In this pipeline, registers may be read and written in the same cycle. For example, if register $s0 is written in cycle 5, a dependent instruction may read register $s0 in cycle 5. Draw a pipeline diagram that shows the code above executing on this pipeline. Be sure to indicate where the bubbles occur. Instr add IF ID RR EX MA WB lw IF ID RR EX MA WB sub IF ID stall stall RR EX MA WB or IF ID stall stall stall stall RR EX MA WB sw IF ID stall stall stall stall RR EX MA WB Spring 2000 Page 8 of 9 Final Exam

9 9. Answer the following short questions: A) Integer addition is both commutative and associative. Floating point addition is commutative but NOT associative. Why not? Give an example. Floating point addition is not associative because of the limited range and precision. For example, (1.0 x x ) x 2 0 <> 1.0 x (-1.0 x x 2 0 ) 1.0 x 2 0 <> 0 B) Describe in one or two short sentences why a vector processor (e.g., the Cray 1) can perform some operations in far fewer instructions than can a MIPS processor. A vector processors like the Cray-1 has registers that hold vectors of 64 values and has instructions that operate on vectors. Thus the Cray-1 can issue a single instruction that multiplies two vectors together, while a MIPS processor must issue 64 multiplies. C) What is meant when a processor is called superscalar? A processor is called superscalar if the hardware tries to execute more than one scalar instruction per cycle. Unlike a VLIW or vector processor, there is nothing in the instruction set that helps the hardware to know which operations can be executed at the same time. 10.The kernel used in the homework assignments includes the following code that is executed for some exceptions, but not others: _k_increturn: mfc0 $k1, $14 add $k1, $k1, 4 mtc0 $k1, $14 Explain the purpose of this code. Which exceptions execute it? Which do not? Why? This code increments the value stored in the Exception PC (EPC) register in coprocessor 0. It is used by those synchronous exceptions that want to skip over the instruction it points to. The main example of this is syscall, because we do not want to re-execute the syscall instruction again after returning from the kernel (otherwise we would have an infinite loop). There are a few other examples of this, such as when the kernel emulates the behavior of the instruction that trapped. Spring 2000 Page 9 of 9 Final Exam