Spectre-Compatible Process Design Kits

Transcription

1 Spectre-Compatible Process Design Kits August 2005

2 Notice The information contained in this document is subject to change without notice. Agilent Technologies makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Agilent Technologies shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material. Warranty A copy of the specific warranty terms that apply to this software product is available upon request from your Agilent Technologies representative. Restricted Rights Legend Use, duplication or disclosure by the U. S. Government is subject to restrictions as set forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS for DoD agencies, and subparagraphs (c) (1) and (c) (2) of the Commercial Computer Software Restricted Rights clause at FAR for other agencies. Agilent Technologies, Inc Page Mill Road, Palo Alto, CA U.S.A. Acknowledgments Mentor Graphics is a trademark of Mentor Graphics Corporation in the U.S. and other countries. Microsoft, Windows, MS Windows, Windows NT, and MS-DOS are U.S. registered trademarks of Microsoft Corporation. Pentium is a U.S. registered trademark of Intel Corporation. PostScript and Acrobat are trademarks of Adobe Systems Incorporated. UNIX is a registered trademark of the Open Group. Java is a U.S. trademark of Sun Microsystems, Inc. SystemC is a registered trademark of Open SystemC Initiative, Inc. in the United States and other countries and is used with permission. ii

3 Contents 1 Introduction Understanding Spectre-Compatible PDKs Intended Audience Using Spectre-Compatible PDKs in RFDE The ADSsim and Spectre Simulators The ADSsim Simulator The Spectre Simulator Multi-Language Simulator Front End Supported Design Flows The PDK Development Flow Support Model Documentation References Administrative Tasks Setting Up the Cadence Environment Spectre-Compatibility File Descriptions Viewing Effective RFDE Library Compatibility for Library Cells Setting Up Library Cell Compatibility for RFDE Testing Library Cells for RFDE Spectre Compatibility Setting Up Model Includes and Include Path Setting Up Cell Model Parameters Setting Up Switch and Stop View lists Compatible Devices and Models Internal Mapping Supported Devices and Models Sources Supported Sources Behavioral Source (bsource) Cadence Provided Libraries ahdllib analoglib basic rflib Compatible Features Expressions Operators Algebraic and Trigonometric Functions Built-in Constants Subcircuits iii

4 Nested Subcircuits Inline Subcircuits Subcircuit Parameters Process Variation and Mismatch The statistics Statement Structural if-else Sectional Includes Special Character Support Verilog-A Support (ahdl_include) Using Design Variables Managing Unsupported Features Identifying Unsupported Features Unsupported Parameters on Supported Devices Generating Debugging Output Incompatible Features Spectre Analyses Spectre Control Statements The paramtest Component Model Scale Factor (scalem) Missing Devices and Models Spectre High-Level Description Language (HDL) Cadence Compiled-Model Interface (CMI) Spectre Encryption SPICE Format Compatibility The RFDE Netlister Instance Netlisting Basic Spectre Formatting Instance Name Mapping Node Name Mapping Adding Instance Pins for pinmapping Subcircuit Netlisting Scoping Rules Verilog-A Netlisting Include Files Default Switch and Stop View Lists, Hierarchy Editor Error Messages Alias Warning Messages Backward Compatibility Spectre-Compatible Process Design Kit Verification Setting Up and Running a Simulation iv

5 Using the Results Browser Annotating DC Results Annotating DC Voltages Annotating DC Currents Displaying DC Operating Points Index v

6 vi

7 Chapter 1: Introduction This documentation provides information on how to be successful using a Spectre Process Design Kit (PDK) in the RF Design Environment (RFDE). This RFDE capability is referred to as Spectre-Compatible PDK. In general, RFDE now supports Spectre simulator syntax allowing simulations in both RFDE and Spectre using the same PDK. The documentation assumes that you are familiar with the development of process design kits and that you have some familiarity with RFDE and Spectre simulation in the Cadence Design Framework II (DFII) environment. The goal of this documentation is to provide information on: What steps to take to accomplish your tasks using the software What are the likely design repercussions of the options available at each step What are the likely outcomes with the current limitations of the tools The information in this first chapter describes an overview of a single process design kit for RFDE and Spectre. Understanding Spectre-Compatible PDKs Process Design Kits or PDKs are a complete set of the basic building blocks that enable custom IC design. In addition to the numerous baseline PDKs that are available from various vendors, custom PDKs can be developed to suit your own specific needs. PDKs are essential in today s fast-paced electronic design environment in order to meet aggressive design and development schedules. Agilent EEsof EDA is now introducing a Spectre-Compatible solution for RF Design Environment (RFDE) users. Agilent Technologies has included a number of new circuit features and devices available in RFDE that are Spectre-Compatible. When developing a new PDK, or a foundry library, you can now set up your PDK or library to be Spectre-Compatible in RFDE and take advantage of both the ADSsim and Spectre simulators. These new Spectre-Compatible features are readily available and easy to use; however, it is important to recognize that there are certain limitations due to differences between the two simulator technologies. This documentation is intended to help you understand specifically what is supported. The documentation can also help to identify areas of concern and how to deal with these particular situations. Understanding Spectre-Compatible PDKs 1-1

8 Introduction Intended Audience The audience intended for this documentation consists of a variety of people involved in process design kit creation, verification, distribution and use. However, the primary audience for this documentation are process design kit developers and CAD administrators. Advanced PDK users who need to understand the details of Spectre compatibility may also benefit from understanding this information. Using Spectre-Compatible PDKs in RFDE The complexity of model file translation has been greatly reduced, and in some cases, completely eliminated in this release of RF Design Environment. Model file translation is only required to overcome issues where a feature in Spectre is not supported in RFDE. Model file verification is also simplified. A single netlist can be reused to verify multiple simulators, and the netlist does not have to be generated by the Cadence environment. Library setup is also eliminated or greatly reduced. Library setup is only required in cases where a feature in Spectre is unsupported and requires a work-around, or when a specific RFDE feature that does not exist in Spectre is desired. Programming has also been reduced in the local CAD environment setup. Setups related to switch views, stop views, and model files can now be automated in the Cadence Initialization (.cdsinit) or Library Initialization (libinit.il) file. The setup that works for Spectre now also works for RFDE. Depending on the components used, there are also no requirements to use the RFDE delivered Analog Library (analoglib). The ADSsim and Spectre Simulators Circuit designers do not typically care if Process Design Kits are compatible; they simply expect PDKs to function with either the ADSsim or Spectre simulator. If a PDK developed for Spectre does not function in RF Design Environment, this can present a significant barrier for the RFDE user. The goal of this document is to help CAD Managers and PDK designers become successful in configuring RFDE for use with Spectre-Compatible PDKs. 1-2 Intended Audience

9 The ADSsim Simulator Agilent Technologies provides two distinct products that use a common simulation technology called the ADS Analog/RF Simulator (ADSsim). RF Design Environment, using ADSsim, is available in Cadence Design Framework II. A separate, stand-alone product, Advanced Design System, also uses ADSsim. RF Design Environment enables you to simulate circuits and RF systems designed for specific objectives, such as large-scale RF/mixed signal IC design. RFDE makes available, in the Cadence environment, important frequency-domain and mixed-domain simulation technologies optimization and statistical design tools additional device, system, and behavioral models powerful data display post processing The Spectre Simulator The Spectre simulator provided by Cadence Design Systems is used to simulate analog and digital circuits at the differential equation level. The simulator uses algorithms that offer increased simulation speed and greatly improved convergence characteristics over SPICE. In addition to the basic capabilities, the Spectre circuit simulator provides additional capabilities over SPICE. SpectreHDL (Spectre High-Level Description Language) and Verilog-A use functional description text files, or modules, to model the behavior of electrical circuits and other systems. The Virtuoso Spectre RF Simulation option includes several analyses that support the efficient calculation of the operating point, transfer function, noise, and distortion of common RF and communication circuits, such as mixers, oscillators, sample holds, and switched-capacitor filters. Multi-Language Simulator Front End RF Design Environment includes a multi-language simulator front end as part of the Spectre-Compatibility solution. The front end recognizes the Spectre simulator lang statement with options set to either spectre or ads. For example, simulator lang=spectre simulator lang=ads The ADSsim and Spectre Simulators 1-3

10 Introduction This ability to specify a specific language in the netlist is critical to how RFDE s Spectre parser functions. Once the system selects the spectre or ads simulator language, it can read in the netlist written for spectre or ads syntax, parse the netlist into its various parts, and make the information available for analysis. Supported Design Flows Agilent Technologies provides two recognized design flows that can take advantage of the Spectre-Compatible solution: RF Design Environment RFIC Dynamic Link An engineer using the RFIC Dynamic Link flow creates a design in the Cadence Virtuoso Schematic Capture. The design is then dynamically linked via inter-process communication (IPC) for simulation in Advanced Design System. This manual is generally focused on the RF Design Environment design flow. For more information, refer to the Advanced Design System RFIC Dynamic Link and/or the Cadence Library Integration documentation. All Advanced Design System and RF Design Environment documentation can be accessed from the Agilent EEsof EDA Web site at: The PDK Development Flow The general methodology used for developing process design kits is shown in Figure 1-1. The process begins with the foundry. A manufacturing process is used to generate an integrated circuit (IC) design. The Cadence PDK encapsulates the data for the manufacturing process into a format that will enable a group of designers to create an IC using the specified manufacturing process. This includes libraries that contain layout definitions and verification rule files that can verify that a layout generated using the library can be maintained. Secondary to the layout data is schematic data that can be used to create logical representations of the design. Because of the complexity of modern designs, as well as the cost of manufacturing, it is unrealistic to assume that a designer would create a design directly in layout. 1-4 Supported Design Flows

11 PDK Development Flow Foundry CAD Services Foundry CAD Group Foundry PDK Designers Test data is fed back to improve Foundry and/or internal models Foundry Manufacturing and Testing Test data is fed back to the designer so the design can be corrected or improved Final IC Test Packaging and Module Integration Foundry Process Package Module Test Customers receive the finished product PDK Customers Customers provide specifications, complaints, and/or demands for improved products Figure 1-1. High Level Process Design Kit Development Flow Supported Design Flows 1-5

12 Introduction Support Model If you are creating a process design kit that requires some Spectre capability that is not included in this document or includes a feature that is not supported by Agilent Technologies, the Agilent Technologies Spectre-Compatible Process Design Kit team would like to understand your situation. There may be a solution that has not yet been documented, or Agilent Technologies may choose to add it based on a demonstrated need and mutual, widespread benefit. The standard RF Design Environment user interface does not recognize Spectre netlists. Spectre-Compatibility mode is turned off by default. This means that your designs should be compatible with previous releases. If a problem does occur when using Spectre-Compatibility with a design from a previous release, turn the Spectre-Compatible features off in RFDE to troubleshoot the problem. For more information, contact your Agilent Technologies sales representative or technical support with a request to submit a suggestion to the Spectre-Compatible Process Design Kit team at the factory. Documentation References This section includes important references to both Agilent Technologies and Cadence Design Systems documentation. The primary Agilent Technologies documents that are referenced in this documentation include: UNIX and Linux Installation Using Circuit Simulators analoglib Components Introduction to Circuit Components Nonlinear Devices Sources Cadence Library Integration RF Design Environment Examples 1-6 Support Model

13 The primary Cadence Design Systems documents that are referenced in this documentation include: Cadence Design Framework II Configuration Guide Virtuoso Analog Design Environment User Guide Virtuoso Spectre Circuit Simulator User Guide Virtuoso Spectre Circuit Simulator Reference Virtuoso Spectre Circuit Simulator Components and Device Models Manual Analog Library Reference Guide Where ever possible, product version numbers have been included in this document to help identify the correct Cadence documentation. For more information on Cadence documentation, log into your Cadence SourceLink account from the Cadence Design Systems Web site at: Documentation References 1-7

14 Introduction 1-8 Documentation References

15 Chapter 2: Administrative Tasks This chapter describes the administrative tasks that can help a CAD Manager or PDK Designer improve the efficiency of their tasks. The chapter also includes information on the Spectre-Compatibility tools used for setting up and testing library cells. Setting Up the Cadence Environment This section describes the different files required for RFDE and the Spectre-Compatibility option to function. With the exception of the RFDE Spectre-Compatibility Configuration file, all other required files are standard Cadence setup files. Once you have configured your Cadence environment to operate with Spectre and RFDE, you can configure your RFDE Spectre-Compatibility Configuration file if not already done. For more information, refer to the RFDE Spectre-Compatibility Configuration File on page 2-3. Spectre-Compatibility File Descriptions This section includes information on files required for Spectre-Compatibility. In general, the information below includes the file names, locations, purpose, and general contents included in each of the files required for Spectre-Compatibility. References to Cadence documentation are included where appropriate. For detailed information on RF Design Environment configuration, refer to your UNIX and Linux Installation documentation. For general information on Cadence configuration, refer to the Cadence Design Framework II Configuration Guide, Product Version 5.0. Cadence Initialization File The Cadence initialization file (.cdsinit) is loaded when you start a Cadence session. The.cdsinit file is a SKILL file that enables you to add in commands to do additional customization to the Cadence environment that cannot be easily accomplished by simply changing something in your.cdsenv file. You can load other files in addition to having SKILL commands in your.cdsinit file. The Cadence initialization file (.cdsinit) is located under: <Cadence Installation Dir>/tools/dfII/local/ Setting Up the Cadence Environment 2-1

16 Administrative Tasks For more information on the.cdsinit file, refer to Creating a.cdsinit File and Modifying the.cdsinit File in the Cadence Design Framework II Configuration Guide, Product Version 5.0. Cadence Environment Variable File Cadence environment variable files (.cdsenv) contain information for one or more specific tools that have been configured to work in the Cadence environment. Each tool has its own specific tool file, located under: <Cadence Installation Dir>/tools/dfII/etc/tools or located in a directory specified in a setup.loc file if you are using CDS_LOAD_ENV and have set it to CSF. For more information on the setup.loc file, refer to Chapter 3: Cadence Setup Search File: setup.loc in the Cadence Application Infrastructure User Guide, Product Version 3.4. The Cadence environment variable file for ADSsim is located under: <Cadence Installation Dir>/tools/dfII/etc/tools/ADSsim/ For more information on the.cdsenv file, refer to Customizing the Environment in Chapter 2 of the Cadence User Interface SKILL Functions Reference, Product Version 5.0. Cadence Library Definition File The Cadence Library Definition file (cds.lib) is located under your Cadence installation directory. This is your library setup file. For more information on the cds.lib file, refer to Chapter 5: Cadence Library Definition File:cds.lib in the Cadence Application Infrastructure User Guide, Product Version 3.4. The analoglib library distributed with Cadence tools is partially RFDE compatible; however, the analoglib distributed with RFDE is preferred due to greater component coverage. The RFDE version of analoglib is located under: $HPEESOF_DIR/cdslibs The location is specifically keyed off of the Cadence version, which is obtained in the RFDE initialization file, ads.ini. To keep things simple, an include file, rfde.lib, is provided which defines the RFDE analoglib, as well as the adslib. It is 2-2 Setting Up the Cadence Environment

17 recommended that both of these, as well as the RFDE version of the Cadence basic library, be added to your cds.lib file, by including the rfde.lib file. RFDE Spectre-Compatibility Configuration File The RF Design Environment Spectre-Compatibility Configuration file (rfdespectrecompatibility.cfg) enables you to specify whether certain libraries and/or components will work in RFDE Spectre-Compatibility mode. A cell that is marked as incompatible will only netlist in ads mode. A cell that is marked as compatible will netlist in spectre mode assuming that it does not evaluate to having an ads stop view. For more information on stop views, refer to Setting Up Switch and Stop View lists on page If a library is specified, all components in the library will use that setting, unless there is a specific cell setting that will override the library setting. Format <libraryname> <cellname> TRUE FALSE <- Set cell compatibility <libraryname> TRUE FALSE <- Set library compatibility If there are duplicates, only the first setting will be used. The rfdespectrecompatibility.cfg file is located under the following directories: <libraryname>/ $HPEESOF_DIR/custom/config/ $HOME/hpeesof/config/ These files contain compatibility setting files. The directory locations above are shown from the highest priority to the lowest priority as described in Table 2-1. Table 2-1. File Priority for rfdespectrecompatibility.cfg Priority Setting Path Comments 1 LIBRARY <libraryname>/ Overrides SITE & USER settings 2 SITE $HPEESOF_DIR/custom/config/ Overrides USER setting 3 USER $HOME/hpeesof/config/ Lowest priority Setting Up the Cadence Environment 2-3

18 Administrative Tasks Note You can add a setting to the file in your home directory and it will be recognized; however, if it is the same setting as in the library or site directory, it will be overridden. An additional option is to use the ADSsim.envOpts environment variable. This variable would take the absolute lowest priority below this options listed in Table 2-1. This environment variable can be set in ~/.cdsenv or.cdsenv: ADSsim.envOpts spectrecompatibility boolean nil Or, the global file at $CDSHOME/tools/dfII/etc/tools/ADSsim/.cdsenv can be set for all users: ADSsim.envOpts spectrecompatibility boolean nil nil Setting the value to t (true) makes the default behavior for cells to be Spectre-Compatible, no rfdespectrecompatibility.cfg file is required to set the library or individual components. An additional environment variable that can be used for selecting output format is called translateresults. Setting the translateresults environment variable to t (true) will force parameter storage format (PSF) output for all simulations unless you de-activate the Translate Results to PSF option in the Data Display Options form. ADSsim.envOpts translateresults boolean nil t You can access the Data Display Options form by choosing Results > Data Display Options in the Analog Design Environment window. Viewing Effective RFDE Library Compatibility for Library Cells You can use the View Effective RFDE Compatibility for Library Cells form in RF Design Environment to identify which cells can or cannot work with RFDE. RFDE can detect that library components are RFDE-compatible or not. If you have specified that a component is not Spectre-Compatible with RFDE, the software will look for an ads simulation component in the siminfo. If you want to force cells to be allowed in a simulation, you have that option as well. Assuming you have write access to a library, you can use the Setup Library Cell 2-4 Viewing Effective RFDE Library Compatibility for Library Cells

19 Compatibility for RFDE form to change the library defaults to allow Spectre compatibility. To preview a specific library and review which cells can be simulated in RF Design Environment, launch the Cadence software with RFDE. From the Cadence Command Interpreter Window (CIW), 1. Choose Tools > Agilent RFDE > RFDE Library Compatibility. The View Effective RFDE Compatibility for Library Cells form appears. Note The View Effective RFDE Compatibility for Library Cells form can also be accessed from the Analog Design Environment (ADE) window when the ADSsim simulator is selected. To access the form from ADE, choose Tools > RFDE Library Compatibility. The options for the View Effective RFDE Compatibility for Library Cells form are described in Table 2-2 below. 2. Select a library from the Library drop-down list. The fields in the form will automatically populate with the library contents. Individual cells are separated into two categories, Cells that work with RFDE and Cells that do not work with RFDE. 3. Click a cell of interest in one of the two categories. Notice that information about the selected cell is displayed in the RFDE Compatibility Setting Status field at the bottom of the form. Viewing Effective RFDE Library Compatibility for Library Cells 2-5

20 Administrative Tasks Table 2-2. The View Effective RFDE Compatibility for Library Cells Form Option Library Cells that work with RFDE Cells that do not work with RFDE Description Use the drop-down list to select the appropriate library. This field lists the RFDE-Compatible cells within the specified library. Click a library cell to view the effective compatibility displayed in the RFDE Compatibility Setting Status field. While some cells are Spectre-Compatible and will netlist with RFDE, they may still need to be setup for a simulation. This field lists the cells within the specified library that are incompatible with RFDE. Click a library cell to view information about why the cell is incompatible. The information will be displayed in the RFDE Compatibility Setting Status field. 2-6 Viewing Effective RFDE Library Compatibility for Library Cells

21 Table 2-2. The View Effective RFDE Compatibility for Library Cells Form Option RFDE Compatibility Setting Status Edit Settings Description This field displays information about a selected cell. Click the Edit Settings button to setup library cells for RFDE-Compatibility. For more information, refer to Setting Up Library Cell Compatibility for RFDE on page 2-7. Setting Up Library Cell Compatibility for RFDE To access the Setup Library Cell Compatibility for RFDE form from the Cadence Command Interpreter Window (CIW), 1. Choose Tools > Agilent RFDE > RFDE Library Compatibility. The View Effective RFDE Compatibility for Library Cells form appears. Note The View Effective RFDE Compatibility for Library Cells form can also be accessed from the Analog Design Environment (ADE) window when the ADSsim simulator is selected. To access the form from ADE, choose Tools > RFDE Library Compatibility. 2. Click Edit Settings in the View Effective RFDE Compatibility for Library Cells form. The Setup Library Cell Compatibility for RFDE form appears. Viewing Effective RFDE Library Compatibility for Library Cells 2-7

22 Administrative Tasks If you make a change to your library setup and attempt to close the form without saving your changes, the Save form appears asking if you want to save your changes. Save your settings to ensure your changes are not lost. Note If you are not the owner of a particular setting, such as a site file, you may not have permissions to change the value of a particular setting. Work with your CAD manager or site administrator to make the appropriate changes. Refer to Table 2-3 for information on using the Setup Library Cell Compatibility for RFDE form. 2-8 Viewing Effective RFDE Library Compatibility for Library Cells

23 Table 2-3. The Setup Library Cell Compatibility for RFDE Form Option Library Show Settings In Library default is to allow Spectre Simulation Information use with RFDE Cells that work with RFDE Cells that do not work with RFDE Description Use the drop-down list to select the appropriate library. Select a radio button to User File, Site File, Library File. Use the drop-down list to set this option to Yes or No. When this option is set to Yes, cells that are specified as Spectre-Compatible will use the Spectre-Compatible features available in RF Design Environment. When this option is set to No, standard RFDE mode will be used. The default value is No. This field lists the RFDE-Compatible cells within the specified library. This field lists the RFDE-Incompatible cells within the specified library. <-- Use this button to move an entry from the Cells that do not work with RFDE field into the Cells that work with RFDE field. --> Use this button to move an entry from the Cells that work with RFDE field into the Cells that do not work with RFDE field. ADD Use the ADD button to add an entry. DEL Use the DEL button to delete an entry. > Cells that are preceded by the > symbol have a compatibility setting in a higher priority file and cannot be changed. + Cells that are preceded by the + symbol have a cell setting that is inherited from the environment or library default. * Cells that are preceded by the * symbol do not have a Spectre siminfo or Spectre stop view and do not need compatibility setup. Testing Library Cells for RFDE Spectre Compatibility This section describes how to test a specific library for Spectre-Compatibility from within the Cadence environment. The tools available in RF Design Environment enable you to test whether a library cell will function in RFDE if it uses Spectre simulation setups. You can set up your own library or cell, or use default settings to control if Spectre-Compatibility should be used or not. You can also save these settings in your configuration file for future use. Settings are saved by default to your configuration file under: $HOME/hpeesof/config Testing Library Cells for RFDE Spectre Compatibility 2-9

24 Administrative Tasks Note If you are not the owner of a particular setting, such as a site file, you may not have permissions to change the value of a particular setting. Work with your CAD manager or site administrator to make the appropriate changes. To access the Test Library Cells for RFDE Spectre Compatibility tool, launch Cadence with RFDE. The tool will set up compatibility files by checking if a cell with a Spectre simulation setup will work with RFDE. From the Cadence Command Interpreter Window (CIW), 1. Choose Tools > Agilent RFDE > Test and Setup RFDE Spectre Compatibility. The Test Library Cells for RFDE Spectre Compatibility form appears. 2. Use the Library drop-down list to select the appropriate library. The Cells that have a spectre simulation setup field will be populated with the cells in the library that include a spectre stop view. 3. Click a cell that you want to test and then click the right arrow (-->) to move the cell into the Cells to test for RFDE spectre compatibility field Testing Library Cells for RFDE Spectre Compatibility

25 4. Click Model File Setup. The Setup Model Includes and Include Path form appears. For more information on model file setup, refer to Setting Up Model Includes and Include Path on page Click Cell Parameter Setup. The Setup Cell Model Parameter form appears. For more information on cell parameter setup, refer to Setting Up Cell Model Parameters on page Click Switch/Stop View Setup. Testing Library Cells for RFDE Spectre Compatibility 2-11

26 Administrative Tasks The Setup switch and stop view lists form appears. For more information on switch view and stop view list setup, refer to Setting Up Switch and Stop View lists on page Table 2-4. The Test Library Cells for RFDE Spectre Compatibility Form Option Library Test Directory Test Library Name Cells that have a spectre simulation setup Cells to test for RFDE spectre compatibility Description Use the drop-down list to select the appropriate library. Enter the Test Directory to use in the field provided. This is the directory where test results are stored. The default test directory is under your startup directory. A default name will be generated in the Test Library Name field. The default name simply appends _rfdecompatibilitytests to the selected library name. You can change this name as desired. This field lists all cells that include a Spectre simulation setup. You can click the right arrow button (-->) to move a selected cell into the Cells to test for RFDE spectre compatibility list. This field lists all cells that are ready to test for RFDE Spectre-Compatibility. You can click the left arrow button (<--) to move a selected cell back into the Cells that have a spectre simulation setup list. --> Use this button to move an entry from the Cells that have a spectre simulation setup field into the Cells to test for RFDE spectre compatibility field. <-- Use this button to move an entry from the Cells to test for RFDE spectre compatibility field into the Cells that have a spectre simulation setup field. Model File Setup Click the Model File Setup button to launch the Setup Model Includes and Include Path form. Functionality is generally the same as Cadence; however, this form allows you to set a Model include path inside the form. For more information, refer to Setting Up Model Includes and Include Path on page Cell Parameter Setup Click the Cell Parameter Setup button to launch the Setup Cell Model Parameter form. This form enables you to set model parameter cells that require a model parameter to be set. If no model parameters are required, a warning message will be displayed in the CIW. For more information, refer to Setting Up Cell Model Parameters on page Switch/Stop View Setup Click the Switch/Stop View Setup button to launch the Setup switch and stop view lists form. The switch view and stop view functionality is the same as in the Cadence Environment Options form. For more information, refer to Setting Up Switch and Stop View lists on page Testing Library Cells for RFDE Spectre Compatibility

27 Table 2-4. The Test Library Cells for RFDE Spectre Compatibility Form Option Create Test Benches Description Click the Create Test Benches button to create a test bench from the Cells to test for RFDE Spectre-Compatibility. A test bench enables you to configure a library cell so that you can perform a simple simulation. Test benches are created and stored under: $HOME/simulation/<libraryName>_<cellName>_test/ Create Test Benches And Run Simulations Click the Create Test Benches And Run Simulations button to create a test bench from the Cells to test for RFDE Spectre-Compatibility and launch a simulation. A pass/fail text file is displayed after the simulation is complete. This file lists all Cells that successfully simulated along with the Cells that failed to simulate. Simulation results are stored under: $HOME/simulation/<libraryName>_<cellName>_test/ Run Simulations Click this button to run a simulation on the Cells to test for RFDE spectre compatibility. A pass/fail text file is displayed after the simulation is complete. This file lists all Cells that successfully simulated along with the Cells that failed to simulate. Simulation results are stored under: $HOME/simulation/<libraryName>_<cellName>_test/ Setting Up Model Includes and Include Path In general, the functionality in the Setup Model Includes and Include Path form is the same as provided in the Cadence; however, this form enables you to set a Model include path inside the form. To access the Setup Model Includes and Include Path tool, 1. Access the Test and Setup RFDE Spectre Compatibility form as described in Testing Library Cells for RFDE Spectre Compatibility on page Click a cell that you want to include. Note that the Model File Setup button is activated. 3. Click the Model File Setup button. The Setup Model Includes and Include Path form appears. Testing Library Cells for RFDE Spectre Compatibility 2-13

28 Administrative Tasks Refer to Table 2-5 for information on using the Setup Model Includes and Include Path form. Table 2-5. The Setup Model Includes and Include Path Form Option #Disable Model Library Setup Section Enable Disable Up Down Model Library File Description Lists all of the model files to be included. Enter the model file name and optional section into the Model Library File and Section (opt.) fields described below. Lists all optionally included sections that were entered in the Section (opt.) field below. Enables the highlighted/selected model files in the Model Library Setup field for a particular run. If any of the highlighted/selected model files in the Model Library Setup field are prefixed with a comment character (#), clicking the Enable button removes the # sign. De-selects the highlighted model files. Once the Disable button is clicked, the highlighted/selected model files in the Model Library Setup field are disabled and a comment character (#) is added before the model path. Move a highlighted/selected model files in the Model Library Setup field up in the list. This button is disabled if more than one model file is highlighted/selected in the Model Library Setup field. If the first item is highlighted/selected in the Model Library Setup field, the Down button is activated. Move a highlighted/selected model files in the Model Library Setup field down in the list. This button is disabled if more than one model file is highlighted/selected in the Model Library Setup field. If the last item is highlighted/selected in the Model Library Setup field, the Up button is activated. Enter the model library file name in this field Testing Library Cells for RFDE Spectre Compatibility

29 Table 2-5. The Setup Model Includes and Include Path Form Option Section (opt.) Add Delete Change Load from Spectre State Include Path Description Enter an optional section to include with the model library file in this field. Adds the value of the Model Library File field (and Section (opt.) field) to the end of the list of files in the Model Library Setup field. If a file is selected in the Model Library File field, the Model Library File (and Section (opt.) field) entry is added above the highlighted item. Removes any highlighted items that are selected in the Model Library Setup field. An item in the Model Library Setup field must be selected in order to remove the file. Replaces the selected entry with the value of the Model Library File field (and Section (opt.) field). Click this button to load a model include and the include path from a previously saved state. For more information, refer to Loading Model Includes and Include Path from a State on page Enter the directory or list of directories for the include path. The paths are checked in sequence. Note The Setup Model Includes and Include Path form operation in RFDE is very similar to the Cadence Model Library Setup form. For more information, refer to Model Setup for Direct Simulation in Chapter 2 of the Cadence Virtuoso Analog Design Environment User Guide, Product Version Loading Model Includes and Include Path from a State Cadence allows certain portions of a library (e.g. model setup) to be loaded without forcing the entire state to be reloaded. The simulation settings are saved into individual files under the state directory. All or part of a state can be loaded, from any cell or tool in the state directory that is being pointed at, for any cell that is open in the Analog Design Environment. Note that the settings are based on the tool environment value names, so if a tool does not have a particular environment setting, those values would be ignored when a state file is loaded. The Cadence artist state directory structure is shown in Figure 2-1. Testing Library Cells for RFDE Spectre Compatibility 2-15

30 Administrative Tasks <artist state directory> <library 1> <library 2> <cell 1> <cell 2> <tool 1> <tool 2> <state 1> <state 2> <file 1> <file 2> /tool 1 Figure 2-1. Cadence Artist State Directory Structure To load a model include and the include path from a previously saved state, 1. Access the Setup Model Includes and Include Path form as described in Testing Library Cells for RFDE Spectre Compatibility on page Click the Load from Spectre State button. The Load Model Includes and Include Path from a state form appears. Refer to Table 2-6 for information on using the Load Model Includes and Include Path from a state form Testing Library Cells for RFDE Spectre Compatibility

31 Table 2-6. The Load Model Includes and Include Path from a state Form Option State Save Directory Library Cell State Name Description Enter the path for the state save directory. The default path for saved states is ~/.artist_states. The state directory can also be changed by choosing the Session > Options menu item to access the Editing Session Options form in the Analog Design Environment window. Use the drop-down list to select the name of the library whose state was saved. Use the drop-down list to select the name of the cell whose state was saved. This does not need to match the name of the cell you are currently simulating. Enter the file name specified when the state was saved. 3. Click OK to enter the values or Cancel to abort the entry. If you click OK, the values are uploaded into the Setup Model Includes and Include Path form. Setting Up Cell Model Parameters The Setup Cell Model Parameters form enables you to set cell model parameters that are required. If no cell model parameters are required, a warning message is displayed in the Cadence Command Interpreter Window (CIW). To access the Setup Cell Model Parameter form, 1. Access the Test and Setup RFDE Spectre Compatibility form as described in Testing Library Cells for RFDE Spectre Compatibility on page Click a cell that you want to test and then click the right arrow (-->) to move the cell into the Cells to test for RFDE spectre compatibility field. 3. Click the Cell Parameter Setup button in the Test Library Cells for RFDE Spectre Compatibility form. The Setup Cell Model Parameter form appears. Testing Library Cells for RFDE Spectre Compatibility 2-17

32 Administrative Tasks 4. Click the appropriate cell in the Cells that require model parameter setup field and enter a list of models in the Model List field. 5. Click OK to enter the changes and dismiss the form or Cancel to abort the changes. Setting Up Switch and Stop View lists The switch view and stop view functionality operates the same as it does in the Cadence environment options. To access the Setup switch and stop view lists tool, 1. Access the Test and Setup RFDE Spectre Compatibility form as described in Testing Library Cells for RFDE Spectre Compatibility on page Click a cell that you want to include. Note that the Switch/Stop View Setup button is activated. 3. Click the Switch/Stop View Setup button. The Setup switch and stop view lists form appears Testing Library Cells for RFDE Spectre Compatibility

33 Refer to Table 2-7 for general information on using the Setup switch and stop view lists form. Table 2-7. The Setup switch and stop view lists Form Option Switch View List Stop View List Description This field includes a list of the views that the software switches into when searching for design variables. The software is searched through the hierarchical views in the order shown in the list. This list must contain the name of the simulator(s). This is a list of views that identify the stopping view to be netlisted. This list does not require a particular sequence. Testing Library Cells for RFDE Spectre Compatibility 2-19

34 Administrative Tasks 2-20 Testing Library Cells for RFDE Spectre Compatibility

35 Chapter 3: Compatible Devices and Models This chapter provides information on the devices and models that are supported for use in Spectre-Compatible PDKs. Device/model detail is described at great length in other Agilent and/or Cadence documentation; therefore, the chapter will provide references to additional information in the corresponding documentation where appropriate. Note Some Spectre parameters may not be listed for a particular device or model. All Spectre parameters that are not listed should be considered unsupported parameters. You can also find Spectre instance and model parameter information for each component using the Spectre online help (spectre -h) feature. For more information on this feature, refer to your Cadence documentation set. Internal Mapping When RFDE encounters a Spectre netlist, devices and models are mapped to the equivalent ADS Analog/RF simulator (ADSsim) devices and models. In general, device and model parameters in the ADSsim use initial caps for parameters. Parameters in ADSsim that differ only by the initial cap are mapped directly to the corresponding parameter in Spectre. For example, r in Spectre maps to R in ADSsim. This is helpful to understand when troubleshooting problems in the netlist. Error and warning messages may refer to parameters that are mapped to an equivalent parameter in a different simulator language. When there is a difference in parameter default values between Spectre and ADSsim, the Spectre default value is used. The multiplicity factor (m) in Spectre is mapped to _M in ADSsim. This applies to all device and subcircuit instances. Table 3-1 below displays a list of supported Spectre device and models and their ADSsim equivalents. For information on device, model, and DC operating point parameter mapping, refer to Supported Devices and Models on page 3-4. Internal Mapping 3-1

36 Compatible Devices and Models Table 3-1. Supported Devices and Models Spectre Instance ADSsim Instance Spectre Model ADSsim Model resistor R resistor R_Model capacitor C capacitor C_Model inductor L inductor L_Model mutual_inductor Mutual diode Diode diode Diode (Diode_Model) juncap Juncap (JUNCAP) juncap Juncap (Juncap_Model) bjt bht bjt503 bjt504 bjtst vbic bsim3v3 bsim4 mos1 mos2 mos3 mos902 bjt (BJT_NPN, BJT_PNP ) bht (HICUM_NPN, HICUM_PNP) bjt503 (BJT_NPN, BJT_PNP) bjt504 (M504_BJT_NPN, M504_BJT_PNP) bjtst (BJT_NPN, BJT_PNP) vbic (VBIC_NPN, VBIC_PNP) bsim3v3 (MOSFET_NMOS, MOSFET_PMOS) bsim4 (BSIM4_NMOS, BSIM4_PMOS) mos1 (MOSFET_NMOS, MOSFET_PMOS) mos2 (MOSFET_NMOS, MOSFET_PMOS) mos3 (MOSFET_NMOS, MOSFET_PMOS) mos902 (MM9_NMOS, MM9_PMOS) bjt bht bjt503 bjt504 bjtst vbic bsim3v3 bsim4 mos1 mos2 mos3 mos902 BJT (BJT_Model) HICUM (HICUM_Model) MextramBJT (MEXTRAM_Model) MextramBJT504 (MEXTRAM_504_Model) STBJT (STBJT_Model) VBIC (VBIC_Model) MOSFET (BSIM3_Model) BSIM4 (BSIM4_Model) MOSFET (LEVEL1_Model) MOSFET (LEVEL2_Model) MOSFET (LEVEL3_Model) MOS9 (MOS_Model9_Single) Supported types are dc, sine, pwl, exp, and pulse. 3-2 Internal Mapping

37 Table 3-1. Supported Devices and Models Spectre Instance ADSsim Instance Spectre Model ADSsim Model mos903 mos903 (MM9_NMOS, MM9_PMOS) mos903 MOS9 (MOS_Model9_Single) jfet jfet (JFET_NFET, JFET_PFET) jfet JFET (JFET_Model) cccs SDD pcccs SDD ccvs SDD pccvs SDD vccs SDD pvccs SDD vcvs SDD pvcvs SDD vsource V_Source isource I_Source port(type=dc) rfdepdc port(type=sine) rfdepsin port(type=exp) rfdepexp port(type=pwl) rfdeppwl port(type=pulse) rfdeppulse bsource Bsource delay Hybrid iprobe Short transformer Hybrid nport SnP Supported types are dc, sine, pwl, exp, and pulse. Internal Mapping 3-3

38 Compatible Devices and Models Supported Devices and Models This section provides a list of supported devices and models Passive Devices and Models Resistor on page 3-5 Capacitor on page 3-7 Inductor on page 3-9 Mutual Inductor on page 3-11 Diode and Bipolar Devices and Models Diode on page 3-12 JUNCAP (Junction Capacitor) on page 3-16 BJT (Bipolar Junction Transistors) on page 3-19 BHT (HICUM) on page 3-25 BJT503 on page 3-30 BJT504 on page 3-34 BJTST on page 3-41 VBIC on page 3-45 FET Devices and Models BSIM3v3 on page 3-50 BSIM4 on page 3-67 MOS1 on page 3-89 MOS2 on page 3-94 MOS3 on page MOS902 on page MOS903 on page JFET on page Sources Supported Sources on page Behavioral Source (bsource) on page Supported Devices and Models

39 Resistor Table 3-2 shows the supported resistor instance parameter mapping. The Spectre resistor instance is mapped to the ADSsim R instance. For more information on the resistor in Spectre, refer to the Two Terminal Resistor (resistor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the resistor device in RFDE, refer to R (Resistor) in Chapter 2 of the Introduction to Circuit Components documentation. Table 3-2. Supported Resistor Instance Parameters Spectre ADSsim Comments r R tc1 TC1 tc1r TC1 alias for tc1 tc2 TC2 tc2r TC2 alias for tc2 isnoisy Noise trise Trise w Width l Length Table 3-3 shows the supported resistor model parameter mapping. The Spectre resistor model is mapped to the ADSsim R_model. For more information on the resistor model in RFDE, refer to R_Model (Resistor Model) in Chapter 2 of the Introduction to Circuit Components documentation. Table 3-3. Supported Resistor Model Parameters Spectre r rsh l w etch etchl tnom ADSsim R Rsh Length Width Dw Dl Tnom Supported Devices and Models 3-5

40 Compatible Devices and Models Table 3-3. Supported Resistor Model Parameters Spectre tc1 tc2 scaler trise coeffs kf af wdexp ldexp weexp leexp fexp ADSsim TC1 TC2 Scale Trise Coeffs Kf Af Wdexp Ldexp Weexp Leexp Fexp Table 3-4 shows the supported resistor model DC operating point parameter mapping. The Spectre resistor model is mapped to the ADSsim R_model. Table 3-4. Supported Resistor Model DC Operating Point Parameters Spectre i pwr res v ADSsim i power r v 3-6 Supported Devices and Models

41 Capacitor Table 3-5 shows the supported capacitor instance parameter mapping. The Spectre capacitor instance is mapped to the ADSsim C instance. For more information on the capacitor in Spectre, refer to the Two Terminal Capacitor (capacitor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the capacitor device in RFDE, refer to C (Capacitor) in Chapter 2 of the Introduction to Circuit Components documentation. Table 3-5. Supported Capacitor Instance Parameters Spectre c tc1 tc2 ic w l trise ADS C TC1 TC2 InitCond Width Length Trise Table 3-6 shows the supported capacitor model parameter mapping. The Spectre capacitor model is mapped to the ADSsim C_model. For more information on the capacitor model in RFDE, refer to C_Model (Capacitor Model) in Chapter 2 of the Introduction to Circuit Components documentation. Table 3-6. Supported Capacitor Model Parameters Spectre c cj cjsw l w etch tnom tc1 tc2 ADS C Cj Cjsw Length Width Narrow Tnom TC1 TC2 Supported Devices and Models 3-7

42 Compatible Devices and Models Table 3-6. Supported Capacitor Model Parameters Spectre scalec trise coeffs ADS Scale Trise Coeffs Table 3-7 shows the supported capacitor model DC operating point parameter mapping. The Spectre capacitor model is mapped to the ADSsim C_model. Table 3-7. Supported Capacitor Model DC Operating Point Parameters Spectre cap ADSsim c 3-8 Supported Devices and Models

43 Inductor Table 3-8 shows the supported inductor instance parameter mapping. The Spectre inductor instance is mapped to the ADSsim L instance. For more information on the inductor in Spectre, refer to the Two Terminal Inductor (inductor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the inductor device in RFDE, refer to L (Inductor) in Chapter 2 of the Introduction to Circuit Components documentation. Table 3-8. Supported Inductor Instance Parameters Spectre l r ic isnoisy trise tc1 tc2 ADSsim L R InitCond Noise Trise TC1 TC2 Table 3-9 shows the supported inductor model parameter mapping. The Spectre inductor model is mapped to the ADSsim L_model. For more information on the inductor model in RFDE, refer to L_Model (Inductor Model) in Chapter 2 of the Introduction to Circuit Components documentation. Table 3-9. Supported Inductor Model Parameters Spectre l r tnom tc1 tc2 scalei trise coeffs ADSsim L R Tnom TC1 TC2 Scale Trise Coeffs Supported Devices and Models 3-9

44 Compatible Devices and Models Table 3-9. Supported Inductor Model Parameters Spectre kf af ADSsim Kf Af Table 3-10 shows the supported inductor model DC operating point parameter mapping. The Spectre inductor model is mapped to the ADSsim L_model. Table Supported Inductor Model DC Operating Point Parameters Spectre i ind ADSsim i l 3-10 Supported Devices and Models

45 Mutual Inductor Table 3-11 shows the supported mutual_inductor instance parameter mapping. The Spectre mutual_inductor instance is mapped to the ADSsim Mutual instance. For more information on the mutual inductor in Spectre, refer to the Mutual Inductor (mutual inductor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the mutual inductor in RFDE, refer to Mutual (Mutual Inductor) in Chapter 2 of the Introduction to Circuit Components documentation. Table Supported Mutual Inductor Instance Parameters Spectre coupling k mind ind1 ind2 ADSsim K K M Inductor1 Inductor2 Supported Devices and Models 3-11

46 Compatible Devices and Models Diode Table 3-12 shows the supported diode instance parameter mapping. The Spectre diode instance is mapped to the ADSsim Diode instance. For more information on the diode in Spectre, refer to the Diode Model (diode) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the diode device in RFDE, refer to Diode (PN-Junction Diode) in Chapter 1 of the Nonlinear Devices documentation. Table Supported Diode Instance Parameters Spectre ADSsim Comments area Area lv1 Area alias for area perim Periph pj Periph l Length w Width scale Scale region Region off -> 0 on -> 1 breakdown -> ignored trise Trise Table 3-13 shows the supported diode model parameter mapping. The Spectre diode model is mapped to the ADSsim Diode model. For more information on the diode model in RFDE, refer to Diode_Model (PN-Junction Diode Model) in Chapter 1 of the Nonlinear Devices documentation. Table Supported Diode Model Parameters Spectre ADSsim Comments level Level level=1,3 -> Level=11 Junction level=2 -> Not Supported etch etch1 shrink l Etch Etch1 Shrink Length 3-12 Supported Devices and Models

47 Table Supported Diode Model Parameters Spectre ADSsim Comments w Width js Js is Is jsw Jsw isw Isw n N ns Ns ik Ikf ikp Ikp ikr Ikr area Area perim Periph allow_scaling AllowScaling tt Tt cd Cd lx5 Cd cjo Cjo vj Vj m M cjsw Cjsw cjp Cjsw alias for cjsw vjsw Vjsw php Vjsw alias for vjsw mjsw Msw fc Fc fcs Fcsw bv Bv vb Bv alias for bv ibv Ibv nz Nbv bvj Bvj rs Rs rsw Rsw gleak Gleak gleaksw Gleaksw Supported Devices and Models 3-13

48 Compatible Devices and Models Table Supported Diode Model Parameters Spectre ADSsim Comments minr Minr tlev Tlev tlevc Tlevc eg Eg gap1 Gap1 gap2 Gap2 xti Xti tbv1 Tbv1 tcv Tbv1 alias for tbv1 tbv2 Tbv2 tnom Tnom trise Trise trs Trs trs2 Trs2 tgs Tgs tgs2 Tgs2 cta Tcjo ctp Tcjsw pta Tvj ptp Tvjsw jmelt Imelt imelt Imelt expli Imelt imax Imax jmax Imax kf Kf af Af ttt1 Ttt1 ttt2 Ttt2 tm1 Tm1 tm2 Tm2 cj Cjo mj M pt Pt 3-14 Supported Devices and Models

49 Table Supported Diode Model Parameters Spectre ADSsim Comments pj pbsw Periph Vjsw Table 3-14 shows the supported diode model DC operating point parameter mapping. The Spectre diode model is mapped to the ADSsim Diode model. Table Supported Diode Model DC Operating Point Parameters Spectre cap capp i lx1 pwr res resp v ADSsim cd cdsw id id power rd rdsw vd Supported Devices and Models 3-15

50 Compatible Devices and Models JUNCAP (Junction Capacitor) Table 3-15 shows the supported juncap instance parameter mapping. The Spectre juncap instance is mapped to the ADSsim Juncap instance. For more information on the junction capacitor in Spectre, refer to the Junction Capacitor (juncap) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the junction capacitor device in RFDE, refer to JUNCAP (Philips JUNCAP Device) in Chapter 1 of the Nonlinear Devices documentation. Table Supported Junction Capacitor Instance Parameters Spectre ADSsim Comments ab Ab ls Ls lg Lg region Region rev -> 0 fwd -> 1 breakdown -> ignored Table 3-16 shows the supported juncap model parameter mapping. The Spectre juncap model is mapped to the ADSsim Juncap model. For more information on the junction capacitor model in RFDE, refer to Juncap_Model (Philips JUNCAP Model) in Chapter 1 of the Nonlinear Devices documentation. Table Supported Junction Capacitor Model Parameters Spectre ADSsim Comments type Reversed type=n -> Reversed=1 type=p -> Reversed=0 jsgbr Jsgbr jsdbr Jsdbr jsgsr Jsgsr jsdsr Jsdsr jsggr Jsggr jsdgr Jsdgr imax Imax dta Trise alias of trise trise Trise 3-16 Supported Devices and Models

51 Table Supported Junction Capacitor Model Parameters Spectre ADSsim Comments tr Tr tref Tr alias of tr tnom Tr cjbr Cjbr cjsr Cjsr cjgr Cjgr nb Nb ns Ns ng Ng vr Vr vdbr Vdbr vdsr Vdsr vdgr Vdgr pb Pb ps Ps pg Pg cjb Cjb cjs Cjs cjg Cjg isdb Isdb isds Isds isdg Isdg isgb Isgb isgs Isgs isgg Isgg vdb Vdb vds Vds vdg Vdg Table 3-17 shows the supported juncap model DC operating point parameter mapping. The Spectre juncap model is mapped to the ADSsim Juncap model. Supported Devices and Models 3-17

52 Compatible Devices and Models Table Supported Junction Capacitor Model DC Operating Point Parameters Spectre c i pwr v ADSsim cd id power vd 3-18 Supported Devices and Models

53 BJT (Bipolar Junction Transistors) Table 3-18 shows the supported bjt instance parameter mapping. The Spectre bjt instance is mapped to the ADSsim bjt instance. For more information on the bipolar junction transistor in Spectre, refer to the BJT Model (bjt) in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the bjt device in RFDE, refer to BJT_NPN, BJT_PNP (Bipolar Junction Transistors NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJT Instance Parameters Spectre ADSsim Comments area Area trise Trise region Region off -> 0 fwd -> 1 rev -> 2 sat -> 3 others -> (ignored) Table 3-19 shows the supported bjt model parameter mapping. The Spectre bjt model is mapped to the ADSsim BJT model. For more information on the bjt model in RFDE, refer to BJT_Model (Bipolar Transistor Model) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJT Model Parameters Spectre ADSsim Comments type NPN & PNP type=npn -> NPN=1 PNP=0 type=pnp -> NPN=0 PNP=1 struct Lateral struct=lateral -> Lateral=1 struct=vertical -> Lateral=0 is ise isc iss c2 c4 cbo Is Ise Isc Iss C2 C4 Cbo Supported Devices and Models 3-19

54 Compatible Devices and Models Table Supported BJT Model Parameters Spectre ADSsim Comments gbo Gbo vbo Vbo tcbo Tcbo tgbo Tgbo nf Nf nr Nr ne Ne nc Nc ns Ns bf Bf br Br ikf Ikf jbf Ikf alias for ikf ikr Ikr jbr Ikr alias for ikr vaf Vaf va Vaf var Var vb Var ke Ke kc Kc rb Rb rbm Rbm irb Irb jrb Irb alias for irb rbmod RbModel rc Rc rcv Rcv rcm Rcm dope Dope cex Cex cco Cco re Re minr Minr cje Cje 3-20 Supported Devices and Models

55 Table Supported BJT Model Parameters Spectre ADSsim Comments vje Vje mje Mje cjc Cjc vjc Vjc mjc Mjc xcjc Xcjc xcjc2 Xcjc2 cjs Cjs vjs Vjs mjs Mjs fc Fc tf Tf td Td xtf Xtf vtf Vtf itf Itf jtf Itf alias for itf tr Tr ptf Ptf tnom Tnom trise Trise eg Eg xtb Xtb xti Xti pt Xti alias for xti trb1 Trb1 trb2 Trb2 trm1 Trm1 trm2 Trm2 trc1 Trc1 trc2 Trc2 tre1 Tre1 tre2 Tre2 tlev Tlev tlevc Tlevc Supported Devices and Models 3-21

56 Compatible Devices and Models Table Supported BJT Model Parameters Spectre ADSsim Comments gap1 gap2 tikf1 tikf2 tikr1 tikr2 tirb1 tirb2 tis1 tis2 tise1 tise2 tisc1 tisc2 tiss1 tiss2 tbf1 tbf2 tbr1 tbr2 tvaf1 tvaf2 tvar1 tvar2 titf1 titf2 ttf1 ttf2 ttr1 ttr2 tnf1 tnf2 tnr1 tnr2 tne1 EgAlpha EgBeta Tikf1 Tikf2 Tikr1 Tikr2 Tirb1 Tirb2 Tis1 Tis2 Tise1 Tise2 Tisc1 Tisc2 Tiss1 Tiss2 Tbf1 Tbf2 Tbr1 Tbr2 Tvaf1 Tvaf2 Tvar1 Tvar2 Titf1 Titf2 Ttf1 Ttf2 Ttr1 Ttr2 Tnf1 Tnf2 Tnr1 Tnr2 Tne Supported Devices and Models

57 Table Supported BJT Model Parameters Spectre ADSsim Comments tne2 Tne2 tnc1 Tnc1 tnc2 Tnc2 tns1 Tns1 tns2 Tns2 tmje1 Tmje1 tmje2 Tmje2 tmjc1 Tmjc1 tmjc2 Tmjc2 tmjs1 Tmjs1 tmjs2 Tmjs2 cte Cte ctc Ctc cts Cts tvje Tvje tvjc Tvjc tvjs Tvjs tvtf1 Tvtf1 tvtf2 Tvtf2 txtf1 Txtf1 txtf2 Txtf2 bvbe Bvbe bvbc Bvbc bvsub Bvwub vbcfwd Vbcfwd vsubfwd Vsubfwd imax Imax kf Kf af Af kb Kb bnoisefc Fb rbnoi Rbnoi cse Tccs Undocumented Spectre parameter nkf Nk Undocumented Spectre parameter Supported Devices and Models 3-23

58 Compatible Devices and Models Table 3-20 shows the supported bjt model DC operating point parameter mapping. The Spectre bjt model is mapped to the ADSsim BJT model. Table Supported BJT Model DC Operating Point Parameters Spectre betaac betadc cmu cmux cpi csub ft gm ib ic isub lv5 lx0 lx1 lx19 lx2 lx20 lx21 lx22 lx3 lx6 pwr ro rpi vbc vbe vce ADSsim betaac betadc cmu cbx cpi ccs ft gm ib ic is ft vbe vbc cpi ic cmu ccs cbx ib gm power ro rpi vbc vbe vce 3-24 Supported Devices and Models

59 BHT (HICUM) Table 3-21 shows the supported bht instance parameter mapping. The Spectre bht instance is mapped to the ADSsim bht instance. For more information on the HICUM bipolar transistor in Spectre, refer to the HICUM Model (bht) in Chapter 6 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the bht device in RFDE, refer to HICUM_NPN, HICUM_PNP (HICUM Bipolar Transistors, NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BHT Instance Parameters Spectre trise self_heating ADSsim Trise Selfheating Table 3-22 shows the supported bht model parameter mapping. The Spectre bht model is mapped to the ADSsim HICUM model. For more information on the HICUM model in RFDE, refer to HICUM_Model (Bipolar Transistor Model) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BHT Model Parameters Spectre ADSsim Comments type NPN & PNP type=npn -> NPN=1 PNP=0 type=pnp -> NPN=0 PNP=1 latb latl c10 qp0 ich hjci hjei mcf tsf hfc hfe alit Latb Latl C10 Qp0 Ich Hjci Hjei Mcf Tsf Hfc Hfe Alit Supported Devices and Models 3-25

60 Compatible Devices and Models Table Supported BHT Model Parameters Spectre ADSsim Comments cjei0 vdei zei aljei cjci0 vdci zci vptci t0 dt0h tbvl tef0 gtfe thcs alhc fthc vces rci0 vlim vpt tr alqf ibeis mbei ireis mrei ibcis mbci favl qavl rbi0 fdqr0 fgeo fqi fcrbi Cjei0 Vdei Zei Aljei Cjci0 Vdci Zci Vptci T0 Dt0h Tbvl Tef0 Gtfe Thcs Alhc Fthc Vces Rci0 Vlim Vpt Tr Alqf Ibeis Mbei Ireis Mrei Ibcis Mbci Favl Qavl Rbi0 Fdqr0 Fgeo Fqi Fcrbi 3-26 Supported Devices and Models

61 Table Supported BHT Model Parameters Spectre ADSsim Comments cjep0 vdep zep aljep ibeps mbep ireps mrep cjcx0 vdcx zcx vptcx ccox fbc ibcxs mbcx ceox rbx re rcx cjs0 vds zs vpts rsu csu iscs msc itss msf msr ibets abet kf af Cjep0 Vdep Zep Aljep Ibeps Mbep Ireps Mrep Cjcx0 Vdcx Zcx Vptcx Ccox Fbc Ibcxs Mbcx Ceox Rbx Re Rcx Cjs0 Vds Zs Vpts Rsu Csu Iscs Msc Itss Msf Msr Ibets Abet Kf Af Supported Devices and Models 3-27

62 Compatible Devices and Models Table Supported BHT Model Parameters Spectre ADSsim Comments krbi vgb alb alfav alqav zetaci alvs alces zetarbi zetarbx zetarcx zetare alt0 kt0 rth cth trise tnom Krbi Vgb Alb Alfav Alqav Zetaci Alvs Alces Zetarbi Zetarbx Zetarcx Zetare Alt0 Kt0 Rth Cth Trise Tnom Table 3-23 shows the supported bht model DC operating point parameter mapping. The Spectre bht model is mapped to the ADSsim HICUM model. Table Supported BHT Model DC Operating Point Parameters Spectre cdci cdei cjci cjei cjep cjs gm ib ic is pwr ADSsim cdci cdei cjci cjei cjep cjs gm ib ic is power 3-28 Supported Devices and Models

63 Table Supported BHT Model DC Operating Point Parameters Spectre rbi sfb sfc srb src temp vbci vcei ADSsim rbi sfb sfc srb src temp vbc vce Supported Devices and Models 3-29

64 Compatible Devices and Models BJT503 Table 3-24 shows the supported bjt503 instance parameter mapping. The Spectre bjt503 instance is mapped to the ADSsim bjt503 instance. For more information on the vertical NPN/PNP transistor (bjt503) in Spectre, refer to the Vertical NPN/PNP Transistor (bjt503) in Chapter 11 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the bjt503 device in RFDE, refer to BJT_NPN, BJT_PNP (Bipolar Junction Transistors NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJT503 Instance Parameters Spectre ADSsim Comments area Area mult Area Alias for area region Region off -> 0 fwd -> 1 rev -> 2 sat -> 3 others -> (ignored) Table 3-25 shows the supported bjt503 model parameter mapping. The Spectre bjt503 model is mapped to the ADSsim MextramBJT model. For more information on the bjt503 model in RFDE, refer to MEXTRAM_Model (MEXTRAM Model) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJT503 Model Parameters Spectre ADSsim Comments type NPN & PNP type=npn -> NPN=1 PNP=0 type=pnp -> NPN=0 PNP=1 exmod exphi exavl is bf xibi ibf Exmod Exphi Exavl Is Bf Xibi Ibf 3-30 Supported Devices and Models

65 Table Supported BJT503 Model Parameters Spectre ADSsim Comments vlf Vlf ik Ik bri Bri ibr Ibr vlr Vlr xext Xext qbo Qb0 eta Eta avl Avl efi Efi ihc Ihc rcc Rcc rcv Rcv scrcv Scrcv sfh Sfh rbc Rbc rbv Rbv re Re taune Taune mtau Mtau cje Cje vde Vde pe Pe xcje Xcje cjc Cjc vdc Vdc pc Pc xp Xp mc Mc xcjc Xcjc tref Tref tnom Tref alias for tref tr Tref alias for tref dta Dta trise Dta Supported Devices and Models 3-31

66 Compatible Devices and Models Table Supported BJT503 Model Parameters Spectre ADSsim Comments vge vgb vgc vgj vi na er ab aepi aex ac kf kfn af iss iks cjs vds ps vgs as Vge Vgb Vgc Vgj Vi Na Er Ab Aepi Aex Ac Kf Kfn Af Iss Iks Cjs Vds Ps Vgs As Table 3-26 shows the supported bjt503 model DC operating point parameter mapping. The Spectre bjt503 model is mapped to the ADSsim MextramBJT model. Table Supported BJT503 Model DC Operating Point Parameters Spectre cb1b2 ib ic ie is pwr vbc ADSsim cb1b2 ib ic ie is power vbc 3-32 Supported Devices and Models

67 Table Supported BJT503 Model DC Operating Point Parameters Spectre vbe vce ADSsim vbe vce Supported Devices and Models 3-33

68 Compatible Devices and Models BJT504 Table 3-27 shows the supported bjt504 instance parameter mapping. The Spectre bjt504 instance is mapped to the ADSsim bjt504 instance. For more information on the vertical NPN/PNP transistor (bjt504) in Spectre, refer to the Vertical NPN/PNP Transistor (bjt504) in Chapter 7 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the bjt504 device in RFDE, refer to M504_BJT_NPN, M504_BJT_PNP (Mextram 504 Nonlinear Bipolar Transistors) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJT504 Instance Parameters Spectre ADSsim Comments mult Mult area Area alias of mult Table 3-28 shows the supported bjt504 model parameter mapping. The Spectre bjt504 model is mapped to the ADSsim MextramBJT504 model. For more information on the bjt504 model in RFDE, refer to MEXTRAM_504_Model (MEXTRAM 504 Model) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJT504 Model Parameters Spectre ADSsim Comments type NPN & PNP type=npn -> NPN=1 PNP=0 type=pnp -> NPN=0 PNP=1 tref Tref tnom Tnom tr Tref alias of tref in Spectre level Level dta Dta exmod Exmod exphi Exphi exavl Exavl is Is ik Ik ver Ver 3-34 Supported Devices and Models

69 Table Supported BJT504 Model Parameters Spectre ADSsim Comments vef bf ibf mlf xibi bri ibr vlr xext wavl vavl sfh re rbc rbv rcc rcv scrcv ihc axi cje vde pe xcje cbeo cjc vdc pc xp mc xcjc cbco mtau taue taub Vef Bf Ibf Mlf Xibi Bri Ibr Vlr Xext Wavl Vavl Sfh Re Rbc Rbv Rcc Rcv Scrcv Ihc Axi Cje Vde Pe Xcje Cbeo Cjc Vdc Pc Xp Mc Xcjc Cbco Mtau Taue Taub Supported Devices and Models 3-35

70 Compatible Devices and Models Table Supported BJT504 Model Parameters Spectre ADSsim Comments tepi taur deg xrec aqbo ae ab aepi aex ac dvgbf dvgbr vgb vgc vgj dvgte af kf kfn iss iks cjs vds ps vgs as Tepi Taur Deg Xrec Aqbo Ae Ab Aepi Aex Ac dvgbf dvgbr Vgb Vgc Vgj dvgte Af Kf Kfn Iss Iks Cjs Vds Ps Vgs As Table 3-29 shows the supported bjt504 model DC operating point parameter mapping. The Spectre bjt504 model is mapped to the ADSsim MextramBJT504 model. Table Supported BJT504 Model DC Operating Point Parameters Spectre Cb1b2 cb1b2 ADSsim cb1b2 cb1b Supported Devices and Models

71 Table Supported BJT504 Model DC Operating Point Parameters Spectre Cb1b2x cb1b2x Cb1b2y cb1b2y Cb1b2z cb1b2z Cbcex cbcex Cbcx cbcx Cbcy cbcy Cbcz cbcz Cbex cbex Cbey cbey Cbez cbez Cts cts gmuex gmux gmuy gmuz gpix gpiy gpiz grbvx grbvy grbvz grcvy grcvz gs ADSsim cb1b2x cb1b2x cb1b2y cb1b2y cb1b2z cb1b2z cbcex cbcex cbcx cbcx cbcy cbcy cbcz cbcz cbex cbex cbey cbey cbez cbez cts cts gmuex gmux gmuy gmuz gpix gpiy gpiz grbvx grbvy grbvz grcvy grcvz gs Supported Devices and Models 3-37

72 Compatible Devices and Models Table Supported BJT504 Model DC Operating Point Parameters Spectre gs gsf gsf gx gy gz Iavl iavl Ib ib Ib1 ib1 Ib1b2 ib1b2 Ib2 ib2 Ib3 ib3 Ic ic Ic1c2 ic1c2 Iex iex In in IRBC irbc IRCC ircc IRE ire Isf isf Isub ADSsim gs gsf gsf gx gy gz iavl iavl ib ib ib1 ib1 ib1b2 ib1b2 ib2 ib2 ib3 ib3 ic ic ic1c2 ic1c2 iex iex in in irbc irbc ircc ircc ire ire isf isf isub 3-38 Supported Devices and Models

73 Table Supported BJT504 Model DC Operating Point Parameters Spectre isub Qb1b2 qb1b2 Qbc qbc Qbe qbe Qe qe Qepi qepi Qex qex Qtc qtc Qte qte Qtex qtex Qts qts Rbv rbv SCbe scbe Sgpi sgpi SIb1 sib1 SQte sqte XCbcex xcbcex Xgmuex xgmuex ADSsim isub qb1b2 qb1b2 qbc qbc qbe qbe qe qe qepi qepi qex qex qtc qtc qte qte qtex qtex qts qts rbv rbv scbe scbe sgpi sgpi sib1 sib1 sqte sqte xcbcex xcbcex xgmuex xgmuex Supported Devices and Models 3-39

74 Compatible Devices and Models Table Supported BJT504 Model DC Operating Point Parameters Spectre XgS xgs XIex xiex XIsub xisub XQex xqex XQtex xqtex ADSsim xgs xgs xiex xiex xisub xisub xqex xqex xqtex xqtex 3-40 Supported Devices and Models

75 BJTST Table 3-30 shows the supported bjtst instance parameter mapping. The Spectre bjtst instance is mapped to the ADSsim bjtst instance. For more information on the bjtst in Spectre, refer to the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the bjtst device in RFDE, refer to BJT_NPN, BJT_PNP (Bipolar Junction Transistors NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJTST Instance Parameters Spectre area ADSsim Area Table 3-31 shows the supported bjtst model parameter mapping. The Spectre bjtst model is mapped to the ADSsim STBJT model. For more information on the bjtst model in RFDE, refer to STBJT_Model (ST Bipolar Transistor Model) in Chapter 2 of the Nonlinear Devices documentation. Table Supported BJTST Model Parameters Spectre ADSsim Comments type NPN & PNP type=npn -> NPN=1 PNP=0 type=pnp -> NPN=0 PNP=1 is isn bf nf br nr isf nbf isr nbr ise ne isc nc Is Isn Bf Nf Br Nr Isf Nbf Isr Nbr Ise Ne Isc Nc Supported Devices and Models 3-41

76 Compatible Devices and Models Table Supported BJTST Model Parameters Spectre ADSsim Comments vaf var ikf ikr enp rp rw vjj vrp bvc mf fa avc bve mr fb ave rb irb rbm re rc rcs cje vje mje fc cjc vjc mjc xjbc cjs vjs mjs xjbs Vaf Var Ikf Ikr Enp Rp Rw Vjj Vrp Bvc Mf Fa Avc Bve Mr Fb Ave Rb Irb Rbm Re Rc Rcs Cje Vje Mje Fc Cjc Vjc Mjc Xjbc Cjs Vjs Mjs Xjbs 3-42 Supported Devices and Models

77 Table Supported BJTST Model Parameters Spectre ADSsim Comments vert subsn tf xtf vtf itf ptf tfcc tr kf af eg xti xtb trb1 trb2 trbm1 trbm2 tre1 tre2 trc1 trc2 trcs1 trcs2 tmeas Vert Subsn Tf Xtf Vtf Itf Ptf Tfcc Tr Kf Af Eg Xti Xtb Trb1 Trb2 Trbm1 Trbm2 Tre1 Tre2 Trc1 Trc2 Trcs1 Trcs2 Tmeas Table 3-32 shows the supported bjtst model DC operating point parameter mapping. The Spectre bjtst model is mapped to the ADSsim STBJT model. Table Supported BJTST Model DC Operating Point Parameters Spectre betaac betadc cbs cbx ADSsim betaac betadc cbs cbx Supported Devices and Models 3-43

78 Compatible Devices and Models Table Supported BJTST Model DC Operating Point Parameters Spectre ccs cmu cpi cxs gm ib ic rcv rmu ro rpi rx vbc vbe vce ADSsim ccs cmu cpi cxs gm ib ic rcv rmu ro rpi rx vbc vbe vce 3-44 Supported Devices and Models

79 VBIC Table 3-33 shows the supported vbic instance parameter mapping. The Spectre vbic instance is mapped to the ADSsim vbic instance. For more information on the VBIC model, refer to VBIC Model (vbic) in Chapter 8 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the VBIC device in RFDE, refer to VBIC_NPN, VBIC_PNP (VBIC Nonlinear Bipolar Transistors, NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation. Table Supported VBIC Instance Parameters Spectre ADSsim Comments area Scale region Region off -> 0 fwd -> 1 rev -> 2 sat -> 3 others -> (ignored) trise Trise dtmp Trise alias for trise dtemp Trise alias for trise Table 3-34 shows the supported vbic model parameter mapping. The Spectre vbic model is mapped to the ADSsim VBIC model. For more information on the vbic model in RFDE, refer to VBIC_Model (VBIC Model) in Chapter 2 of the Nonlinear Devices documentation. Table Supported VBIC Model Parameters Spectre ADSsim Comments type NPN & PNP type=npn -> NPN=1 PNP=0 type=pnp -> NPN=0 PNP=1 is ibei iben ibci ibcn isp Is Ibei Iben Ibci Ibcn Isp Supported Devices and Models 3-45

80 Compatible Devices and Models Table Supported VBIC Model Parameters Spectre ADSsim Comments ibeip ibenp ibcip ibcnp vo gamm hrcf wbe wsp nf nr nei nen nci ncn nfp ncip ncnp ikf ikr ikp vef ver avc1 avc2 rbi rbx re rs rbp rcx rci cje pe me Ibeip Ibenp Ibcip Ibcnp Vo Gamm Hrcf Wbe Wsp Nf Nr Nei Nen Nci Ncn Nfp Ncip Ncnp Ikf Ikr Ikp Vef Ver Avc1 Avc2 Rbi Rbx Re Rs Rbp Rcx Rci Cje Pe Me 3-46 Supported Devices and Models

81 Table Supported VBIC Model Parameters Spectre ADSsim Comments aje Aje fc Fc cbeo Cbeo cjc Cjc cjep Cjep pc Pc mc Mc ajc Ajc cbco Cbco qco Qco cjcp Cjcp ps Ps ms Ms ajs Ajs tf Tf tr Tr td Td qtf Qtf xtf Xtf vtf Vtf itf Itf selft Selft tnom Tnom trise Trise dtmp Trise alias for trise dtemp Trise alias for trise rth Rth cth Cth xis Xis xii Xii xin Xin tnf Tnf tavc Tavc ea Ea eaie Eaie Supported Devices and Models 3-47

82 Compatible Devices and Models Table Supported VBIC Model Parameters Spectre ADSsim Comments eaic Eaic eais Eais eane Eane eanc Eanc eans Eans xre Xre xrb Xrb xrbi Xrb alias for xrb xrc Xrc xrci Xrc alias for xrc xrs Xrs xvo Xvo dtmax Dtmax kfn Kfn afn Afn bfn Bfn imelt Imelt bvbe wbvbe bvbc wbvbc bvsub wbvsub vbcfwd wvbcfwd vsubfwd wvsubfwd imax Imax imax1 wicmax Table 3-35 shows the supported vbic model DC operating point parameter mapping. The Spectre vbic model is mapped to the ADSsim VBIC model. Table Supported VBIC Model DC Operating Point Parameters Spectre cbcp cbep cbex dic_dvbc dic_dvbe ADSsim cbcp cbep cbex dicc_dvbci dicc_dvbei 3-48 Supported Devices and Models

83 Table Supported VBIC Model DC Operating Point Parameters Spectre ib ic pwr vbc vbe vce ADSsim ib ic power vbc vbe vce Supported Devices and Models 3-49

84 Compatible Devices and Models BSIM3v3 Table 3-36 shows the supported bsim3v3 instance parameter mapping. The Spectre bsim3v3 instance is mapped to the ADSsim bsim3v3 instance. For more information on the bsim3v3 model, refer to BSIM3v3 Level-11 Model (bsim3v3) in Chapter 20 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the MOSFET device in RFDE, refer to MOSFET_NMOS, MOSFET_PMOS (Nonlinear MOSFETs, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation. Table Supported bsim3v3 Instance Parameters Spectre ADSsim Comments w Width l Length as As ad Ad ps Ps pd Pd nrd Nrd nrs Nrs region Region off -> 0 triode -> 1 sat -> 3 others-> (ignored) nqsmod Nqsmod trise Trise geo Geo delk1 Delk1 delnfct Delnfct delvto Delvt0 mulu0 Mulu0 sa Sa sb Sb Table 3-37 shows the supported bsim3v3 model parameter mapping. The Spectre bsim3v3 model is mapped to the ADSsim MOSFET model with Idsmod=8 (BSIM3_Model) Supported Devices and Models

85 For more information on the bsim3v3 model in RFDE, refer to BSIM3_Model (BSIM3 MOSFET Model) in Chapter 5 of the Nonlinear Devices documentation. Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments type NMOS & PMOS type=n-> NMOS=yes PMOS=no type=p-> NMOS=no PMOS=yes vtho vth0 vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag nsub nch ngate Vth0 Vth0 Vfb K1 K2 K3 K3b W0 Nlx Gamma1 Gamma2 Vbx Vbm Dvt0 Dvt1 Dvt2 Dvt0w Dvt1w Dvt2w A0 B0 B1 A1 A2 Ags Keta Vfbflag Nsub Nch Ngate Supported Devices and Models 3-51

86 Compatible Devices and Models Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm xt rdsw prwb prwg wr binunit mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb Xj Lint Wint Ll Lln Lw Lwn Lwl Wl Wln Ww Wwn Wwl Dwg Dwb Tox Dtoxcv Toxm Xt Rdsw Prwb Prwg Wr Binunit Mobmod U0 Vsat Ua Ub Uc Drout Pclm Pdiblc1 Pdiblc2 Pdiblcb 3-52 Supported Devices and Models

87 Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw is n imelt ijth Pscbe1 Pscbe2 Pvag Delta Cdsc Cdscb Cdscd Nfactor Cit Voff Dsub Eta0 Etab Alpha0 Alpha1 Beta0 Rsh Rs Rd Lgcs Lgcd Rsc Rdc Rss Rdd Sc Ldif Hdif Minr Js Jsw Is Nj Imelt Ijth Supported Devices and Models 3-53

88 Compatible Devices and Models Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments tt cgso cgdo cgbo cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg capmod nqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc Tt Cgso Cgdo Cgbo Cgsl Cgdl Ckappa Cbs Cbd Cj Mj Pb Fc Cjsw Mjsw Pbsw Cjswg Mjswg Pbswg Capmod Nqsmod Dwc Dlc Clc Cle Cf Elm Vfbcv Acde Moin Noff Voffcv Xpart Llc Lwc 3-54 Supported Devices and Models

89 Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments lwlc wlc wwc wwlc wmlt w l as ad ps pd nrd nrs version paramchk acm calcacm tnom trise tlev tlevc eg gap1 gap2 kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute Lwlc Wlc Wwc Wwlc Wmlt W L As Ad Ps Pd Nrd Nrs Version Paramchk Acm Calcacm Tnom Trise Tlev Tlevc Eg Gap1 Gap2 Kt1 Kt1l Kt2 At Ua1 Ub1 Uc1 Prt Trs Trd Ute Supported Devices and Models 3-55

90 Compatible Devices and Models Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic em flkmod gamma nlev gdsnoi wmax wmin lmax lmin imax bvj vbox xl xw sa0 sb0 wlod Xti Pta Tpb Ptp Tpbsw Tpbswg Cta Tcj Ctp Tcjsw Tcjswg Noimod Kf Af Ef Noia Noib Noic Em Flkmod Gamma Nlev Gdsnoi Wmax Wmin Lmax Lmin Imax wbvsub wbvg Xl Xw Sa0 Sb0 Wlod 3-56 Supported Devices and Models

91 Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments ku0 kvsat kvth0 tku0 llodku0 wlodku0 lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 nj idsmod lxt lvbm lvbx lvfbcv lvfb lxj ldwg ldwb lnch lnsub lngate lgamma1 lgamma2 lalpha0 lalpha1 lacde lmoin Ku0 Kvsat Kvth0 Tku0 Llodku0 Wlodku0 Lku0 Wku0 Pku0 Lkvth0 Wkvth0 Pkvth0 Stk2 Lodk2 Steta0 Lodeta0 Nj Idsmod Lxt Lvbm Lvbx Lvfbcv Lvfb Lxj Ldwg Ldwb Lnch Lnsub Lngate Lgamma1 Lgamma2 Lalpha0 Lalpha1 Lacde Lmoin Supported Devices and Models 3-57

92 Compatible Devices and Models Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments lelm lbeta0 lvth0 lk1 lk2 lk3 lk3b lw0 lnlx ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w ldrout ldsub lua lua1 lub lub1 luc luc1 lu0 lute lrdsw lprwg lprwb lwr lprt lvsat lat la0 lketa lags Lelm Lbeta0 Lvth0 Lk1 Lk2 Lk3 Lk3b Lw0 Lnlx Ldvt0 Ldvt1 Ldvt2 Ldvt0w Ldvt1w Ldvt2w Ldrout Ldsub Lua Lua1 Lub Lub1 Luc Luc1 Lu0 Lute Lrdsw Lprwg Lprwb Lwr Lprt Lvsat Lat La0 Lketa Lags 3-58 Supported Devices and Models

93 Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments la1 la2 lb0 lb1 lvoff lvoffcv lnoff lnfactor lcdsc lcdscb lcdscd lcit leta0 letab lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lkt1 lkt1l lkt2 lcgsl lcgdl lckappa lcf lclc lcle pxt pvbm pvbx pvfbcv La1 La2 Lb0 Lb1 Lvoff Lvoffcv Lnoff Lnfactor Lcdsc Lcdscb Lcdscd Lcit Leta0 Letab Lpclm Lpdiblc1 Lpdiblc2 Lpdiblcb Lpscbe1 Lpscbe2 Lpvag Ldelta Lkt1 Lkt1l Lkt2 Lcgsl Lcgdl Lckappa Lcf Lclc Lcle Pxt Pvbm Pvbx Pvfbcv Supported Devices and Models 3-59

94 Compatible Devices and Models Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments pvfb pxj pdwg pdwb pnch pnsub pngate pgamma1 pgamma2 palpha0 palpha1 pacde pmoin pelm pbeta0 pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pdrout pdsub pua pua1 pub pub1 puc Pvfb Pxj Pdwg Pdwb Pnch Pnsub Pngate Pgamma1 Pgamma2 Palpha0 Palpha1 Pacde Pmoin Pelm Pbeta0 Pvth0 Pk1 Pk2 Pk3 Pk3b Pw0 Pnlx Pdvt0 Pdvt1 Pdvt2 Pdvt0w Pdvt1w Pdvt2w Pdrout Pdsub Pua Pua1 Pub Pub1 Puc 3-60 Supported Devices and Models

95 Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments puc1 pu0 pute prdsw pprwg pprwb pwr pprt pvsat pat pa0 pketa pags pa1 pa2 pb0 pb1 pvoff pvoffcv pnoff pnfactor pcdsc pcdscb pcdscd pcit peta0 petab ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta Puc1 Pu0 Pute Prdsw Pprwg Pprwb Pwr Pprt Pvsat Pat Pa0 Pketa Pags Pa1 Pa2 Pb0 Pb1 Pvoff Pvoffcv Pnoff Pnfactor Pcdsc Pcdscb Pcdscd Pcit Peta0 Petab Ppclm Ppdiblc1 Ppdiblc2 Ppdiblcb Ppscbe1 Ppscbe2 Ppvag Pdelta Supported Devices and Models 3-61

96 Compatible Devices and Models Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments pkt1 pkt1l pkt2 pcgsl pcgdl pckappa pcf pclc pcle wxt wvbm wvbx wvfbcv wvfb wxj wdwg wdwb wnch wnsub wngate wgamma1 wgamma2 walpha0 walpha1 wacde wmoin welm wbeta0 wvth0 wk1 wk2 wk3 wk3b ww0 wnlx Pkt1 Pkt1l Pkt2 Pcgsl Pcgdl Pckappa Pcf Pclc Pcle Wxt Wvbm Wvbx Wvfbcv Wvfb Wxj Wdwg Wdwb Wnch Wnsub Wngate Wgamma1 Wgamma2 Walpha0 Walpha1 Wacde Wmoin Welm Wbeta0 Wvth0 Wk1 Wk2 Wk3 Wk3b Ww0 Wnlx 3-62 Supported Devices and Models

97 Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wdrout wdsub wua wua1 wub wub1 wuc wuc1 wu0 wute wrdsw wprwg wprwb wwr wprt wvsat wat wa0 wketa wags wa1 wa2 wb0 wb1 wvoff wvoffcv wnoff wnfactor wcdsc Wdvt0 Wdvt1 Wdvt2 Wdvt0w Wdvt1w Wdvt2w Wdrout Wdsub Wua Wua1 Wub Wub1 Wuc Wuc1 Wu0 Wute Wrdsw Wprwg Wprwb Wwr Wprt Wvsat Wat Wa0 Wketa Wags Wa1 Wa2 Wb0 Wb1 Wvoff Wvoffcv Wnoff Wnfactor Wcdsc Supported Devices and Models 3-63

98 Compatible Devices and Models Table Supported bsim3v3 Model Parameters Spectre ADSsim Comments wcdscb wcdscd wcit weta0 wetab wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wkt1 wkt1l wkt2 wcgsl wcgdl wckappa wcf wclc wcle Wcdscb Wcdscd Wcit Weta0 Wetab Wpclm Wpdiblc1 Wpdiblc2 Wpdiblcb Wpscbe1 Wpscbe2 Wpvag Wdelta Wkt1 Wkt1l Wkt2 Wcgsl Wcgdl Wckappa Wcf Wclc Wcle Table 3-38 shows the supported bsim3v3 model DC operating point parameter mapping. The Spectre bsim3v3 model is mapped to the ADSsim MOSFET model. Table Supported bsim3v3 Model DC Operating Point Parameters Spectre cbd cbg cbs cdd cdg cds cgd ADSsim dqbdvdb dqbdvgb dqbdvsb dqddvdb dqddvgb dqddvsb dqgdvdb 3-64 Supported Devices and Models

99 Table Supported bsim3v3 Model DC Operating Point Parameters Spectre cgg cgs cjd cjs gds gm gmbs i1 i3 i4 ibulk id is lv10 lv9 lx1 lx18 lx19 lx2 lx20 lx21 lx22 lx23 lx28 lx29 lx3 lx32 lx33 lx34 lx7 lx8 lx9 pwr vbs vds ADSsim dqgdvgb dqgdvsb capbd capbs gds gm gmb id is ib ib id is vdsat vth vbs dqgdvgb dqgdvdb vgs dqgdvsb dqbdvgb dqbdvdb dqbdvsb capbs capbd vds dqddvgb dqddvdb dqddvsb gm gds gmb power vbs vds Supported Devices and Models 3-65

100 Compatible Devices and Models Table Supported bsim3v3 Model DC Operating Point Parameters Spectre vdsat vgs vth ADSsim vdsat vgs vth 3-66 Supported Devices and Models

101 BSIM4 Table 3-39 shows the supported bsim4 instance parameter mapping. The Spectre bsim4 instance is mapped to the ADSsim bsim4 instance. For more information on the bsim4 model, refer to BSIM4.2 Level-14 Model (bsim4) in Chapter 21 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the BSIM4 device in RFDE, refer to BSIM4_NMOS, BSIM4_PMOS (BSIM4 Transistor, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation. Table Supported bsim4 Instance Parameter Mapping Spectre ADSsim Comments w Width l Length as As ad Ad ps Ps pd Pd nrd Nrd nrs Nrs trnqsmod Trnqsmod acnqsmod Acnqsmod trise Trise dtemp Trise alias of trise rgatemod Rgatemod rbodymod Rbodymod geomod Geomod rgeomod Rgeomod rbpb Rbpb rbpd Rbpd rbps Rbps rbdb Rbdb rbsb Rbsb nf Nf min Min sa Sa Supported Devices and Models 3-67

102 Compatible Devices and Models Table Supported bsim4 Instance Parameter Mapping Spectre ADSsim Comments sb sd delvto mulu0 delk1 delnfct Sb Sd Delvt0 Mulu0 Delk1 Delnfct Table 3-40 shows the supported bsim4 model parameter mapping. The Spectre bsim4 model is mapped to the ADSsim BSIM4 model. For more information on the bsim4 model in RFDE, refer to BSIM4_Model (BSIM4 MOSFET Model) in Chapter 5 of the Nonlinear Devices documentation. Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments type NMOS & PMOS type=n-> NMOS=yes PMOS=no type=p-> NMOS=no PMOS=yes vtho vth0 phin k1 k2 k3 k3b w0 lpe0 lpeb gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvtp0 dvtp1 Vth0 Vth0 Phin K1 K2 K3 K3b W0 Lpe0 Lpeb Gamma1 Gamma2 Vbx Vbm Dvt0 Dvt1 Dvt2 Dvtp0 Dvtp Supported Devices and Models

103 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta epsrox toxe toxp dtox ndep nsd nsub ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb toxm xt Dvt0w Dvt1w Dvt2w A0 B0 B1 A1 A2 Ags Keta Epsrox Toxe Toxp Dtox Ndep Nsd Nsub Ngate Xj Lint Wint Ll Lln Lw Lwn Lwl Wl Wln Ww Wwn Wwl Dwg Dwb Toxm Xt Supported Devices and Models 3-69

104 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments binunit rdsmod rdsw rdswmin rdw rdwmin rsw rswmin prwb prwg wr mobmod u0 vsat ua ub uc eu lambda vtl lc xn drout fprout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta pdits pditsl pditsd Binunit Rdsmod Rdsw Rdswmin Rdw Rdwmin Rsw Rswmin Prwb Prwg Wr Mobmod U0 Vsat Ua Ub Uc Eu Lambda Vtl Lc Xn Drout Fprout Pclm Pdiblc1 Pdiblc2 Pdiblcb Pscbe1 Pscbe2 Pvag Delta Pdits Pditsl Pditsd 3-70 Supported Devices and Models

105 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments cdsc cdscb cdscd nfactor cit voff voffl minv dsub eta0 etab alpha0 alpha1 beta0 rgatemod rsh rshg dmcg dmci dmdg dmcgt dwj xgw xgl ngcon nf permod geomod rgeomod xw xl agidl bgidl cgidl egidl Cdsc Cdscb Cdscd Nfactor Cit Voff Voffl Minv Dsub Eta0 Etab Alpha0 Alpha1 Beta0 Rgatemod Rsh Rshg Dmcg Dmci Dmdg Dmcgt Dwj Xgw Xgl Ngcon Nf Permod Geomod Rgeomod Xw Xl Agidl Bgidl Cgidl Egidl Supported Devices and Models 3-71

106 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments igcmod igbmod aigbacc bigbacc cigbacc nigbacc aigbinv bigbinv cigbinv eigbinv nigbinv aigc bigc cigc aigsd bigsd cigsd dlcig nigc poxedge pigcd ntox toxref diomod jss jsd jsws jswd jswgs jswgd njs njd imelt ijthsrev ijthdrev Igcmod Igbmod Aigbacc Bigbacc Cigbacc Nigbacc Aigbinv Bigbinv Cigbinv Eigbinv Nigbinv Aigc Bigc Cigc Aigsd Bigsd Cigsd Dlcig Nigc Poxedge Pigcd Ntox Toxref Diomod Jss Jsd Jsws Jswd Jswgs Jswgd Njs Njd Imelt Ijthsrev Ijthdrev 3-72 Supported Devices and Models

107 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments ijthsfwd ijthdfwd xjbvs xjbvd cgso cgdo cgbo cgsl cgdl ckappas ckappad cjs cjd mjs mjd pbs pbd cjsws cjswd mjsws mjswd pbsws pbswd cjswgs cjswgd mjswgs mjswgd pbswgs pbswgd bvs bvd capmod trnqsmod acnqsmod dwc Ijthsfwd Ijthdfwd Xjbvs Xjbvd Cgso Cgdo Cgbo Cgsl Cgdl Ckappas Ckappad Cjs Cjd Mjs Mjd Pbs Pbd Cjsws Cjswd Mjsws Mjswd Pbsws Pbswd Cjswgs Cjswgd Mjswgs Mjswgd Pbswgs Pbswgd Bvs Bvd Capmod Trnqsmod Acnqsmod Dwc Supported Devices and Models 3-73

108 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments dlc clc cle cf vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc w l as ad ps pd nrd nrs version paramchk tnom trise tlev tlevc eg gap1 gap2 kt1 kt1l Dlc Clc Cle Cf Vfbcv Acde Moin Noff Voffcv Xpart Llc Lwc Lwlc Wlc Wwc Wwlc W L As Ad Ps Pd Nrd Nrs Version Paramchk Tnom Trise Tlev Tlevc Eg Gap1 Gap2 Kt1 Kt1l 3-74 Supported Devices and Models

109 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments kt2 at ua1 ub1 uc1 prt ute xtis xtid pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg tempmod saref sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 Kt2 At Ua1 Ub1 Uc1 Prt Ute Xtis Xtid Pta Tpb Ptp Tpbsw Tpbswg Cta Tcj Ctp Tcjsw Tcjswg Tempmod Saref Sbref Wlod Ku0 Kvsat Kvth0 Tku0 Llodku0 Wlodku0 Llodvth Wlodvth Lku0 Wku0 Pku0 Lkvth0 Supported Devices and Models 3-75

110 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 fnoimod tnoimod kf af ef noia noib noic em ntnoi tnoia tnoib rnoia rnoib rbodymod xrcrg1 xrcrg2 rbpb rbpd rbps rbdb rbsb gbmin wmax wmin lmax lmin vbox llambda Wkvth0 Pkvth0 Stk2 Lodk2 Steta0 Lodeta0 Fnoimod Tnoimod Kf Af Ef Noia Noib Noic Em Ntnoi Tnoia Tnoib Rnoia Rnoib Rbodymod Xrcrg1 Xrcrg2 Rbpb Rbpd Rbps Rbdb Rbsb Gbmin Wmax Wmin Lmax Lmin wbvg Llambda 3-76 Supported Devices and Models

111 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments wlambda plambda lvtl wvtl pvtl lxn wxn pxn lcdsc lcdsc lcdscb lcdscd lcit lnfactor lxj lvsat lat la0 lags la1 la2 lketa lnsub lndep lnsd lphin lngate lgamma1 lgamma2 lvbx lvbm lxt lk1 lkt1 lkt1l Wlambda Plambda Lvtl Wvtl Pvtl Lxn Wxn Pxn Lcdsc Lcdsc Lcdscb Lcdscd Lcit Lnfactor Lxj Lvsat Lat La0 Lags La1 La2 Lketa Lnsub Lndep Lnsd Lphin Lngate Lgamma1 Lgamma2 Lvbx Lvbm Lxt Lk1 Lkt1 Lkt1l Supported Devices and Models 3-77

112 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments lkt2 lk2 lk3 lk3b lw0 ldvtp0 ldvtp1 llpe0 llpeb ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w ldrout ldsub lvth0 lua lua1 lub lub1 luc luc1 lu0 lute lvoff lminv ldelta lrdsw lrsw lrdw lprwg lprwb lprt Lkt2 Lk2 Lk3 Lk3b Lw0 Ldvtp0 Ldvtp1 Llpe0 Llpeb Ldvt0 Ldvt1 Ldvt2 Ldvt0w Ldvt1w Ldvt2w Ldrout Ldsub Lvth0 Lua Lua1 Lub Lub1 Luc Luc1 Lu0 Lute Lvoff Lminv Ldelta Lrdsw Lrsw Lrdw Lprwg Lprwb Lprt 3-78 Supported Devices and Models

113 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments leta0 letab lpclm lpdiblc1 lpdiblc2 lpdiblcb lfprout lpdits lpditsd lpscbe1 lpscbe2 lpvag lwr ldwg ldwb lb0 lb1 lcgsl lcgdl lckappas lckappad lcf lclc lcle lalpha0 lalpha1 lbeta0 lagidl lbgidl lcgidl legidl laigc lbigc lcigc laigsd Leta0 Letab Lpclm Lpdiblc1 Lpdiblc2 Lpdiblcb Lfprout Lpdits Lpditsd Lpscbe1 Lpscbe2 Lpvag Lwr Ldwg Ldwb Lb0 Lb1 Lcgsl Lcgdl Lckappas Lckappad Lcf Lclc Lcle Lalpha0 Lalpha1 Lbeta0 Lagidl Lbgidl Lcgidl Legidl Laigc Lbigc Lcigc Laigsd Supported Devices and Models 3-79

114 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments lbigsd lcigsd laigbacc lbigbacc lcigbacc laigbinv lbigbinv lcigbinv lnigc lnigbinv lnigbacc lntox leigbinv lpigcd lpoxedge lvfbcv lvfb lacde lmoin lnoff lvoffcv lxrcrg1 lxrcrg2 leu wcdsc wcdscb wcdscd wcit wnfactor wxj wvsat wat wa0 wags wa1 Lbigsd Lcigsd Laigbacc Lbigbacc Lcigbacc Laigbinv Lbigbinv Lcigbinv Lnigc Lnigbinv Lnigbacc Lntox Leigbinv Lpigcd Lpoxedge Lvfbcv Lvfb Lacde Lmoin Lnoff Lvoffcv Lxrcrg1 Lxrcrg2 Leu Wcdsc Wcdscb Wcdscd Wcit Wnfactor Wxj Wvsat Wat Wa0 Wags Wa Supported Devices and Models

115 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments wa2 wketa wnsub wndep wnsd wphin wngate wgamma1 wgamma2 wvbx wvbm wxt wk1 wkt1 wkt1l wkt2 wk2 wk3 wk3b ww0 wdvtp0 wdvtp1 wlpe0 wlpeb wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wdrout wdsub wvth0 wua wua1 Wa2 Wketa Wnsub Wndep Wnsd Wphin Wngate Wgamma1 Wgamma2 Wvbx Wvbm Wxt Wk1 Wkt1 Wkt1l Wkt2 Wk2 Wk3 Wk3b Ww0 Wdvtp0 Wdvtp1 Wlpe0 Wlpeb Wdvt0 Wdvt1 Wdvt2 Wdvt0w Wdvt1w Wdvt2w Wdrout Wdsub Wvth0 Wua Wua1 Supported Devices and Models 3-81

116 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments wub wub1 wuc wuc1 wu0 wute wvoff wminv wdelta wrdsw wrsw wrdw wprwg wprwb wprt weta0 wetab wpclm wpdiblc1 wpdiblc2 wpdiblcb wfprout wpdits wpditsd wpscbe1 wpscbe2 wpvag wwr wdwg wdwb wb0 wb1 wcgsl wcgdl wckappas Wub Wub1 Wuc Wuc1 Wu0 Wute Wvoff Wminv Wdelta Wrdsw Wrsw Wrdw Wprwg Wprwb Wprt Weta0 Wetab Wpclm Wpdiblc1 Wpdiblc2 Wpdiblcb Wfprout Wpdits Wpditsd Wpscbe1 Wpscbe2 Wpvag Wwr Wdwg Wdwb Wb0 Wb1 Wcgsl Wcgdl Wckappas 3-82 Supported Devices and Models

117 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments wckappad wcf wclc wcle walpha0 walpha1 wbeta0 wagidl wbgidl wcgidl wegidl waigc wbigc wcigc waigsd wbigsd wcigsd waigbacc wbigbacc wcigbacc waigbinv wbigbinv wcigbinv wnigc wnigbinv wnigbacc wntox weigbinv wpigcd wpoxedge wvfbcv wvfb wacde wmoin wnoff Wckappad Wcf Wclc Wcle Walpha0 Walpha1 Wbeta0 Wagidl Wbgidl Wcgidl Wegidl Waigc Wbigc Wcigc Waigsd Wbigsd Wcigsd Waigbacc Wbigbacc Wcigbacc Waigbinv Wbigbinv Wcigbinv Wnigc Wnigbinv Wnigbacc Wntox Weigbinv Wpigcd Wpoxedge Wvfbcv Wvfb Wacde Wmoin Wnoff Supported Devices and Models 3-83

118 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments wvoffcv wxrcrg1 wxrcrg2 weu pcdsc pcdscb pcdscd pcit pnfactor pxj pvsat pat pa0 pags pa1 pa2 pketa pnsub pndep pnsd pphin pngate pgamma1 pgamma2 pvbx pvbm pxt pk1 pkt1 pkt1l pkt2 pk2 pk3 pk3b pw0 Wvoffcv Wxrcrg1 Wxrcrg2 Weu Pcdsc Pcdscb Pcdscd Pcit Pnfactor Pxj Pvsat Pat Pa0 Pags Pa1 Pa2 Pketa Pnsub Pndep Pnsd Pphin Pngate Pgamma1 Pgamma2 Pvbx Pvbm Pxt Pk1 Pkt1 Pkt1l Pkt2 Pk2 Pk3 Pk3b Pw Supported Devices and Models

119 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments pdvtp0 pdvtp1 plpe0 plpeb pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pdrout pdsub pvth0 pua pua1 pub pub1 puc puc1 pu0 pute pvoff pminv pdelta prdsw prsw prdw pprwg pprwb pprt peta0 petab ppclm ppdiblc1 ppdiblc2 Pdvtp0 Pdvtp1 Plpe0 Plpeb Pdvt0 Pdvt1 Pdvt2 Pdvt0w Pdvt1w Pdvt2w Pdrout Pdsub Pvth0 Pua Pua1 Pub Pub1 Puc Puc1 Pu0 Pute Pvoff Pminv Pdelta Prdsw Prsw Prdw Pprwg Pprwb Pprt Peta0 Petab Ppclm Ppdiblc1 Ppdiblc2 Supported Devices and Models 3-85

120 Compatible Devices and Models Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments ppdiblcb pfprout ppdits ppditsd ppscbe1 ppscbe2 ppvag pwr pdwg pdwb pb0 pb1 pcgsl pcgdl pckappas pckappad pcf pclc pcle palpha0 palpha1 pbeta0 pagidl pbgidl pcgidl pegidl paigc pbigc pcigc paigsd pbigsd pcigsd paigbacc pbigbacc pcigbacc Ppdiblcb Pfprout Ppdits Ppditsd Ppscbe1 Ppscbe2 Ppvag Pwr Pdwg Pdwb Pb0 Pb1 Pcgsl Pcgdl Pckappas Pckappad Pcf Pclc Pcle Palpha0 Palpha1 Pbeta0 Pagidl Pbgidl Pcgidl Pegidl Paigc Pbigc Pcigc Paigsd Pbigsd Pcigsd Paigbacc Pbigbacc Pcigbacc 3-86 Supported Devices and Models

121 Table Supported bsim4 Model Parameter Mapping Spectre ADSsim Comments paigbinv pbigbinv pcigbinv pnigc pnigbinv pnigbacc pntox peigbinv ppigcd ppoxedge pvfbcv pvfb pacde pmoin pnoff pvoffcv pxrcrg1 pxrcrg2 peu Paigbinv Pbigbinv Pcigbinv Pnigc Pnigbinv Pnigbacc Pntox Peigbinv Ppigcd Ppoxedge Pvfbcv Pvfb Pacde Pmoin Pnoff Pvoffcv Pxrcrg1 Pxrcrg2 Peu Table 3-41 shows the supported bsim4 model DC operating point parameter mapping. The Spectre bsim4 model is mapped to the ADSsim BSIM4 model. Table Supported bsim4 Model DC Operating Point Parameters Spectre cbd cbg cbs cdd cdg cds cgb cgd cgg gds ADSsim dqb_dvdb dqb_dvgb dqb_dvsb dqd_dvdb dqd_dvgb dqd_dvsb dqg_dvsb dqg_dvdb dqg_dvgb gds Supported Devices and Models 3-87

122 Compatible Devices and Models Table Supported bsim4 Model DC Operating Point Parameters Spectre gm gmbs ibulk id lv10 lv9 lx1 lx2 lx3 lx7 lx8 lx82 lx83 lx85 lx86 lx87 lx88 lx89 lx9 lx90 pwr vbs vds vdsat vgs vth ADSsim gm gmb ib id vdsat vth vbs vgs vds gm gds dqg_dvgb dqg_dvdb dqd_dvdb dqd_dvsb dqd_dvgb dqb_dvgb dqb_dvdb gmb dqb_dvsb power vbs vds vdsat vgs vth 3-88 Supported Devices and Models

123 MOS1 Table 3-42 shows the supported mos1 instance parameter mapping. The Spectre mos1 instance is mapped to the ADSsim mos1 instance. For more information on the mos1 model, refer to MOS Level-1 Model (mos1) in Chapter 14 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the mos1 device in RFDE, refer to MOSFET_NMOS, MOSFET_PMOS (Nonlinear MOSFETs, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos1 Instance Parameters Spectre ADSsim Comments w Width l Length as As ad Ad ps Ps pd Pd nrd Nrd nrs Nrs region Region off -> 0 triode -> 1 sat -> 3 others-> (ignored) nqsmod Nqsmod trise Trise Table 3-43 shows the supported mos1 model parameter mapping. The Spectre mos1 model is mapped to the ADSsim MOSFET model with Idsmod=1 (LEVEL1_Model). For more information on the mos1 model in RFDE, refer to LEVEL1_Model (MOSFET Level-1Model) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos1 Model Parameters Spectre ADSsim Comments type NMOS & PMOS type=n-> NMOS=yes PMOS=no type=p-> NMOS=no PMOS=yes vto Vto Supported Devices and Models 3-89

124 Compatible Devices and Models Table Supported mos1 Model Parameters Spectre ADSsim Comments kp Kp lambda Lambda phi Phi gamma Gamma uo Uo vmax Vmax theta Theta nsub Nsub nss Nss nfs Nfs tpg Tpg ld Ld tox Tox ai0 Ai0 lai0 Lai0 wai0 Wai0 bi0 Bi0 lbi0 Lbi0 wbi0 Wbi0 cgso Cgso cgdo Cgdo capmod Capmod spectre ADS none --> 0 (no) meyer --> 3 (qmeyer) yang --> 1 (meyer_ward) bsim --> 2 (smooth) xpart Xpart xqc Xpart rs Rs rd Rd rss Rss rdd Rdd rsh Rsh rsc Rsc rdc Rdc minr Minr 3-90 Supported Devices and Models

125 Table Supported mos1 Model Parameters Spectre ADSsim Comments ldif hdif lgcs lgcd sc js is n imelt cbs cbd cj mj pb fc cjsw mjsw pbsw imax bvj vbox tnom trise ute tlev tlevc eg gap1 gap2 trs trd xti pta ptp cta Ldif Hdif Lgcs Lgcd Sc Js Is N Imelt Cbs Cbd Cj Mj Pb Fc Cjsw Mjsw Pbsw Imax wbvsub wbvg Tnom Trise Ute Tlev Tlevc Eg Gap1 Gap2 Trs Trd Xti Pta Ptp Cta Supported Devices and Models 3-91

126 Compatible Devices and Models Table Supported mos1 Model Parameters Spectre ADSsim Comments ctp w l as ad ps pd nrd nrs noisemod kf af ef wmax wmin lmax lmin idsmod Ctp W L As Ad Ps Pd Nrd Nrs Noimod Kf Af Ef Wmax Wmin Lmax Lmin Idsmod Table 3-44 shows the supported mos1 model DC operating point parameter mapping. The Spectre mos1 model is mapped to the ADSsim MOSFET model. Table Supported mos1 Model DC Operating Point Parameters Spectre cbd cbg cbs cdd cdg cds cgd cgg cgs cjd cjs ADSsim dqbdvdb dqbdvgb dqbdvsb dqddvdb dqddvgb dqddvsb dqgdvdb dqgdvgb dqgdvsb capbd capbs 3-92 Supported Devices and Models

127 Table Supported mos1 Model DC Operating Point Parameters Spectre gds gm gmbs i1 i3 i4 ibulk id is lv10 lv9 lx1 lx18 lx19 lx2 lx20 lx21 lx22 lx23 lx28 lx29 lx3 lx32 lx33 lx34 lx7 lx8 lx9 pwr vbs vds vdsat vgs vth ADSsim gds gm gmb id is ib ib id is vdsat vth vbs dqgdvgb dqgdvdb vgs dqgdvsb dqbdvgb dqbdvdb dqbdvsb capbs capbd vds dqddvgb dqddvdb dqddvsb gm gds gmb power vbs vds vdsat vgs vth Supported Devices and Models 3-93

128 Compatible Devices and Models MOS2 Table 3-45 shows the supported mos2 instance parameter mapping. The Spectre mos2 instance is mapped to the ADSsim mos2 instance. For more information on the mos2 model, refer to MOS Level-2 Model (mos2) in Chapter 15 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the mos2 device in RFDE, refer to MOSFET_NMOS, MOSFET_PMOS (Nonlinear MOSFETs, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos2 Instance Parameters Spectre ADSsim Comments w Width l Length as As ad Ad ps Ps pd Pd nrd Nrd nrs Nrs region Region off -> 0 triode -> 1 sat -> 3 others-> (ignored) trise Trise Table 3-46 shows the supported mos2 model parameter mapping. The Spectre mos2 model is mapped to the ADSsim MOSFET model with Idsmod=2 (LEVEL2_Model). For more information on the mos2 model in RFDE, refer to LEVEL2_Model (MOSFET Level-2 Model) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos2 Model Parameters Spectre ADSsim Comments type NMOS & PMOS type=n-> NMOS=yes PMOS=no type=p-> NMOS=no PMOS=yes vto kp Vto KP 3-94 Supported Devices and Models

129 Table Supported mos2 Model Parameters Spectre ADSsim Comments lambda Lambda phi Phi gamma Gamma uo Uo vmax Vmax ucrit Ucrit uexp Uexp neff Neff delta Delta nsub Nsub nss Nss nfs Nfs tpg Tpg tox Tox ld Ld xl Xl xw Xw xj Xj ai0 Ai0 lai0 Lai0 wai0 Wai0 bi0 Bi0 lbi0 Lbi0 wbi0 Wbi0 cgso Cgso cgdo Cgdo cgbo Cgbo capmod Capmod spectre ADS none --> 0 (no) meyer --> 3 (qmeyer) yang --> 1 (meyer_ward) bsim --> 2 (smooth) xpart Xpart xqc Xqc rs Rs rd Rd Supported Devices and Models 3-95

130 Compatible Devices and Models Table Supported mos2 Model Parameters Spectre ADSsim Comments rsh rsc rdc minr ldif hdif lgcs lgcd sc js is n imelt cbs cbd cj mj pb fc cjsw mjsw pbsw imax vbox tnom trise ute tlev tlevc eg gap1 gap2 trs trd xti Rsh Rsc Rdc Minr Ldif Hdif Lgcs Lgcd Sc Js Is N Imelt Cbs Cbd Cj Mj Pb Fc Cjsw Mjsw Pbsw Imax wbvg Tnom Trise Ute Tlev Tlevc Eg Gap1 Gap2 Trs Trd Xti 3-96 Supported Devices and Models

131 Table Supported mos2 Model Parameters Spectre ADSsim Comments pta ptp cta ctp w l as ad ps pd nrd nrs noisemod kf af ef wmax wmin lmax lmin Pta Ptp Cta Ctp W L As Ad Ps Pd Nrd Nrs Noimod Kf Af Ef Wmax Wmin Lmax Lmin Table 3-47 shows the supported mos2 model DC operating point parameter mapping. The Spectre mos2 model is mapped to the ADSsim MOSFET model. Table Supported mos2 Model DC Operating Point Parameters Spectre cbd cbg cbs cdd cdg cds cgd cgg cgs ADSsim dqbdvdb dqbdvgb dqbdvsb dqddvdb dqddvgb dqddvsb dqgdvdb dqgdvgb dqgdvsb Supported Devices and Models 3-97

132 Compatible Devices and Models Table Supported mos2 Model DC Operating Point Parameters Spectre cjd cjs gds gm gmbs i1 i3 i4 ibulk id is lv10 lv9 lx1 lx18 lx19 lx2 lx20 lx21 lx22 lx23 lx28 lx29 lx3 lx32 lx33 lx34 lx7 lx8 lx9 pwr vbs vds vdsat ADSsim capbd capbs gds gm gmb id is ib ib id is vdsat vth vbs dqgdvgb dqgdvdb vgs dqgdvsb dqbdvgb dqbdvdb dqbdvsb capbs capbd vds dqddvgb dqddvdb dqddvsb gm gds gmb power vbs vds vdsat 3-98 Supported Devices and Models

133 Table Supported mos2 Model DC Operating Point Parameters Spectre vgs vth ADSsim vgs vth Supported Devices and Models 3-99

134 Compatible Devices and Models MOS3 Table 3-48 shows the supported mos3 instance parameter mapping. The Spectre mos3 instance is mapped to the ADSsim mos3 instance. For more information on the mos3 model, refer to MOS Level-3 Model (mos3) in Chapter 16 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the mos3 device in RFDE, refer to MOSFET_NMOS, MOSFET_PMOS (Nonlinear MOSFETs, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos3 Instance Parameters Spectre ADSsim Comments w Width l Length as As ad Ad ps Ps pd Pd nrd Nrd nrs Nrs region Region off -> 0 triode -> 1 sat -> 3 others-> (ignored) trise Trise Table 3-49 shows the supported mos3 model parameter mapping. The Spectre mos3 model is mapped to the ADSsim MOSFET model with Idsmod=3 (LEVEL3_Model). For more information on the mos3 model in RFDE, refer to LEVEL3_Model (MOSFET Level-3 Model) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos3 Model Parameters Spectre ADSsim Comments type NMOS & PMOS type=n-> NMOS=yes PMOS=no type=p-> NMOS=no PMOS=yes vto kp Vto Kp Supported Devices and Models

135 Table Supported mos3 Model Parameters Spectre ADSsim Comments theta Theta phi Phi gamma Gamma uo Uo vmax Vmax eta Eta kappa Kappa delta Delta nsub Nsub nss Nss nfs Nfs tpg Tpg tox Tox ld Ld xl Xl xw Xw xj Xj ai0 Ai0 lai0 Lai0 wai0 Wai0 bi0 Bi0 lbi0 Lbi0 wbi0 Wbi0 cgso Cgso cgdo Cgdo cgbo Cgbo capmod Capmod spectre ADS none --> 0 (no) meyer --> 3 (qmeyer) yang --> 1 (meyer_ward) bsim --> 2 (smooth) xpart Xpart xqc Xqc rs Rs rd Rd rsh Rsh Supported Devices and Models 3-101

136 Compatible Devices and Models Table Supported mos3 Model Parameters Spectre ADSsim Comments rsc rdc ldif hdif lgcs lgcd sc js is n imelt cbs cbd cj mj pb fc cjsw mjsw pbsw imax vbox tnom trise ute tlev tlevc eg gap1 gap2 trs trd xti pta ptp Rsc Rdc Ldif Hdif Lgcs Lgcd Sc Js Is N Imelt Cbs Cbd Cj Mj Pb Fc Cjsw Mjsw Pbsw Imax wbvg Tnom Trise Ute Tlev Tlevc Eg Gap1 Gap2 Trs Trd Xti Pta Ptp Supported Devices and Models

137 Table Supported mos3 Model Parameters Spectre ADSsim Comments cta ctp w l as ad ps pd nrd nrs noisemod kf af ef wmax wmin lmax lmin idsmod Cta Ctp W L As Ad Ps Pd Nrd Nrs Noimod Kf Af Ef Wmax Wmin Lmax Lmin Idsmod Table 3-50 shows the supported mos3 model DC operating point parameter mapping. The Spectre mos3 model is mapped to the ADSsim MOSFET model. Table Supported mos3 Model DC Operating Point Parameters Spectre cbd cbg cbs cdd cdg cds cgd cgg cgs cjd ADSsim dqbdvdb dqbdvgb dqbdvsb dqddvdb dqddvgb dqddvsb dqgdvdb dqgdvgb dqgdvsb capbd Supported Devices and Models 3-103

138 Compatible Devices and Models Table Supported mos3 Model DC Operating Point Parameters Spectre cjs gds gm gmbs i1 i3 i4 ibulk id is lv10 lv9 lx1 lx18 lx19 lx2 lx20 lx21 lx22 lx23 lx28 lx29 lx3 lx32 lx33 lx34 lx7 lx8 lx9 pwr vbs vds vdsat vgs vth ADSsim capbs gds gm gmb id is ib ib id is vdsat vth vbs dqgdvgb dqgdvdb vgs dqgdvsb dqbdvgb dqbdvdb dqbdvsb capbs capbd vds dqddvgb dqddvdb dqddvsb gm gds gmb power vbs vds vdsat vgs vth Supported Devices and Models

139 MOS902 Table 3-51 shows the supported mos902 instance parameter mapping. The Spectre mos902 instance is mapped to the ADSsim mos902 instance. For more information on the mos902 model, refer to Philips Models > Compact MOS-Transistor Model (mos902) in Chapter 11 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the mos902 device in RFDE, refer to MM9_NMOS, MM9_PMOS (Philips MOS Model 9, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos902 Instance Parameters Spectre ADSsim Comments l Length w Width mult Mult area Mult region Region off -> 0 triode -> 1 sat -> 3 others-> (ignored) Table 3-52 shows the supported mos902 model parameter mapping. The Spectre mos902 model is mapped to the ADSsim MOS9 model. For more information on the mos902 model in RFDE, refer to MOS_Model9_Single (Philips MOS Model 9, Single Device) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos902 Model Parameters Spectre ADSsim Comments type NMOS & PMOS type=n-> NMOS=yes PMOS=no type=p-> NMOS=no PMOS=yes ler wer lvar lap wvar wot Ler Wer Lvar Lap Wvar Wot Supported Devices and Models 3-105

140 Compatible Devices and Models Table Supported mos902 Model Parameters Spectre ADSsim Comments wdog vtor slvto stvto sl2vto swvto kor slko swko kr slk swk phibr vsbxr slvsbx swvsbx betsq etabet the1r stthe1r slthe1r stlthe1 swthe1 fthe1 the2r stthe2r slthe2r stlthe2 swthe2 the3r stthe3r slthe3r stlthe3 swthe3 gam1r Wdog Vtor Slvto Stvto Sl2vto Swvto Kor Slko Swko Kr Slk Swk Phibr Vsbxr Slvsbx Swvsbx Betsq Etabet The1r Stthe1r Slthe1r Stlthe1 Swthe1 Fthe1 The2r Stthe2r Slthe2r Stlthe2 Swthe2 The3r Stthe3r Slthe3r Stlthe3 Swthe3 Gam1r Supported Devices and Models

141 Table Supported mos902 Model Parameters Spectre ADSsim Comments slgam1 swgam1 etadsr alpr slalp swalp vpr gamoor slgamoo etagamr mor stmo slmo etamr zet1r etazet slzet1 vsbtr slvsbt a1r sta1 Sla1 swa1 a2r sla2 swa2 a3r sla3 swa3 tox col ntr nfr tr tref Slgam1 Swgam1 Etadsr Alpr Slalp Swalp Vpr Gamoor Slgamoo Etagamr Mor Stmo Slmo Etamr Zet1r Etazet Slzet1 Vsbtr Slvsbt A1r Sta1 Sla1 Swa1 A2r Sla2 Swa2 A3r Sla3 Swa3 Tox Col Ntr Nfr Tr Tr Supported Devices and Models 3-107

142 Compatible Devices and Models Table Supported mos902 Model Parameters Spectre ADSsim Comments tnom Tnom trise Trise the1r The1r dta Trise alias for trise Table 3-53 shows the supported mos902 model DC operating point parameter mapping. The Spectre mos902 model is mapped to the ADSsim MOS9 model. Table Supported mos902 Model DC Operating Point Parameters Spectre cbb cbd cbg cdb cdd cdg cgb cgd cgg csb csd csg gds gm gmb ibe ids ige ise pwr vds vgs vsb ADSsim cb_sb cb_ds cb_gs cd_sb cd_ds cd_gs cg_sb cg_ds cg_gs cs_sb cs_ds cs_gs gid_ds gid_gs gid_sb ib id ig is power vds vgs vbs Supported Devices and Models

143 MOS903 Table 3-54 shows the supported mos903 instance parameter mapping. The Spectre mos903 instance is mapped to the ADSsim mos903 instance. For more information on the mos903 model, refer to Philips Models > Compact MOS-Transistor Model (mos903) in Chapter 11 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the mos903 device in RFDE, refer to MM9_NMOS, MM9_PMOS (Philips MOS Model 9, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos903 Instance Parameters Spectre ADSsim Comments l Length w Width mult Mult area Mult region Region off -> 0 triode -> 1 sat -> 3 others-> (ignored) Table 3-55 shows the supported mos903 model parameter mapping. The Spectre mos903 model is mapped to the ADSsim MOS9 model. For more information on the mos903 model in RFDE, refer to MOS_Model9_Single (Philips MOS Model 9, Single Device) in Chapter 5 of the Nonlinear Devices documentation. Table Supported mos903 Model Parameters Spectre ADSsim Comments type NMOS & PMOS type=n-> NMOS=yes PMOS=no type=p-> NMOS=no PMOS=yes ler wer lvar lap wvar wot Ler Wer Lvar Lap Wvar Wot Supported Devices and Models 3-109

144 Compatible Devices and Models Table Supported mos903 Model Parameters Spectre ADSsim Comments wdog vtor slvto stvto sl2vto swvto kor slko swko kr slk swk phibr vsbxr slvsbx swvsbx betsq etabet the1r stthe1r slthe1r stlthe1 swthe1 fthe1 the2r stthe2r slthe2r stlthe2 swthe2 the3r stthe3r slthe3r stlthe3 swthe3 gam1r Wdog Vtor Slvto Stvto Sl2vto Swvto Kor Slko Swko Kr Slk Swk Phibr Vsbxr Slvsbx Swvsbx Betsq Etabet The1r Stthe1r Slthe1r Stlthe1 Swthe1 Fthe1 The2r Stthe2r Slthe2r Stlthe2 Swthe2 The3r Stthe3r Slthe3r Stlthe3 Swthe3 Gam1r Supported Devices and Models

145 Table Supported mos903 Model Parameters Spectre ADSsim Comments slgam1 swgam1 etadsr alpr slalp swalp vpr gamoor slgamoo etagamr mor stmo slmo etamr zet1r etazet slzet1 vsbtr slvsbt a1r sta1 Sla1 swa1 a2r sla2 swa2 a3r sla3 swa3 tox col ntr nfr nfmod nfar Slgam1 Swgam1 Etadsr Alpr Slalp Swalp Vpr Gamoor Slgamoo Etagamr Mor Stmo Slmo Etamr Zet1r Etazet Slzet1 Vsbtr Slvsbt A1r Sta1 Sla1 Swa1 A2r Sla2 Swa2 A3r Sla3 Swa3 Tox Col Ntr Nfr Nfmod Nfar Supported Devices and Models 3-111

146 Compatible Devices and Models Table Supported mos903 Model Parameters Spectre ADSsim Comments nfbr Nfbr nfcr Nfcr tr Tr tref Tr tnom Tr trise Trise dta Trise alias for trise Table 3-56 shows the supported mos903 model DC operating point parameter mapping. The Spectre mos903 model is mapped to the ADSsim MOS9 model. Table Supported mos903 Model DC Operating Point Parameters Spectre cbb cbd cbg cdb cdd cdg cgb cgd cgg csb csd csg gds gm gmb ibe ids ige ise pwr vds ADSsim cb_sb cb_ds cb_gs cd_sb cd_ds cd_gs cg_sb cg_ds cg_gs cs_sb cs_ds cs_gs gid_ds gid_gs gid_sb ib id ig is power vds Supported Devices and Models

147 Table Supported mos903 Model DC Operating Point Parameters Spectre vgs vsb ADSsim vgs vbs Supported Devices and Models 3-113

148 Compatible Devices and Models JFET Table 3-57 shows the supported jfet instance parameter mapping. The Spectre jfet instance is mapped to the ADSsim jfet instance. For more information on the JFET model, refer to JFET Model (jfet) in Chapter 10 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version For more information on the JFET device in RFDE, refer to JFET_NFET, JFET_PFET (Nonlinear Junction FETs, P-Channel, N-Channel) in Chapter 4 of the Nonlinear Devices documentation. Table Supported JFET Instance Parameters Spectre ADSsim Comments area Area trise Trise region Region off -> 0 triode -> 1 sat -> 3 others-> (ignored) Table 3-58 shows the supported jfet model parameter mapping. The Spectre jfet model is mapped to the ADSsim JFET model. For more information on the JFET model in RFDE, refer to JFET_Model (Junction FET Model) in Chapter 4 of the Nonlinear Devices documentation. Table Supported JFET Model Parameters Spectre ADSsim Comments type NFET & PFET type=n -> NFET=yes PFET=no type=p -> NFET=no PFET=yes vto beta lambda rd rs is n imelt cgs Vto Beta Lambda Rd Rs Is N Imelt Cgs Supported Devices and Models

149 Table Supported JFET Model Parameters Spectre ADSsim Comments cgd pb fc tnom trise xti imax bvj kf af Cgd Pb Fc Tnom Trise Xti Imax wbvgd Kf Af Table 3-59 shows the supported jfet model DC operating point parameter mapping. The Spectre jfet model is mapped to the ADSsim JFET model. Table Supported JFET Model DC Operating Point Parameters Spectre cgd cgs gds gm ig pwr vds vgs ADSsim cgd cgs gds gm ig power vds vgs Sources RFDE users can simulate polynomial and linear controlled sources in Spectre-Compatible PDKs. Agilent Technologies supports both linear and polynomial types of current and voltage controlled, current and voltage sources. Polynomial controlled sources (e.g. pvcvs or pcccs) can support multiple controlling inputs as long as the inputs are of the same type (i.e. all voltage or all current controllers); whereas, linear controlled sources are strictly for single input systems. Sources 3-115

150 Compatible Devices and Models Supported Sources Table 3-60 shows a list of currently supported sources for Spectre-Compatible PDKs. Table Supported Sources Source Type Linear Polynomial Independent Current Source (isource) N/A N/A Independent Voltage Source (vsource) N/A N/A Current Controlled Current Source cccs pcccs Current Controlled Voltage Source ccvs pccvs Voltage Controlled Current Source vccs pvccs Voltage Controlled Voltage Source vcvs pvcvs For more information on individual current sources, refer to Current Sources in Chapter 1 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version Table 3-61 shows the supported isource DC operating point parameter mapping. The Spectre isource model is mapped to the ADSsim I_Source model. Table isource DC Operating Point Parameter Mapping Spectre i pwr v ADSsim is power vs For information on current sources in RFDE, refer to the Sources documentation. For more information on individual voltage sources, refer to Voltage Sources in Chapter 1 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version Table 3-62 shows the supported vsource DC operating point parameter mapping. The Spectre vsource model is mapped to the ADSsim V_Source model. Table vsource DC Operating Point Parameter Mapping Spectre i ADSsim is Sources

151 Table vsource DC Operating Point Parameter Mapping Spectre pwr v ADSsim power vs For information on voltage sources in RFDE, refer to the Sources documentation. Behavioral Source (bsource) The behavioral source or bsource enables you to model a resistor, inductor, capacitor, voltage or current source as a behavioral component. This section describes the RFDE, ADSsim implementation of the bsource. Most of the information in this section is in addition to the Spectre documentation for bsource. The purpose of this section is to enable you to understand any potential differences between ADSsim and Spectre implementations. For more information, refer to the Behavioral Source Use Model (bsource) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Bsource parameters ADSsim supports all of the bsource parameters listed in the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version , June The only difference is in the capitalization of the parameter isnoisy. Both ADSsim and Spectre accept the parameter isnoisy. Except for the tnom parameter, all default values for ADSsim are consistent with Spectre. Table Behavioral Source Parameters Parameter Expression Description Default Type r g l phi c q simple_expr type of bsource component v i generic_expr tnom value nominal temperature Options/25 degc trise value temperature rise above circuit ambient 0 tc1 value linear temperature coefficient 0 tc2 value quadratic temperature coefficient 0 max_val value maximum value of bsource expression min_val value minimum value of bsource expression isnoisy flag - yes/no v i r g types - flag to generate noise yes Sources 3-117

152 Compatible Devices and Models Table Behavioral Source Parameters Parameter Expression Description Default white_noise simple_expr v i types - white noise expression flicker_noise simple_expr v i types - flicker noise expression kf value r g types - flicker noise coefficient 0 af value r g types - flicker noise exponent 2 fexp value v i r g types - flicker noise frequency exponent 1 m value multiplicity factor 1 Support for the temp Parameter Spectre supports an undocumented temp parameter for the bsource component. ADSsim also supports this parameter for its bsource equivalent. If the parameter is not specified, then the global (ambient) temperature, as specified by the RFDE Options parameter Temp (default is 27 degrees Celcius), is used. Interpretation of the trise Parameter The standard behavior for ADSsim devices is that the parameter Trise takes effect only if the device parameter Temp is not specified. Then, the actual device temperature is the global circuit temperature (as defined by Options, or 25 C by default) modified by the value of Trise. Otherwise, if the device parameter Temp is specified, Trise is ignored even if a non-zero value is specified. This behavior is different for bsource. Similarly to Spectre, the bsource parameter trise is always used to modify the device temperature, regardless of whether the reference temperature is defined by the undocumented bsource parameter temp or by the global circuit temperature. Bsource Connection Nodes If the bsource behavioral expression contains a reference to a voltage probe v(ni,nj), then the list of bsource connection nodes may be expanded by additional nodes. For example, inst_name (n1 n2 [n3 n4...]) bsource type = expression_with_v(n3,n4) However, simulation results in Spectre are expected to be the same regardless of whether these additional connection nodes are present or not. This behavior is preserved in ADSsim Sources

153 Bsource Hierarchical Nodes The new Spectre front-end allows hierarchical nodes described by a relative path down from the current level of the hierarchy. These relative paths include the separator.. ADSsim does not support hierarchical nodes. This means that except for global nodes, both the connection nodes and the voltage probe nodes must be the nodes from the current subcircuit. Bsource Current Probes The new Spectre front-end allows any component to serve as a current probe. Similar to older versions of Spectre, ADSsim supports only a limited set of these components, basically all the components for which the current is calculated. These components include the ADSsim counterparts of the following Spectre components: vsource, ccvs, pccvs, vcvs, pvcvs, iprobe, inductor and three types of bsource: l, phi, v Limited Syntax for Referencing Current Probes The new Spectre front-end enables you to specify the pin of the current probe component in the form: i("component:index") where index can be either the pin name or a corresponding numeric. Also, in the latest releases of Spectre, the quotes are optional. In ADSsim, similar to the older versions of Spectre, the quotes are required and the index can only assume the value of 0 (zero, default in Spectre), which corresponds to the positive direction of the current through the component. It is recommended to not use the index at all, that is, use the following syntax only: i("component") If an index is specified, even it is set to zero, a warning message will be issued. Bsource Current Probes Across the Circuit Hierarchy The ADSsim bsource implementation does allow current probes from outside of the current subcircuit. However, this may potentially lead to inconsistent results between Spectre and ADSsim. This is because ADSsim treats the component path as Sources 3-119

154 Compatible Devices and Models relative down from the current level of the hierarchy, while Spectre assumes that the component path is an absolute path from the top level circuit. max_val and min_val Clipping If both max_val and min_val bsource parameters are specified, then min_val is applied first. This means if the specified value of min_val is greater than max_val, the resulting expression value will settle at the value of max_val. Temperature Scaling As for Spectre, ADSsim temperature scaling is applied after the max_val and min_val clipping, if any is requested. This means that the actual final value may fall outside of the [min_val, max_val] range. Differentiation and Integration operators A differentiation operator ddt(simple_expr) and the integration operator idt(simple_expr) are allowed only within the generic bsource expression defining either the v or i type of the bsource. They are not allowed anywhere outside of the bsource component. Nested operators are not allowed. The Scope of the Integration Operators Similarly to the Spectre bsource, ADSsim bsource accepts only one field in the integration operator idt(simple_expr), that is the simple_expr to be integrated. The general Verilog-A syntax for the operator allows other fields, namely the initial condition, assert, nature and abstol. None of these are currently supported in bsource. User-defined Functions In general, ADSsim allows Spectre user-defined functions. However, their definition cannot include the probe functions v() and i(). The probe functions can only be used as arguments when the user-defined functions are actually used inside of bsource expressions. For example, real myfunc( real x ) { return abs(x); }.. mybs1 net1 net2 bsource r=myfunc( v(net1,net2) ) Sources

155 Spectre behavioral resistor, inductor and capacitor A resistor, inductor, or capacitor in Spectre with main parameter r, l, and c, respectively, may be defined using behavioral expressions as shown here: inst_name (n1 n2) resistor r = simple_expr parameters = expression_values inst_name (n1 n2) inductor l = simple_expr parameters = expression_values inst_name (n1 n2) capacitor c = simple_expr parameters = expression_values If any of these components are defined using a behavioral expression, the ADSsim simulator, similar to Spectre, produces an equivalent bsource component: inst_name (n1 n2) bsource r l c = simple_expr parameters = expression_values For more information on the bsource model in Spectre, refer to Behavior Source (bsource) in Chapter 1 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version Cadence Provided Libraries Cadence Design Systems provides reference libraries that contain basic design objects that are available to use in your designs. ahdllib The ahdllib contains behavioral definitions for a large number of analog and digital primitives. These cells have not all been simulated in RF Design Environment. However, RFDE can utilize veriloga definitions, provided the veriloga license is available. The crossing_detector is not supported in RFDE. This feature has an ahdl view, but no veriloga view. All other cells have a veriloga definition that can be utilized with RFDE. Note Digital components simulated in frequency domain simulations may cause issues with convergence, or may be inaccurate if a suitable number of harmonics is not used in the simulation. Cadence Provided Libraries 3-121

156 Compatible Devices and Models analoglib The Cadence Analog Library (analoglib) is a standard component library provided within the Cadence Analog Design Environment. The library contains basic components such as resistors, capacitors, and transistors that can be used in building more complex analog blocks such as amplifiers. Each component in analoglib can be supported by different simulators such as the ADSsim or Spectre simulators. Table 3-64 shows a list of components that are included in analoglib. If a component includes a Y in the Spectre-Compatible [Y/N]? column, then RFDE will be able to netlist and simulate the spectre view of this component. However, if a component includes an N in the Spectre-Compatible [Y/N]? column, then RFDE cannot netlist and simulate the spectre view. For more information on Spectre-Compatiblity for each individual component in analoglib, refer to Viewing Effective RFDE Library Compatibility for Library Cells on page 2-4. Component Name bcs bvs cap cccs Table analoglib Component Support Spectre- Compatible (Y/N)? N N Y Y Comments cccs4 n/a No spectre view for this component. The ads view is only available in the Agilent supplied analoglib. ccvs Y ccvs4 n/a No spectre view for this component. The ads view is only available in the Agilent supplied analoglib. cmdmprobe N core N corefragment N delay Y diode Y dummy N fourier N fourier2ch N gnd Y gnda Y Cadence Provided Libraries

157 Component Name Table analoglib Component Support Spectre- Compatible (Y/N)? Comments gndd Y iam N ibis_buffer N idc Y ideal_balun Y iexp Y ind Y iopamp N iprobe Y ipulse Y ipwl Y ipwlf N isffm N isin Y isource [type] Y* * If type = piecewise linear file, it is not Spectre-Compatible ixfmr N mind Y MOS_a2d N MOS_d2a N msline N mtline N n1port Y n2port Y n3port Y n4port Y nbsim Y nbsim4 Y njfet Y nmes Y nmes4 N nmos Y nmos4 Y nodequantity N Cadence Provided Libraries 3-123

158 Compatible Devices and Models Component Name Table analoglib Component Support Spectre- Compatible (Y/N)? Comments noise N npn Y nport Y nsoi N pbsim Y pbsim4 Y pcapacitor Y pcccs Y pccvs Y pdc Y pdiode Y pexp Y pgen N phyres N pinductor Y pjfet Y pmind Y pmos Y pmos4 Y pmsin N pnp Y port [type] Y* * If type = piecewise linear file, it is not Spectre-Compatible powersupply N pppulse Y ppwl Y ppwlf N presistor Y psin Y psoi N pvccs Y pvccs2 Y pvccs3 Y pvccsp N Cadence Provided Libraries

159 Cadence Provided Libraries pvcvs Y pvcvs2 Y pvcvs3 Y pvcvsp N rcwireload N res Y scasubckt N scccs N sccvs N schottky Y scr N sp1tswitch N sp2tswitch N sp3tswitch N sp4tswitch N svccs N svcvs N switch N tline N TTL_a2d N TTL_d2a N u1wire N u2wire N u3wire N u4wire N u5wire N usernpn N userpnp N vam N vcc Y vcca Y vccap N vccd Y vccs Y Table analoglib Component Support Component Name Spectre- Compatible (Y/N)? Comments

160 Compatible Devices and Models Component Name Table analoglib Component Support Spectre- Compatible (Y/N)? Comments vccsp N vcres N vcvs Y vcvsp Y vdc Y vdd Y vdda Y vddd Y vee Y veea Y veed Y vexp Y vpulse Y vpwl Y vpwlf N vsffm N vsin Y vsource [type] Y* * If type = piecewise linear file, it is not Spectre-Compatible vss Y vssa Y vssd Y winding N xfmr Y zcccs Y zccvs Y zener Y zvccs Y zvcvs Y For more information on the Cadence analoglib, refer to the Cadence Analog Library Reference Guide Cadence Provided Libraries

161 basic The Cadence basic library (basic) contains schematic and symbol views of various connectors, pins, and supplies. The Cadence basic library is now 100% compatible with RFDE; therefore, an RFDE provided basic library is no longer required. rflib The Cadence RF Library (rflib) contains behavioral model components. These behavioral components are based on Verilog-A model files. The Cadence rflib library components that use veriloga models are compatible with RFDE; however, components that use ahdl are not compatible with RFDE. Cadence Provided Libraries 3-127

162 Compatible Devices and Models Cadence Provided Libraries

163 Chapter 4: Compatible Features This chapter provides a detailed list of the Spectre-Compatible features that are supported by the ADS Analog/RF simulator (ADSsim) for use with Spectre-Compatible PDKs. The chapter highlights compatible features such as inline and nested sub-circuits, process mismatch, structural if-else, sectional includes, Boolean/algebraic expressions, Verilog-A support, etc. The chapter provides references to additional information in the RF Design Environment and/or Cadence documentation set where appropriate. Expressions For information on simulator functions in RFDE, refer to the Simulator Expressions documentation. For information on post processing functions in RFDE, refer to the Measurement Expressions documentation. The tables provided in the sections below include various Spectre expression capabilities and their compatible ADSsim equivalents. Note In Spectre-Compatibility mode, only the Spectre expression capabilities are valid. In native RFDE mode, only the ADSsim expression capabilities are valid. For information on expressions in Spectre, refer to Expressions (expressions) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Operators The operators listed in Table 4-1 are supported by the ADSsim simulator unless otherwise noted and are listed in order of decreasing precedence. Table 4-1. Arithmetic and Boolean Operator Precedence Spectre Operator Unary +, Unary - Spectre Symbol(s) To the power of ** ** ^ + - ADSsim Symbol(s) + - Value Value of the operand, negative of the operand First operand to be raised to the power of the second operand Expressions 4-1

164 Compatible Features Table 4-1. Arithmetic and Boolean Operator Precedence (continued) Spectre Operator Multiply, Divide Binary Plus, Binary Minus * / + - Shift << >> Relational < <= > >= Equality == Spectre Symbol(s) ADSsim Symbol(s) * / + - < <= > >= == = equals Value Product, quotient of the operands Sum, difference of the operands. First operand shift by the number of bits specified by the second operand; first operand shifted right by the number of bits specified by the second operand. Less than, less than or equal to, greater than, greater than or equal to True if the operands are equal; true if the operands are not equal.!=!= notequals Bitwise AND & Bitwise AND (of integer operands) Bitwise Exclusive NOR ~^ (or ^~) Bitwise exclusive NOR (of integer operands) Bitwise OR Bitwise OR (of integer operands) Logical AND && && and Logical OR or True only if both operands are true. True if either operand is true. Conditional selection (cond)? x : y (cond)? x : y Returns x if cond is true, y if not; where x and y are expressions. ( ) Function call [ ] Indexer, array :: Sequence operator wildcard For more information, refer to the section on Expressions in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See also Expressions (expressions) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Expressions

165 Algebraic and Trigonometric Functions The ADSsim simulator in RF Design Environment supports all Spectre built-in algebraic and trigonometric simulator functions. There are only two functions whose names in ADSsim are different than in Spectre. The log(x) function in Spectre is equivalent to ln(x) in ADSsim The atan(x) function in Spectre is equivalent to arctan(x) in ADSsim Table 4-2 displays a list of the algebraic and trigonometric simulator functions. Operands for the trigonometric and hyperbolic functions should be specified in radians. Spectre Function Table 4-2. Built-in Algebraic and Trigonometric Simulator Functions ADSsim Function Function Description Function Domain log(x) ln(x) Natural logarithm X > 0 log10(x) log(x), log10(x) Decimal logarithm X > 0 exp(x) exp(x) Exponential x < 80 in Spectre, default to 60 and can be user specified in ADSsim sqrt(x) sqrt(x) Square root x > 0 min(x,y) min(x,y) Minimum value All x, all y max(x,y) max(x,y) Maximum value All x, all y abs(x) abs(x) Absolute value All x pow(x,y) pow(x,y) x to the power of y All x, all y sin(x) sin(x) Sine All x cos(x) cos(x) Cosine All x tan(x) tan(x) Tangent All x, except x=n*(pi/2), where n odd asin(x) asin(x) Arc-sine -1 <= x <= 1 acos(x) acos(x) Arc-cosine -1 <= x <= 1 atan(x) arctan(x) Arc-tangent All x atan2(x,y) atan2(x,y) Arc-tangent of x/y All x, all y hypot(x,y) hypot(x,y) sqrt(x*x+y*y) All x, all y sinh(x) sinh(x) Hyperbolic sine All x cosh(x) cosh(x) Hyperbolic cosine All x tanh(x) tanh(x) Hyperbolic tangent All x asinh(x) asinh(x) Arc_hyperbolic sine All x acosh(x) acosh(x) Arc_hyperbolic cosine x atanh(x) atanh(x) Arc_hyperbolic tangent -1 <= x <= 1 Expressions 4-3

166 Compatible Features Spectre Function Table 4-2. Built-in Algebraic and Trigonometric Simulator Functions ADSsim Function Function Description Function Domain int(x) int(x) Integer value of x All x ceil(x) ceil(x) Smallest integer >= x All x floor(x) floor(x) Largest integer <= x All x fmod(x,y) fmod(x,y) Floating-point modulus All x, all y, except y=0 For more information, refer to the section on Expressions in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See also Expressions (expressions) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Built-in Constants The Spectre netlist language contains built-in mathematical and physical constants. All Spectre built-constants are supported in RFDE. For more information on built-in constants, refer to the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See also Built-in Mathematical and Physical Constants (constants) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Subcircuits Subcircuits are used to describe the circuit hierarchy and to perform parameterized modeling. You can nest subcircuits, and a subcircuit definition can contain both instances and definitions of other subcircuits. For more information on subcircuits, refer to the section on Subcircuits in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Nested Subcircuits Subcircuit definitions can be nested, in which case the inner-most subcircuit definition can only be referenced from within the subcircuit in which it is defined. The nested subcircuit cannot be referenced from anywhere else. Nested subcircuits define the functional scope for all of the possible references contained inside of a subcircuit 4-4 Subcircuits

167 definition, for example, parameters, models, measurements, instances, sub-definitions, etc. The RFDE solution provides equivalent results to the Spectre behavior with regard to nested subcircuits. For more information, refer to the section on Subcircuits in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Inline Subcircuits An inline subcircuit is a special case where one of the instantiated devices or models within the subcircuit does not get its full hierarchical name but inherits the subcircuit call name. The inline subcircuit is called in the same manner as a regular subcircuit. RF Design Environment supports Spectre s inline subcircuit behavior. For more information, refer to the section on Inline Subcircuits in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Subcircuit Parameters Parameters can be declared on the first line of a subcircuit definition. As a result, their default values are specified. The default values can be modified when creating subcircuit instances. The value or a default value for a parameter can be a constant, expression, a reference to a previously defined parameter (note that parameters must be declared before they are used), or any combination of these. The subcircuit definition or subcircuit instance inherit parameters from their parent (enclosing subcircuit definition, or top-level definition). For more information on subcircuit parameters, refer to the section on Parameters Statement in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Subcircuits 4-5

168 Compatible Features Process Variation and Mismatch Process design kit users need to be able to run an ADSsim simulation in RF Design Environment and analyze a circuit that uses components from a Cadence PDK. Almost every process design kit includes the specifications for process and mismatch variations. These are used in Monte Carlo analysis to predict circuit performance due to process and/or mismatch variations. Support for Spectre s syntax has been added for process and mismatch variations. Process and mismatch variations are defined in the model files. Spectre s process and mismatch variations functionality can be activated through the following RFDE Monte Carlo user interface analysis options: Analysis Variations: Process Only Mismatch Only Process & Mismatch For more information, refer to the section on Monte Carlo Analysis in Chapter 6 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The statistics Statement The Spectre statistics control statement enables you to specify a batch-to-batch (process) and per-instance (mismatch) variations for netlist parameters. The statistics statement is supported in RF Design Environment. For more information on the Spectre statistics statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version Structural if-else The structural if-else statement can be used to conditionally instantiate other instance statements. RF Design Environment supports Spectre s structural if-else conditional instance. For more information, refer to Conditional Instances under the Binning section of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version See 4-6 Process Variation and Mismatch

169 also The Structural if-statement (if) in the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Sectional Includes RF Design Environment supports Spectre s sectional include statement in Spectre netlists. When the Spectre simulator reads the include statement in the netlist, the simulator locates the new file, reads it, and then resumes reading the netlist file. For more information, refer to the section on Library - Sectional Include (library) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Special Character Support Both the Spectre and ADS Analog/RF (ADSsim) simulators assign special meaning to certain characters and words. RF Design Environment manages these special characters and reserved words in names from Spectre netlists so that it can provide equivalent Spectre behavior in ADSsim. This helps to avoid any undesired simulation results. Note The dot, open parentheses, close parentheses, and pound characters in subcircuit, model, parameter, and node names in Spectre netlists are all mapped to the underscore ( _ ) character in the ADSsim simulator output files.. ( ) # all map to underscore ( _ ) When the ADSsim simulator comes across a name in Spectre that happens to be a reserved word in ADSsim, the Spectre name is mapped using the following formula: <Spectre_name> maps to _<Spectre_name>_ads For example, the Spectre name logrforce, which happens to be a reserved word in ADSsim, would be mapped to _logrforce_ads. Sectional Includes 4-7

170 Compatible Features Special character support should be considered when interpreting error messages. Error messages may include modified names. For a similar example, refer to Unsupported Parameters on Supported Devices on page 5-1. For more information on the ADSsim simulator reserved words, refer to Table 5-14 in Chapter 5 of the Using Circuit Simulators documentation. Verilog-A Support (ahdl_include) The Spectre ahdl_include statement is used to include Verilog-A modules in your netlist. You can access Verilog-A files in RF Design Environment from Spectre netlists. Agilent s Verilog-A compiler/interpreter is accessible from the RFDE Spectre parser. When the netlist is parsed, the Verilog-A filename is extracted and passed to the Verilog-A code. The Verilog-A code then manages all further operations. For more information on Verilog-A, refer to Using Verilog-A in RF Design Environment and the Verilog-A Reference Manual. See also Verilog-A Usage and Language Summary (veriloga) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Using Design Variables Design variables are netlisted in ads format only so all design variables in RFDE must use ads equation syntax only. If your design variables are setup to use Spectre equations, they must be modified to use ads equivalent equations in design variables in order for your design variables to netlist properly in RFDE. 4-8 Verilog-A Support (ahdl_include)

171 Chapter 5: Managing Unsupported Features This chapter provides information on identifying problems and known incompatible features, or features that are not supported for use in Spectre-Compatible PDKs. Many incompatible features are described in detail in the RFDE and/or Cadence documentation set; therefore, references to additional information in the RF Design Environment documentation and/or Cadence documentation are provided where appropriate. Identifying Unsupported Features This section includes information to help you identify and understand problems that you may encounter when attempting to use Agilent s Spectre-Compatible solution with unsupported features. Unsupported Parameters on Supported Devices Supported devices are listed under Supported Devices and Models on page 3-4. Each of the supported devices and models includes a list of supported parameters and their mapping. If your device or model parameter is not listed in the Supported Devices and Models section, the component or model should be considered unsupported. When you encounter an unsupported parameter in a device that is known to be supported, you will receive an error message. Error messages may initially be confusing due to aliasing and parameter mapping. For example, consider the message below: hpeesofsim (*) 2005A.day May (built: 05/25/05 21:46:44) Copyright Agilent Technologies, Warning detected by hpeesofsim during netlist flattening. parameter dtoxcv for mosfet model nmos25 is not currently supported. Warning detected by hpeesofsim during netlist flattening. parameter dtoxcv for mosfet model pmos25 is not currently supported. Warning: parameter va for BJT model npn is not currently supported. Warning: parameter va for BJT model pnp is not currently supported. Warning: parameter pbsw for Diode model I3.I9.R1.R1.polyhres. polyhreslw_diode is not currently supported Warning detected by hpeesofsim during netlist flattening Instance polyhreslw : Length is not a valid parameter for an instance of R. Ignoring it. Warning detected by hpeesofsim during netlist flattening. Instance polyhreslw : Identifying Unsupported Features 5-1

172 Managing Unsupported Features Width is not a valid parameter for an instance of R. Ignoring it. Error detected by hpeesofsim during netlist flattening. Undefined parameter trise used by I3.I9.R1.R1.Trise. Warning: parameter pbsw for Diode model I3.I9.R1.R0.polyhres.polyhreslw_diode is not currently supported. Flushing data (please wait)... Resource usage: Total stopwatch time: 0.45 seconds. hpeesofsim terminated due to an error. ds2psf--error: Cannot access file /users/johnqp/cadencegpdk/rfic217a/design/simulation/sim_g7vco/adssim/schematic/netlist/data.ds. Note that the Error detected by hpeesofsim during netlist flattening reports Undefined parameter trise used by I3.I9.R1.R1.Trise. You can use the information provided in the error message to work backwards and decipher the specific problem. In this case, you can see that the this is a resistor instance (R1) is using the Trise parameter. Because Trise uses initial capitalization, you can quickly identify this as an ADSsim parameter (Spectre parameters do not use initial capitalization). Using this information, you can return to the information on the Resistor on page 3-5 and use Table 3-2 (the resistor instance mapping table) to identify the equivalent Spectre parameter, trise in this case. Spectre s trise parameter maps to the RFDE equivalent Trise. Once you find the equivalent parameter that you are looking for, you can use the tools described in Generating Debugging Output on page 5-3. The error message above is fairly straight forward; however, some error messages can be difficult to decipher due to parameter aliasing. If a Spectre parameter is actually an alias for another parameter, the process of understanding the parameter mapping can quickly become less straightforward. Take the time you need to understand the mapping before proceeding to the next section. 5-2 Identifying Unsupported Features

173 Generating Debugging Output ADSsim provides a method for dumping the internal data structures that make up a circuit in a form that looks like an ADSsim netlist. This is a flattened (all subcircuits expanded, no hierarchy) version of the simulated netlist with all instances, flattened node numbers, and models. Instance and model parameters are printed with the numerical value that was used in the simulation; this provides a good way to determine how expressions that may be used to define model parameters are actually evaluated. The netlist is printed after DC simulation is finished, so some simulation controller must be present in the netlist. Insert the following line in the circuit netlist: Options DumpFile="dumpfile.txt" DumpLevel=288 DumpFile is the name of the file that will be created to hold the output. Any existing file is overwritten without warning. DumpLevel should be set to one of two values: DumpLevel=256 - Print a flattened netlist with all instances and models; only those parameters specified in the input netlist are printed. DumpLevel=512 - Print a flattened netlist with all instances and models; all readable parameters are printed; parameters that weren t specified in the input netlist have their default values printed. There are a number of options to DumpLevel that are available. They can be activated by adding the values described in Table 5-1 to the primary DumpLevel. Table 5-1. DumpLevel Options Value Description +1 Print numbers in engineering format with unit strings (Slew=25.6 MV/s); the default is scientific format (Slew=2.56e+07). +8 Print one parameter per line; the default is to print as many parameters as fit in an 80 character line. +16 Print all aliases for parameters (e.g. Tnom=25 Tref=25); by default only one aliased parameter name is printed. +32 Print parameters that default to zero; normally default values of zero are not printed. Instances and models that are secured (either from an encrypted library or via the Secured parameter) do not have their nodes and parameters printed. There are some instance and model parameters that are not printed. Indexed and repeated parameters are currently not printed (e.g. SDD I[1,0]). Identifying Unsupported Features 5-3

174 Managing Unsupported Features You can use the Simulation File Setup form to point to a file that includes the DumpFile and DumpLevel command options. To use the Simulation File Setup form instead of editing the netlist directly, 1. Save the following line in a file named something like DumpOutput.txt. Options DumpFile="dumpfile.txt" DumpLevel=288 Ensure the permissions on the file will allow the software to execute the file. 2. From the Analog Design Environment window, choose Setup > Simulation Files. The Simulation File Setup form appears. 3. Enter the path to the DumpOutput.txt file in the Include Path field. 4. Enter the name of your file, DumpOutput.txt in this case, in the Definition Files field. 5. Click OK and then run your simulation. When your simulation runs, the DumpOutput.txt file will be included in your netlist and the flattened output will be sent to the dumpfile.txt file, or whatever you had defined the output file to be. For more information on Simulation File Setup, refer to Setting Up Simulation Files for Direct Simulation in Chapter 2 of the Cadence Virtuoso Analog Design Environment User Guide, Product Version Incompatible Features This section includes information on known incompatible features. In some cases, it may not be clear if a feature is unsupported or you may encounter a difficult problem that is not documented in this manual. In this case, you may find helpful information to address your particular problem on the Agilent EEsof EDA Knowledge Center. You can access the Knowledge Center from the Agilent EEsof EDA Web site at: Spectre Analyses Spectre Analyses are not supported by RFDE. If the simulator encounters a Spectre Analysis statement in the netlist, a warning message similar to the following will be reported: 5-4 Incompatible Features

175 Warning detected by hpeesofsim during netlist parsing. Skipping instance `dc1' of type `dc'. For more information on Spectre Analyses, refer to Chapter 6: Analyses in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version Spectre Control Statements The Spectre circuit simulator includes multiple control statements that can be sequenced in a Spectre netlist. Many of these control statements are not supported by RF Design Environment. The information below will help you understand some of the issues related to these control statements and how you might work around a particular situation. The alter and altergroup Statements The Spectre alter statement is used to modify individual parameters for devices, models, circuit, and subcircuit parameters during a simulation. The Spectre altergroup statement is used to change model file parameters by listing the device, model, and circuit parameter statements as you would in the main netlist. The alter and altergroup statements are not supported in RF Design Environment. If the simulator encounters a Spectre alter statement in the netlist, a warning message is reported and the statement is ignored. If the simulator encounters a Spectre altergroup statement in the netlist, an error message is reported and the simulation is terminated. For more information on the Spectre alter and altergroup statements, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The assert Statement The Spectre assert statement enables you to set custom checks to determine the safe operating area of your circuit. The assert statement is not supported in RF Design Environment. If the simulator encounters a Spectre assert statement in the netlist, a warning message is reported and the statement is ignored. Incompatible Features 5-5

176 Managing Unsupported Features For more information on the Spectre assert statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The check Statement The Spectre check statement enables you to perform a check analysis at any point in a simulation to be sure that the values of component parameters are reasonable. The check statement is not supported in RF Design Environment. If the simulator encounters a Spectre check statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre check statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The checklimit Statement The Spectre checklimit statement enables you to enable or disable an assert or group of asserts. The checklimit statement is not supported in RF Design Environment. If the simulator encounters a Spectre checklimit statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre checklimit statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The ic and nodeset Statements The Spectre ic and nodeset statements enable you to provide state information to DC and transient analyses. The ic and nodeset statements are not supported in RF Design Environment. If the simulator encounters a Spectre ic or nodeset statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre ic and nodeset statements, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version Incompatible Features

177 The info Statement The Spectre info statement is used to generate lists of component parameter values. The info statement enables you to access the values of input, output, and operating-point parameters in Spectre and print a capacitance table. The info statement is not supported in RF Design Environment. If the simulator encounters a Spectre info statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre info statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The options Statement The Spectre options statement enables you to enter initial parameters for your simulation that you do not specify in your environment variables or on your command line. The options statement is not supported in RF Design Environment. If the simulator encounters a Spectre options statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre options statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The paramset Statement The Spectre paramset statement enables you to specify a list of parameters and their values for the sweep analysis. The paramset statement is not supported in RF Design Environment. If the simulator encounters a Spectre paramset statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre paramset statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version Incompatible Features 5-7

178 Managing Unsupported Features The save Statement The Spectre save statement enables you to save signals for individual nodes and components or save groups of signals. The save statement is not supported in RF Design Environment. If the simulator encounters a Spectre save statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre save statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The set Statement The Spectre set statement enables you to modify any options statement parameters you set at the beginning of the netlist, with the exception of temperature parameters and scaling factors. The set statement is not supported in RF Design Environment. If the simulator encounters a Spectre set statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre set statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The shell Statement The Spectre shell statement enables you to pass a command given in a SHELL environment variable to the operating system command interpreter. The shell statement is not supported in RF Design Environment. If the simulator encounters a Spectre shell statement in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre shell statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version The paramtest Component The Spectre paramtest component enables you to test the value of subcircuit parameters. 5-8 Incompatible Features

179 The paramtest component is not supported in RF Design Environment. If the simulator encounters a Spectre paramtest component in the netlist, a warning message is reported and the statement is ignored. For more information on the Spectre paramtest component, refer to Range Checking on Subcircuit Parameters in Chapter 13 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version Model Scale Factor (scalem) The Spectre model scale factor (scalem) capability is used to set scaling factors for model parameters. The scalem feature is not supported by RF Design Environment and there is no equivalent model scale factor in RFDE. The model scale factor is specified in the Spectre options statement. If a scalem statement is encountered, a warning message is generated and the options statement is ignored. For more information on scalem, refer to Scaling Factors (scale and scalem) in Chapter 3 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version Missing Devices and Models Supported devices and models are listed under Supported Devices and Models on page 3-4. If your device or model is not listed in the Supported Devices and Models section, the component or model should be considered unsupported. Spectre High-Level Description Language (HDL) The Spectre High-Level Description Language (HDL) is a language that uses functional description text files (modules) to model the behavior of electrical circuits and other systems. Spectre HDL is not supported in RF Design Environment; however, RFDE does support Verilog-A models. Therefore, if you have a Spectre HDL model that you want to use, the recommendation is to convert your Spectre HDL model to a Verilog-A model. If you attempt to netlist an HDL module, an error will be generated. For more information on Spectre HDL, refer to the Cadence SpectreHDL Reference, Product Version 5.0. For more information on Verilog-A, refer to Using Verilog-A in RF Design Environment and the Verilog-A Reference Manual. Incompatible Features 5-9

180 Managing Unsupported Features See also Verilog-A Usage and Language Summary (veriloga) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version Cadence Compiled-Model Interface (CMI) Custom models created using Cadence Compiled-Model Interface (CMI) are not supported in RFDE. If a CMI model is encountered, an error will be generated. RFDE does however support user-defined models. In order to use CMI, the recommendation is to convert your CMI models to RFDE user-defined models or Verilog-A models. For more information on Verilog-A models, refer to the RFDE Verilog-A documentation in the Simulation and Optimization section of your RFDE documentation set. For more information on user-defined models, refer to the Advanced Design System User-Defined Models documentation in the ADS Model Development section. The ADS documentation set can be accessed from the Agilent EEsof EDA Web site at: Spectre Encryption RFDE cannot simulate models that have been encrypted by Spectre. If a Spectre encrypted model is encountered, an error will be generated. If you have a Spectre encrypted model that you would like to use, you will need to acquire an un-encrypted version of the Spectre model. SPICE Format Compatibility Using simulator lang=<mode>, you can specify a language mode for subsequent statements. Spectre supports the simulator lang=spice statement; however, if RFDE encounters the simulator lang=spice statement, it will not be able to parse anything other than comments, blank lines, and other simulator lang=<mode> statements. Any other SPICE statements will generate error messages. If you have a file that is compatible with Spectre and includes a mix of Spectre and SPICE syntax, you can use the Spectre Pre-Parser (SPP) command (spectrespp) from the Cadence directory to enable the SPICE Reader and output the file so that it is 100% Spectre syntax. The recommendation is to use the spectrespp command to 5-10 Incompatible Features

181 output a 100% Spectre syntax file and then use that file with RF Design Environment. For more information on the running the SPICE Reader, refer to SPICE Compatibility in Chapter 3 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version Alternatively, you can translate a 100% SPICE netlist using the nettrans command to convert your SPICE netlist into an ads netlist. The issue here is that the netlist must be 100% SPICE syntax. The nettrans command will not accept a netlist with a mix of Spectre and SPICE syntax. For more information on the nettrans command, refer to the Advanced Design System Netlist Translator for SPICE and Spectre documentation. You can access this documentation from the Agilent EEsof EDA Web site at: Incompatible Features 5-11

182 Managing Unsupported Features Error Handling When a syntax error (including an unknown feature) is encountered by the system, an error is reported to the user. Any simulation that attempts to netlist an unsupported format will generate a syntax error. In general, any time the simulator encounters an error, the simulation will be terminated. For more information on error messages that may be generated, refer to Identifying Unsupported Features on page 5-1. See also the Agilent EEsof EDA Knowledge Center for the latest up-to-date information Incompatible Features

183 Chapter 6: The RFDE Netlister This chapter provides information on the RFDE Netlister. The chapter covers information on the following topics: Instance Netlisting on page 6-2 Basic Spectre Formatting on page 6-2 Instance Name Mapping on page 6-3 Node Name Mapping on page 6-3 Adding Instance Pins for pinmapping on page 6-3 Subcircuit Netlisting on page 6-4 Scoping Rules on page 6-4 Verilog-A Netlisting on page 6-5 Include Files on page 6-5 Default Switch and Stop View Lists, Hierarchy Editor on page 6-6 Error Messages on page 6-6 Alias Warning Messages on page 6-7 Backward Compatibility on page 6-7 A netlister is used to create a text based representation of a circuit database. The format of the netlist is specific to the tool that will use it. It is a tried and true method of passing information from one tool to another, and the format of the netlist provides a basis for the two tools to understand one another. Typically, this is used by a database tool, such as Cadence s schematic environment, to talk to a simulator such as Cadence s Spectre or Agilent s ADSsim in RFDE. Cadence requires that a library be set up to create a proper netlist for a simulator. Multiple simulators can be set up for a particular component in a library; however, each of these setups can take time and require a resource to perform verification of the setups. Setup also requires specific knowledge of specific simulator components and simulator syntax. Agilent EEsof EDA now provides a product that operates with Cadence library components that are setup to work with the Cadence Spectre netlister. The RFDE netlister has been updated so that it can switch between using the RFDE native formatter and the Spectre formatter. The net result of this is that little or no RFDE 6-1

184 The RFDE Netlister specific setup in addition to existing Spectre setup is required. The RFDE user interface has also been enhanced so that you can specify Spectre model files from a PDK to have them read in by the ADSsim simulator properly. Instance Netlisting Instances can be netlisted in either RFDE native format or in Spectre format. To enable this, several functions have been modified. Control over the formatting is determined by the stop view that is encountered, and upon user definable compatibility setups. When an ads stop view is encountered, the netlister will choose to format the instance using the existing RFDE native formatter. If the stop view is not ads, the software will check to see if the component has been marked as being incompatible with RFDE s Spectre-Compatibility. If the component is determined to be incompatible, the RFDE formatter will be used; if there is no ads tool setup, this will result in a netlisting error. If the component is determined to be compatible, the Spectre formatter will be used to output the instance. A simulator lang=spectre or simulator lang=ads line will be output as necessary, depending on whether spectre or ads format is being utilized. Basic Spectre Formatting To specify a component in Spectre, you need to use an instance statement. The example below shows the general format for a Spectre instance statement. name (node1...noden) type [param1=value1...paramn=valuen] where name is the component name you supply for the instance statement. node1...noden are the pin names for each node of the component. type is the name of a built-in primitive (such as a resistor), a model, a subcircuit, or an AHDL module. param1=value1...paramn=valuen are used to specify parameter values for your component. All functions called during Spectre formatting come from the Spectre formatter. Custom netlist functions should be written for the Spectre formatter. The Spectre siminfo is utilized to determine formatting. In cases where a viewinfo exists, the viewinfo is assumed to be set up for the Spectre formatter, not the ads formatter. If no 6-2 Instance Netlisting

185 netlisting function is specified, the nlprintinst function from the Spectre formatter is used to format the instance. For custom netlisting functions, the formatter passed to the function will be of the spectreformatter class, not the adsformatter class. All calls will be scoped based on using the spectreformatter. For more information, refer to the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version Instance Name Mapping All instance name mappings are stored in the netlist/amap directory. RFDE is compatible with OASIS, and utilizes identical files to Spectre. When Spectre mapping is used, the map and amap directories are created under the ADSsim tool directory for the cell, and can be used directly by RFDE for back annotation. In cases where the name is mapped, nlgetsimname will return the Spectre mapped name. Note Instance mapping will affect measurement equation generation. Measurement equations may need to be manually set up to account for the netlisting mapping. Node Name Mapping Node names are mapped based on the ADSsim reserved word rules and node name rules. This is to ensure that node names within ADS and Spectre sections will be identical. The Spectre formatter is altered after it is created so that the Spectre mapping rules are replaced with the ADSsim mapping rules. Adding Instance Pins for pinmapping For storage of pin currents, the netlisting code has been set up to automatically add the proper pinmapping information to the session in the function nlsetcurrentinstance. In previous releases, it was necessary to call rfdenetlistpinmapping_addinstance( _inst ) in a custom netlisting function to get the pin mapping data added. This is no longer required. Instance Name Mapping 6-3

186 The RFDE Netlister Subcircuit Netlisting Because of potential scoping rule differences, the mode that a subcircuit is netlisted in can affect the final outcome. This is a rare situation; however, to ensure compatibility, it is still possible to have RFDE netlist a subcircuit in Spectre mode. To do this, you must explicitly add Spectre compatibility to your user-defined compatibility file for the library containing your subcircuits. If this is done, the Spectre formatter will be used to output the subcircuit header, parameters, and footer. If nothing is set, the existing RFDE formatter is used to output the subcircuit header, parameters, and footer in native RFDE format. Example The following is an example of Spectre subcircuit output. simulation lang=spectre subckt name ( node1... noden ) parameters param1=... paramn=... ends name Scoping Rules The process of name resolution is slightly different for ADSsim-language subcircuits versus Spectre-language subcircuits. The language of a subcircuit, and therefore the scoping rules used by that subcircuit, follow from the language used for the subcircuit header. For example: simulator lang=ads define mysubckt1 [...] end mysubckt1 simulator lang=spectre subckt mysubckt2 [...] ends mysubckt2 For evaluating references in expressions, both Spectre-language and ADSsim-language subcircuits use dynamic scoping rules, which resolve a name by searching upward through the instantiation hierarchy. This is consistent with how the Spectre simulator behaves. 6-4 Subcircuit Netlisting

187 For locating a component type, an ADSsim-language subcircuit uses dynamic scoping rules, and a Spectre-language subcircuit uses static scoping rules. Static scoping looks upward through the definition hierarchy, rather than the instantiation hierarchy. Note The component type referred to above is the model or subcircuit used to instantiate the instance. In ADSsim syntax, it is the name on the left side of the colon. In Spectre syntax, it is the last name given before the list of parameters begins. This example shows that it is possible to construct a case where the behavior of a subcircuit may depend on whether static scoping rules or dynamic scoping rules are used. Construction of such a problem requires that at least one subcircuit contain a model definition or a nested subcircuit. A netlist without such nested definitions is not subject to any scoping problems of this sort. This problem also requires that the same name be used for differing component types, in different parts of the netlist. The easiest way to be free from worry about this problem is to use unique names for models and subcircuits. Note If you depend on scoping rules and use ambiguous names for component types to avoid simulation problems, you are likely to confuse your foundry kit users. It is highly recommended that you use unique names and avoid relying on particular scoping rules. Verilog-A Netlisting Components that are set up to utilize veriloga using viewinfo setups will use the RFDE native formatter, unless the component is explicitly set up to be listed as compatible with RFDE Spectre-Compatibility. Include Files The model include, definition, and stimulus files will all be checked for netlist format. The following rules apply: If the file ends with a.scs suffix, it is assumed to be a Spectre syntax file. The file will be output using Spectre include/section syntax. Verilog-A Netlisting 6-5

188 The RFDE Netlister If the file ends with a.een suffix, it is assumed to be an EEsof netlist, and will be output with the existing #define/#include syntax for backward compatibility. If the file does not end with either of the above suffixes, the file will be opened and parsed. If a simulator lang=spectre line is found, the file is assumed to be a Spectre syntax file, and is output using Spectre include/section syntax. If the file does not have a simulator lang=spectre line, or if non-comment lines are found prior to encountering a simulator lang=spectre line, the file is assumed to be RFDE native syntax, and the existing #define/#include syntax is output. Note If a non-spectre or non-rfde file is included (e.g. an hspice netlist), it will still be output and included as RFDE syntax. This will cause a syntax error in the simulator. Default Switch and Stop View Lists, Hierarchy Editor The RFDE environment files have been updated to add spectre to the default switch and stop view lists for ADSsim. In addition, spectre has been added to the ads template for the Hierarchy Editor. In the event that an existing state that stored environment settings is loaded, you will need to add spectre to the switch and stop view list in order to use it. If an existing Hierarchy Editor config file is opened, you will need to add spectre to the switch and stop view lists manually. For more information on the Hierarchy Editor, refer to the Cadence Hierarchy Editor User Guide, Product Version Error Messages The following example errors are specific to Spectre-Compatibility: Spectre view not added to the switch view list and stop view list for a compatibility enabled library. Spectre siminfo does not exist for a compatibility enabled library. Bad simulation results obtained due to scoping differences between Spectre and RFDE. Model file specified with Spectre library and sections that include other files, but the file does not have a.scs extension. ads stop view and siminfo not added to a library that will not be used in compatibility mode. 6-6 Default Switch and Stop View Lists, Hierarchy Editor

189 OASIS traps numerous error conditions; however, these error messages cannot be readily trapped and overridden in RF Design Environment. There are also numerous issues that can relate to mis-configuring your PDK setup for Spectre. For example, specifying a non-existent netlisting function for Spectre. These are not covered here, the netlister assumes that a PDK is properly configured and installed to work with Spectre. Alias Warning Messages This section provides information on how to interpret simulator warning messages generated by RFDE and what actions you need to take to understand the issue when these messages appear. Incompatible Spectre Definition Warning!: The spectre definition for the cell <cell> in the library <library> is not compatible with RFDE. The ads definition will be used instead. This warning is issued if there is an ads definition available to use for netlisting. If there is no definition available, an alternate error message is generated: Error!: The spectre definition for the cell <cell> in the library <library> is not compatible with RFDE. There is no ads definition for the cell, this component cannot be netlisted. In the error condition above, there will additionally be an OASIS generated error message that specifies that a master could not be found for the instance. All other errors and warnings are generated by OASIS. Backward Compatibility All components that have been set up to work with RFDE in prior releases will continue to be output identically in the current release, provided the component is set up to be netlisted in RFDE native mode. RFDE native mode is the default netlisting mode. RFDE native mode will be used for a component if an ads stop view is encountered, or if the component is not listed as being Spectre-Compatible in one of the compatibility setup files. Alias Warning Messages 6-7

190 The RFDE Netlister 6-8 Backward Compatibility

191 Chapter 7: Spectre-Compatible Process Design Kit Verification This chapter describes how to compare Spectre and RFDE results using the Cadence Results Browser, DC annotation, and DC operating points through the Cadence environment. Setting Up and Running a Simulation Before comparing your results, you will need to perform a simulation on your design using both Spectre and RF Design Environment. Note that your RFDE output data must be translated into Cadence s native data format, parameter storage format (PSF), in order for you to compare your results in the Cadence Results Browser. The procedure below will guide you through setting up and running your simulation. 1. Open your design by choosing File > Open from the CIW. Use the Open File form to open the schematic window with your design. 2. From the schematic window, choose Tools > Analog Environment. The Cadence Analog Design Environment window appears. 3. Setup the Analog Design Environment for your Spectre simulation by selecting the spectre simulator. 4. From the Cadence CIW, choose File > Open. Use the Open File form to open a new schematic window with your design. Note Be aware that when you make a change in one schematic window, the other window will automatically update with the change you made in the first window. You may want to save a backup copy of your design using the Design > Save As menu item in the schematic window. You can name your backup design something like <schematic_name>_original. 5. Setup the Analog Design Environment for your RFDE simulation by selecting the ADSsim simulator. 6. In the Analog Design Environment window for your RFDE simulation, choose Results > Data Display Options. The Data Display Options form appears. Setting Up and Running a Simulation 7-1

192 Spectre-Compatible Process Design Kit Verification 7. Enable the Translate Results to PSF option in the Data Display Options form and click OK. This will ensure that your output is saved as PSF and enable you to view and compare your data in the Cadence Results Browser. 8. Run a simulation on both the Spectre and RFDE setups. After your simulations have completed successfully, you will be able to compare your results in the Cadence Results Browser. Using the Results Browser This section briefly describes how to launch the Cadence Results Browser and view your results from multiple simulations. The Results Browser is a standalone front-end to the Cadence Waveform Viewer. The tool enables you to send plots to a graph, a table, or to the Cadence Calculator. The prerequisite is that your RFDE output data is translated into PSF. For a tutorial on using the Cadence Results Browser stand-alone, refer to Chapter 2 of the Cadence WaveScan Tutorial, Product Version To verify your results using the Results Browser from RF Design Environment, 1. Access the Analog Design Environment (ADE) window. 2. Choose Tools > Results Browser. The Results Browser window appears. 7-2 Using the Results Browser

193 You will notice that the PSF directory output names from Cadence are different from the PSF output names for RFDE. This is due to data format differences between Agilent s Data Display and Cadence s Spectre. Generally speaking, Cadence provides names that are doubled-up for the simulation that was run. For example, dc-dc (for a DC simulation), sp-sp (for an S-parameter simulation), etc. Results with these types of names will contain swept data. RFDE results, especially for sweeps, typically have a sweep name in the directory name. For example, a DC sweep will be output into something like srcsweep, as opposed to dc-dc. Refer to Table 7-1 for several examples. Table 7-1. Example PSF Output Directory Names Spectre Directory Name RFDE Directory Name dc-dc dcopdc sp-sp variables srcsweep dcop-dc sp-sp variables Using the Results Browser 7-3