Non-Pipelined Processors
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1 Constructive Computer Architecture: Non-Pipelined Processors Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology L10-1 Single-Cycle RISC Processor As an illustrative example, we will use a subset of RISC-V 32-bit ISA. Register File 2 read & 1 write ports PC +4 Decode Execute Inst Memory separate Instruction & Data memories Data Memory Datapath and control are derived automatically from a high-level rule-based description L10-2 1
2 Single-Cycle Implementation code structure module mkproc(proc); Reg#(Addr) pc <- mkregu; RFile rf <- mkrfile; IMemory imem <- mkimemory; DMemory dmem <- mkdmemory; to be explained later instantiate the state rule doproc; let inst = imem.req(pc); extracts fields let dinst = decode(inst); needed for let rval1 = rf.rd1(dinst.rsrc1); execution let rval2 = rf.rd2(dinst.rsrc2); let einst = exec(dinst, rval1, rval2, pc); produces values update rf, pc and dmem needed to update the processor state L10-3 RISC-V Register States 32 general purpose registers (GPR) x0, x1,, x31 32-bit wide integer registers x0 is hard-wired to zero Program counter (PC) 32-bit wide CSR (Control and Status Registers) cycle instret mhartid mtohost... will be implemented in labs as needed L10-4 2
3 Computational Instructions Register-Register instructions (R-type) funct7 rs2 rs1 funct3 rd opcode opcode=op: rd rs1 (funct3, funct7) rs2 funct3 = SLT/SLTU/AND/OR/XOR/SLL funct3= ADD funct7 = : rs1 + rs2 funct7 = : rs1 rs2 funct3 = SRL funct7 = : logical shift right funct7 = : arithmetic shift right L10-5 Computational Instructions cont Register-immediate instructions (I-type) imm[11:0] rs1 funct3 rd opcode opcode = OP-IMM: rd rs1 (funct3) I-imm I-imm = signext(inst[31:20]) funct3 = ADDI/SLTI/SLTIU/ANDI/ORI/XORI A slight variant in coding for shift instructions - SLLI / SRLI / SRAI rd rs1 (funct3, inst[30]) I-imm[4:0] L10-6 3
4 Control Instructions Unconditional jump and link (UJ-type) imm[20] imm[10:1] imm[11] imm[19:12] rd opcode opcode = JAL: rd pc + 4; pc pc + J-imm J-imm = signext({inst[31], inst[19:12], inst[20], inst[30:21], 1 b0}) Jump ±1MB range Unconditional jump via register and link (I-type) imm[11:0] rs1 funct3 rd opcode opcode = JALR: rd pc + 4; pc (rs1 + I-imm) & ~0x01 I-imm = signext(inst[31:20]) L10-7 Control Instructions cont. Conditional branches (SB-type) imm[12] imm[10:5] rs2 rs1 funct3 imm[4:1] imm[11] opcode opcode = BRANCH: pc compare(funct3, rs1, rs2)? pc + B-imm : pc + 4 B-imm = signext({inst[31], inst[7], inst[30:25], inst[11:8], 1 b0}) Jump 4KB range funct3 = BEQ/BNE/BLT/BLTU/BGE/BGEU L10-8 4
5 Load & Store Instructions Load (I-type) imm[11:0] rs1 funct3 rd opcode opcode = LOAD: rd mem[rs1 + I-imm] I-imm = signext(inst[31:20]) funct3 = LW/LB/LBU/LH/LHU Store (S-type) imm[11:5] rs2 rs1 funct3 imm[4:0] opcode opcode = STORE: mem[rs1 + S-imm] rs2 S-imm = signext({inst[31:25], inst[11:7]}) funct3 = SW/SB/SH L10-9 Decoding Instructions: extract fields needed for execution instruction Bit#(32) pure combinational logic: derived automatically from the high-level description decode 6:0 6:0,14:12,30 6:0, 14:12 11:7 19:15 24:20 31:7 ext itype IType alufunc AluFunc brcomp BrFunc Type DecodedInst rdst Maybe#(RIndx) rsrc1 Maybe#(RIndx) rsrc2 Maybe#(RIndx) imm Maybe#(Bit#(32)) L
6 Decoded Instruction Type typedef struct { IType itype; AluFunc alufunc; BrFunc brfunc; Maybe#(RIndx) dst; Maybe#(RIndx) src1; Maybe#(RIndx) src2; Maybe#(Data) imm; } DecodedInst deriving(bits, Eq); Destination register 0 behaves like an Invalid destination Instruction groups with similar executions paths typedef enum {Unsupported, Alu, Ld, St, J, Jr, Br, Auipc} IType deriving(bits, Eq); typedef enum {Add, Sub, And, Or, Xor, Slt, Sltu, Sll, Sra, Srl} AluFunc deriving(bits, Eq); typedef enum {Eq, Neq, Lt, Ltu, Ge, Geu, AT, NT} BrFunc deriving(bits, Eq); L10-11 Internal names for various opcode and funct3 patterns // opcode Bit#(7) opopimm = 7'b ; // OP-IMM Bit#(7) opop = 7'b ; // OP Bit#(7) oplui = 7'b ; // LUI Bit#(7) opauipc = 7'b ; // AUIPC... Bit#(7) opjal = 7'b ; // JAL Bit#(7) opjalr = 7'b ; // JALR Bit#(7) opbranch = 7'b ; // BRANCH Bit#(7) opload = 7'b ; // LOAD Bit#(7) opstore = 7'b ; // STORE // funct3 Bit#(3) fnadd = 3'b000; // ADD Bit#(3) fnsll = 3'b001; // SLL Bit#(3) fnslt = 3'b010; // SLT Values are specified in the RISC-V ISA L
7 Decode Function function DecodedInst decode(bit#(32) inst); DecodedInst dinst =?; let opcode = inst[ 6 : 0 ]; let rd = inst[ 11 : 7 ]; let funct3 = inst[ 14 : 12 ]; let rs1 = inst[ 19 : 15 ]; let rs2 = inst[ 24 : 20 ]; let alusel = inst[ 30 ]; // Add/Sub, Srl/Sra Bit#(32)immI= ; Bit#(32)immS= ; Bit#(32)immB= ; initially undefined Bit#(32)immU= ; Bit#(32)immJ= ; // I/S/B/U/J-imm case (opcode) opop... case return dinst; function L10-13 Decoding Instructions: Computational Instructions opop: begin dinst.itype = Alu; dinst.alufunc = case (funct3) fnand: And; fnsltu: Sltu; fnadd: Add; alusel == 0? Add : Sub; fnsr: alusel == 0? Srl : Sra; case; dinst.brfunc = NT; dinst.dst = Valid rd; dinst.src1 = Valid rs1; dinst.src2 = Valid Invalid; rs2; Decoding instructions dinst.imm = Invalid; Valid ImmI; with immediate operand (i.e. opcode = OP-IMM) is similar L
8 Decoding Instructions: Conditional Branch opbranch: begin Maybe#(BrFunc) brf = case(funct3) fnbeq: Valid Eq; fnbgeu: Valid Geu; default: Invalid; case; dinst.itype = isvalid(brf)? Br : Unsupported; dinst.alufunc =?; dinst.brfunc = frommaybe(?, brf); dinst.dst = Invalid; dinst.src1 = Valid rs1; dinst.src2 = Valid rs2; dinst.imm = Valid immb; L10-15 Decoding Instructions: Load & Store opload: begin // only support LW dinst.itype = funct3 == fnlw? Ld : Unsupported; dinst.alufunc = Add; // calc effective addr dinst.brfunc = NT; dinst.dst = Valid rd; dinst.src1 = Valid rs1; dinst.src2 = Invalid; dinst.imm = Valid immi; opstore: begin // only support SW dinst.itype = funct3 == fnsw? St : Unsupported; dinst.alufunc = Add; // calc effective addr dinst.brfunc = NT; dinst.dst = Invalid; dinst.src1 = Valid rs1; dinst.src2 = Valid rs2; dinst.imm = Valid imms; L
9 Reading Registers and Executing Instructions src2 src1 RF Pure combinational logic dinst rval2 rval1 pc execute ALU ALUBr Branch Address itype dst data either for rf write or St either for memory addr reference or branch target brtaken misspredict L10-17 Output of exec function typedef struct { IType itype; Maybe#(RIndx) dst; Data data; Addr addr; Bool mispredict; Bool brtaken; } ExecInst deriving(bits, Eq); L
10 Execute Function function ExecInst exec(decodedinst dinst, Data rval1, Data rval2, Addr pc); ExecInst einst =?; Data aluval2 = frommaybe(rval2, dinst.imm); let alures = alu(rval1, aluval2, dinst.alufunc); einst.itype = dinst.itype; einst.data = dinst.itype==st? rval2 : (dinst.itype==j dinst.itype==jr)? (pc+4) : dinst.itype==auipc? (pc+frommaybe(?, dinst.imm)) : alures; let brtaken = alubr(rval1, rval2, dinst.brfunc); let braddr = braddrcalc(pc, rval1, dinst.itype, frommaybe(?, dinst.imm), brtaken); einst.brtaken = brtaken; einst.addr = (dinst.itype==ld dinst.itype==st)? alures : braddr; einst.dst = dinst.dst; return einst; function L10-19 Single-Cycle SMIPS atomic state updates if(einst.itype == Ld) einst.data <- dmem.req(memreq{op: Ld, addr: einst.addr, data:?}); else if (einst.itype == St) let dummy <- dmem.req(memreq{op: St, addr: einst.addr, data: data}); if(isvalid(einst.dst)) rf.wr(frommaybe(?, einst.dst), einst.data); pc <= einst.brtaken? einst.addr : pc + 4; rule module state updates The whole processor is described using one rule; lots of big combinational functions L
11 Harvard-Style Datapath for MIPS PCSrc br rind jabs pc+4 RegWrite MemWrite old way WBSrc 0x4 Add Add clk PC clk addr inst Inst. Memory 31 we rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext ALU Control ALU z clk we addr rdata Data Memory wdata OpCode RegDst ExtSel OpSel BSrc zero? L10-21 Hardwired Control Table old way Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc ALU ALUi ALUiu LW SW BEQZ z=0 BEQZ z=1 J JAL JR JALR * Reg Func no yes ALU rd pc+4 sext 16 Imm Op no yes ALU rt pc+4 uext 16 Imm Op no yes ALU rt pc+4 sext 16 Imm + no yes Mem rt pc+4 sext 16 Imm + yes no * * pc+4 sext 16 * 0? no no * * br sext 16 * 0? no no * * pc+4 * * * no no * * jabs * * * no yes PC R31 jabs * * * no no * * rind * * * no yes PC R31 rind BSrc = Reg / Imm WBSrc = ALU / Mem / PC RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs L
12 Extras L10-23 Instruction Formats R-type instruction funct7 rs2 rs1 funct3 rd opcode I-type instruction & I-immediate (32 bits) imm[11:0] rs1 funct3 rd opcode I-imm = signext(inst[31:20]) S-type instruction & S-immediate (32 bits) imm[11:5] rs2 rs1 funct3 imm[4:0] opcode S-imm = signext({inst[31:25], inst[11:7]}) L
13 Instruction Formats cont. SB-type instruction & B-immediate (32 bits) imm[12] imm[10:5] rs2 rs1 funct3 imm[4:1] imm[11] opcode B-imm = signext({inst[31], inst[7], inst[30:25], inst[11:8], 1 b0}) U-type instruction & U-immediate (32 bits) 20 imm[31:12] U-imm = signext({inst[31:12], 12 b0}) UJ-type instruction & J-immediate (32 bits) 5 7 rd opcode imm[20] imm[10:1] imm[11] imm[19:12] rd opcode J-imm = signext({inst[31], inst[19:12], inst[20], inst[30:21], 1 b0}) L10-25 Computational Instructions cont. Register-immediate instructions (U-type) 20 imm[31:12] opcode = LUI : rd U-imm opcode = AUIPC : rd pc + U-imm U-imm = {inst[31:12], 12 b0} 5 7 rd opcode L
14 Decoding Instructions case (opcode) // opcode opopimm: opop: oplui: opauipc: opjal: opjalr: opbranch: opload: opstore: default: // Unsupported case; Bit#(7) opopimm = 7'b ; Bit#(7) opop = 7'b ; Bit#(7) oplui = 7'b ; Bit#(7) opauipc = 7'b ; Bit#(7) opjal = 7'b ; Bit#(7) opjalr = 7'b ; Bit#(7) opbranch = 7'b ; Bit#(7) opload = 7'b ; Bit#(7) opstore = 7'b ; L10-27 Decoding Instructions: Computational Instructions - Imm opopimm: begin dinst.itype = Alu; dinst.alufunc = case (funct3) fnadd: Add; fnsltu: Sltu; fnsll: Sll; fnsr: alusel == 0? Srl : Sra; case; dinst.brfunc = NT; dinst.dst = Valid rd; dinst.src1 = Valid rs1; dinst.src2 = Invalid; dinst.imm = Valid immi; L
15 Decoding Instructions: Computational Instructions cont. oplui: begin // rd = immu + r0 dinst.itype = Alu; dinst.alufunc = Add; dinst.brfunc = NT; dinst.dst = tagged Valid rd; dinst.src1 = tagged Valid 0; dinst.src2 = tagged Invalid; dinst.imm = tagged Valid immu; opauipc: begin dinst.itype = Auipc; dinst.alufunc =?; dinst.brfunc = NT; dinst.dst = tagged Valid rd; dinst.src1 = tagged Invalid; dinst.src2 = tagged Invalid; dinst.imm = tagged Valid immu; L10-29 Decoding Instructions: Unconditional Jumps opjal: begin dinst.itype = J; dinst.alufunc =?; dinst.brfunc = AT; dinst.dst = Valid rd; dinst.src1 = Invalid; dinst.src2 = Invalid; dinst.imm = Valid immj; opjalr: begin dinst.itype = Jr; dinst.alufunc =?; dinst.brfunc = AT; dinst.dst = Valid rd; dinst.src1 = Valid rs1; dinst.src2 = Invalid; dinst.imm = Valid immi; L
16 Decoding instructions: Unsupported default: begin dinst.itype = Unsupported; dinst.alufunc =?; dinst.brfunc = NT; dinst.dst = Invalid; dinst.src1 = Invalid; dinst.src2 = Invalid; dinst.imm = Invalid; L10-31 Branch Address Calculation function Addr braddrcalc(addr pc, Data val, IType itype, Data imm, Bool taken); Addr pcplus4 = pc + 4; Addr targetaddr = case (itype) J : {pc + imm}; Jr : {truncatelsb(val + imm), 1'b0}; Br : (taken? pc + imm : pcplus4); default: pcplus4; case; return targetaddr; function L
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