Control Unit. Main Memory. control. status. address instructions. address data. Internal storage Datapath

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Philomena Bruce
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1 control Internal storage Datapath status Control Unit address data address instructions Main Memory March 20, L11-1

2 Our interpreter is a Single-Cycle RISC-V Processor Control Register File 2 read & 1 write ports PC Decode Execute Datapath Memory Inst Memory separate Instruction & Data memories Data Memory Datapath (arrows in this diagram) are derived automatically from a high-level rule-based description March 20, L11-2

3 Instruction interpreter Fetch the instruction at pc Decode the instruction Read source operands Execute the instruction Update the register file, memory and pc March 20, L11-3

4 Our interpreter is a Single-Cycle RISC-V Processor Register File 2 read & 1 write ports PC Decode Execute Inst Memory separate Instruction & Data memories Data Memory Datapath (arrows in this diagram) are derived automatically from a high-level rule-based description March 20, L11-4

5 Instruction interpreter Putting it all together module mkinterpreter(empty); Reg#(Word) pc <- mkreg(0); RFile2R1W rf <- mkrfile2r1w; MagicMemory imem <- mkmagicmemory; MagicMemory dmem <- mkmagicmemory; rule dointerpreter; let inst <- imem.req(memreq{op:ld, addr:pc, data:?}); let dinst = decode(inst); // dinst fields: itype, alufunc, brfunc, dst, rs1, rs2, imm let rval1 = rf.rd1(dinst.rs1); let rval2 = rf.rd2(dinst.rs2); let einst = execute(dinst, rval1, rval2, pc); // einst fields: itype, rd, data, addr, nextpc updatestate(einst, pc, rf, dmem); // returns an action endrule endmodule March 20, L11-5

6 Register File 2 Read ports + 1 Write port index data index data rd1 rd2 rf wr index data en Registers can be read or written any time, so the guards are always true (not shown) typedef Bit#(32) Word; typedef Bit#(5) RIndx; interface RFile2R1W; method Word rd1(rindx index) ; method Word rd2(rindx index) ; method Action wr (RIndx index, Word data); endinterface March 20, L11-6

7 Register File implementation module mkrfile2r1w(rfile2r1w); Vector#(32,Reg#(Word)) rfile <- replicatem(mkreg(0)); method Word rd1(rindx rindx) = rfile[rindx]; method Word rd2(rindx rindx) = rfile[rindx]; method Action wr(rindx rindx, Word data); if(rindx!=0) begin rfile[rindx] <= data; end endmethod endmodule All three methods of the register file can be called simultaneously, and in that case the read methods read the value already in the register file {rd1, rd2} < wr Register 0 is hardwired to zero and cannot be written March 20, L11-7

8 Magic Memory Interface op address store data load data en memreq magic memory Magic memory can be read or written any time, so the guards are always true (not shown) typedef enum {Ld, St} MemOp deriving(bits, Eq); typedef struct {MemOp op; Word addr; Word data;} MemReq deriving(bits, Eq); interface MagicMemory; method ActionValue#(Word) req(memreq r); endinterface let data <- m.req(memreq{op:ld, addr:a, data:?}); let dummy <- m.req(memreq{op:st, addr:a, data:v}); March 20, L11-8

9 Arithmetic-Logic Unit (ALU) typedef enum {Add, Sub, And, Or, Xor, Slt, Sltu, Sll, Sra, Srl} AluFunc deriving(bits, Eq); function Word alu(word a, Word b, AluFunc func); Word res = case(func) Add: (a + b); Sub: (a - b); And: (a & b); Or: (a b); Xor: (a ^ b); Slt: (signedlt(a, b)? 1 : 0); Sltu: ((a < b)? 1 : 0); Sll: (a << b[4:0]); Srl: (a >> b[4:0]); Sra: signedshiftright(a, b[4:0]); endcase; return res; endfunction The ALU can be implemented simply by introducing a mux controlled by func to select the appropriate circuit signed functions are implemented in BSV by converting to Int#(n) and then doing the operation March 20, L11-9

10 ALU for Comparison operators typedef enum {Eq, Neq, Lt, Ltu, Ge, Geu} BrFunc deriving(bits, Eq); function Bool alubr(word a, Word b, BrFunc brfunc); Bool brtaken = case(brfunc) Eq: (a == b); Neq: (a!= b); Lt: signedlt(a, b); Ltu: (a < b); Ge: signedge(a, b); Geu: (a >= b); endcase; return brtaken; endfunction March 20, L11-10

11 Instruction interpreter Putting it all together module mkinterpreter(empty); Reg#(Word) pc <- mkreg(0); RFile2R1W rf <- mkrfile2r1w; MagicMemory imem <- mkmagicmemory; MagicMemory dmem <- mkmagicmemory; rule dointerpreter; let inst <- imem.req(memreq{op:ld, addr:pc, data:?}); let dinst = decode(inst); // dinst fields: itype, alufunc, brfunc, dst, rs1, rs2, imm let rval1 = rf.rd1(dinst.rs1); let rval2 = rf.rd2(dinst.rs2); let einst = execute(dinst, rval1, rval2, pc); // einst fields: itype, rd, data, addr, nextpc updatestate(einst, pc, rf, dmem); // returns an action endrule endmodule March 20, L11-11

12 Instruction decoder We need a function to extract the category and the various fields for each category from a 32-bit instruction Fields we have identified so far are: n n n n n Instruction category: OP, OPIMM, BRANCH, JAL, JALR, LUI, LOAD, STORE, Unsupported Function for alu: alufunc Function for bralu: brfunc Register fields: rd, rs1, rs2 Immediate constants Notice that no instruction has all the fields March 20, L11-12

13 Decoded Instruction Type typedef struct { IType itype; Destination register 0 AluFunc alufunc; behaves like an Invalid BrFunc brfunc; destination Maybe#(RIndx) dst; If dst is invalid register RIndx src1; file update is not RIndx src2; performed Word imm; } DecodedInst deriving(bits, Eq); typedef enum {OP, OPIMM, BRANCH, LUI, JAL, JALR, LOAD, STORE, Unsupported} IType deriving(bits, Eq); typedef enum {Add, Sub, And, Or, Xor, Slt, Sltu, Sll, Sra, Srl} AluFunc deriving(bits, Eq); typedef enum {Eq, Neq, Lt, Ltu, Ge, Geu} BrFunc deriving(bits, Eq); function DecodedInst decode(bit#(32) inst); March 20, L11-13

14 Function execute typedef struct { InstType itype; Maybe#(RIndx) rd; Word data; Word addr; Word nextpc; } ExecInst deriving (Bits, Eq); function ExecInst execute( DecodedInst dinst, Word rval1, Word rval2, Word pc ); March 20, L11-14

15 Single-Cycle RISC-V Processor Register File PC Decode Execute Inst Memory Data Memory March 20, L11-15

16 Function execute function ExecInst execute( DecodedInst dinst, Word rval1, Word rval2, Word pc ); // extract from dinst: itype, alufunc, brfunc, imm // initialize einst and its fields: data, nextpc, addr to? case (itype) matches OP: begin data = alu(rval1, rval2, alufunc); nextpc = pc+4; end OPIMM: begin data = alu(rval1, imm, alufunc); nextpc = pc+4; end BRANCH: begin nextpc = alubr(rval1, rval2, brfunc)? pc+imm : pc+4; end LUI: begin data = imm; nextpc = pc+4; end JAL: begin data = pc+4; nextpc = pc+imm; end JALR: begin data = pc+4; nextpc = (rval1+imm) & ~1; end LOAD: begin addr = rval1+imm; nextpc = pc+4; end STORE: begin data = rval2; addr = rval1+imm; nextpc = pc+4; end endcase // assign to einst; endfunction March 20, L11-16

17 Function update function Action updatestate( ExecInst einst, Reg#(Word) pc, RFile2R1W rf, MagicMemory dmem); return (action // memory access let data = einst.data; if (einst.itype == LOAD) begin data <- dmem.req(memreq{op: Ld, addr: einst.addr, data:?}); end else if (einst.itype == STORE) begin let dummy <- dmem.req(memreq{op: St, addr: einst.addr, data: data}); end // register file write if (isvalid(einst.rd)) rf.wr(frommaybe(?, einst.rd), data); // pc update pc <= einst.nextpc; endaction); endfunction This means we are passing the register, not its value, as a parameter March 20, L11-17

6.004 Recitation Problems L11 RISC-V Interpreter

6.004 Recitation Problems L11 RISC-V Interpreter Refer to the 6.004 ISA Reference Tables (Website > Resources) for details about each instruction. New Bluespec Constructs: Maybe Types // Maybe#() is a