6.004 Recitation Problems L11 RISC-V Interpreter

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6.004 Recitation Problems L11 RISC-V Interpreter Refer to the 6.004 ISA Reference Tables (Website > Resources) for details about each instruction.

1 6.004 Recitation Problems L11 RISC-V Interpreter Refer to the ISA Reference Tables (Website > Resources) for details about each instruction. New Bluespec Constructs: Maybe Types // Maybe#() is a type constructor that takes in a type and returns a new type with an extra bit to specify if the associated data is valid or not. // In the processor, Maybe#(Bit#(5)) is used to represent the destination register. Instructions that write to the register file have a Valid destination register. Instructions that do not write to the register file have an Invalid destination register. Maybe#(Bit#(5)) rd_a = Valid(3); // destination register for an instruction // that writes to x3 Maybe#(Bit#(5)) rd_b = Invalid; // destination register for an instruction // that does not write to a register // isvalid(x) returns True if x is a Valid value, and False if x is Invalid. isvalid(rd_a) // returns True isvalid(rd_b) // returns False // frommaybe(x, y) returns the data for y if y is a Valid value, and it returns x if y is Invalid frommaybe(0, rd_a) // returns 3 (valid value of rd_a) frommaybe(0, rd_b) // returns Worksheet - 1 of 10 - L11 RISC-V Interpreter

2 RISC-V Interpreter: Components Register File typedef Bit#(32) Word; typedef Bit#(5) RIndx; // Register File has 2 read ports and 1 write port interface RFile2R1W; method Word rd1(rindx rindx); method Word rd2(rindx rindx); method Action wr(rindx rindx, Word data); endinterface module mkrfile2r1w(rfile2r1w); Vector#(32, Reg#(Word)) rfile <- replicatem(mkreg(0)); method Word rd1(rindx rindx); return rfile[rindx]; endmethod method Word rd2(rindx rindx); return rfile[rindx]; endmethod method Action wr(rindx rindx, Word data); if (rindx!= 0) begin rfile[rindx] <= data; end endmethod endmodule Main Memory typedef enum { Ld, St } MemOp deriving (Bits, Eq, FShow); typedef struct { MemOp op; Word addr; Word data; } MemReq deriving (Bits, Eq); interface MagicMemory; method ActionValue#(Word) req(memreq memreq); endinterface Worksheet - 2 of 10 - L11 RISC-V Interpreter

3 ALU (within Execute) typedef enum {Add, Sub, And, Or, Xor, Nor, Slt, Sltu, Sll, Srl, Sra} AluFunc deriving (Bits, Eq, FShow); function Word alu(word a, Word b, AluFunc func); // Implemented in LAB2 typedef enum {Eq, Neq, Lt, Ltu, Ge, Geu} BrFunc deriving (Bits, Eq, FShow); function Bool alubr(word a, Word b, BrFunc brfunc); Bool res = case (brfunc) Eq: (a == b); Neq: (a!= b); Lt: signedlt(a, b); Ltu: (a < b); Ge: signedge(a, b); Geu: (a >= b); endcase; return res; Worksheet - 3 of 10 - L11 RISC-V Interpreter

4 Decode typedef enum {LUI, JAL, JALR, BRANCH, LOAD, STORE, OPIMM, OP, Unsupported} InstType deriving (Bits, Eq, FShow); typedef struct { InstType itype; AluFunc alufunc; BrFunc brfunc; Maybe#(RIndx) dst; RIndx src1; RIndx src2; Word imm; } DecodedInst deriving (Bits, Eq, FShow); // definition of AluFunc is with alu // definition of BrFunc is with bralu function DecodedInst decode(bit#(32) inst); // Implemented in Lab 5 return dinst; Worksheet - 4 of 10 - L11 RISC-V Interpreter

5 Execute typedef struct { InstType itype; Maybe#(RIndx) dst; Word data; Word addr; Word nextpc; } ExecInst deriving (Bits, Eq, FShow); function ExecInst execute(decodedinst dinst, Word rval1, Word rval2, Word pc); let imm = dinst.imm; let brfunc = dinst.brfunc; let alufunc = dinst.alufunc; Word data =?; Word nextpc =?; Word addr =?; case (dinst.itype) LUI: begin data = imm; nextpc = pc+4; end JAL: begin data = pc+4; nextpc = pc+imm; end JALR: begin data = pc+4; nextpc = (rval1+imm) & ~1; end BRANCH: begin nextpc = alubr(rval1, rval2, brfunc)? pc+imm : pc+4; end LOAD: begin addr = rval1+imm; nextpc = pc+4; end STORE: begin data = rval2; addr = rval1+imm; nextpc = pc+4; end OPIMM: begin data = alu(rval1, imm, alufunc); nextpc = pc+4; end OP: begin data = alu(rval1, rval2, alufunc); nextpc = pc+4; end endcase ExecInst einst =?; einst.itype = dinst.itype; einst.dst = dinst.dst; einst.data = data; einst.addr = addr; einst.nextpc = nextpc; return einst; Worksheet - 5 of 10 - L11 RISC-V Interpreter

6 Full Interpreter (put it all together) module mkinterpreter(empty); Reg#(Word) pc <- mkreg(0); RFile2R1W rf <- mkrfile2r1w; MagicMemory imem <- mkmagicmemory; // instruction memory MagicMemory dmem <- mkmagicmemory; // data memory rule dointerpreter; let inst <- imem.req(memreq{op: Ld, addr: pc, data:?}); let dinst = decode(inst); let rval1 = rf.rd1(dinst.src1); let rval2 = rf.rd2(dinst.src2); let einst = execute(dinst, rval1, rval2, pc); updatestate(einst, pc, rf, dmem); endrule endmodule function Action updatestate(execinst einst, Reg#(Word) pc, RFile2R1W rf, MagicMemory dmem); return (action // memory access let data = einst.data; if (einst.itype == LOAD) begin data <- dmem.req(memreq{op: Ld, addr: einst.addr, data:?}); end else if (einst.itype == STORE) begin let dummy <- dmem.req(memreq{op: St, addr: einst.addr, data: data}); end // register file write if (isvalid(einst.dst)) rf.wr(frommaybe(?, einst.dst), data); // pc update pc <= einst.nextpc; endaction); Worksheet - 6 of 10 - L11 RISC-V Interpreter

7 Problem 1. Decode the following 32-bit RISC-V instructions: rs2 rs1 000 rd SUB x3, x4, x1 Note that because inst[30] = 1 this is a sub rather than add operation shamt rs1 101 rd SRAI x7, x2, 5 Note that shift instructions only use the bottom 5 bits of the immediate as the actual shift amount Worksheet - 7 of 10 - L11 RISC-V Interpreter

8 Problem 2. Implement the signedlt(a, b) and signedge(a, b) functions that are used by the alu function definition. The function specifications are as follows: function Bool signedlt(word a, Word b); function Bool signedge(word a, Word b); function Bool signedlt(word a, Word b); Int#(32) inta = unpack(a); Int#(32) intb = unpack(b); return inta < intb; function Bool signedge(word a, Word b); Int#(32) inta = unpack(a); Int#(32) intb = unpack(b); return inta >= intb; Worksheet - 8 of 10 - L11 RISC-V Interpreter

9 Problem 3. Add a branch if greater-than (BGT) instruction to the provided RISC-V processor. The instruction encoding should match other branch instructions, but have funct3 = 3 b010. Bit#(7) opbranch = 7 b ; Bit#(3) fngt = 3 b010; function DecodedInst decode(bit#(32) inst); Bit#(7) opcode = inst[6:0]; Bit#(3) funct3 = inst[14:12]; Bit#(5) rs1 = inst[19:15]; Bit#(5) rs2 = inst[24:20]; Word immb = signextend({ inst[31], inst[7], inst[30:25], inst[11:8], 1'b0}); DecodedInst dinst =?; dinst.itype = Unsupported; // Unsupported by default case (opcode) opbranch: case (funct3): fngt: dinst = DecodedInst{dst: Invalid, src1: src1, src2: src2, imm: immb, brfunc: Gt, alufunc:?, itype: BRANCH }; // Lots of omitted code from Lab 5 endcase return dinst; typedef enum {Eq, Neq, Lt, Ltu, Ge, Geu, Gt} BrFunc deriving (Bits, Eq, FShow); function Bool signedgt(word a, Word b); Int#(32) aint = unpack(a); Int#(32) bint = unpack(b); return aint > bint; function Bool alubr(word a, Word b, BrFunc brfunc); Bool res = case (brfunc) Eq: (a == b); Neq: (a!= b); Lt: signedlt(a, b); Ltu: (a < b); Ge: signedge(a, b); Geu: (a >= b); Gt: signedgt(a, b); endcase; return res; Worksheet - 9 of 10 - L11 RISC-V Interpreter

10 Problem 4. Assume that alubr has been replaced with the new branch ALU function, newalubr, shown below. This new branch ALU is controlled by two control signals: newbrfunc and invert. When the result of this function is true, the next PC is going to be computed as pc + imm. typedef enum {Eq, Lt, Ltu} NewBrFunc deriving (Bits, Eq, FShow); function Bool newalubr(word a, Word b, NewBrFunc newbrfunc, Bool negate); Bool res = case (brfunc) Eq: (a == b); Lt: signedlt(a, b); Ltu: (a < b); endcase; return negate?!res : res; A) Fill in the decoding table below to specify what the control signals should be for each funct3. Write an X in the table for entries that don t matter. funct3 newbrfunc invert 3 b000 Eq False BEQ 3 b001 Eq True BNE 3 b010 X X 3 b011 X X 3 b100 Lt False BLT 3 b101 Lt True BGE 3 b110 Ltu False BLTU 3 b111 Ltu True BGEU Worksheet - 10 of 10 - L11 RISC-V Interpreter

6.004 Recitation Problems L13 RISC-V Interpreter

6.004 Recitation Problems L13 RISC-V Interpreter Refer to the 6.004 ISA Reference Tables (Website > Resources) for details about each instruction. RISC-V Interpreter: Components Register File typedef Bit#(32)