DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 2
|
|
- Florence Bridges
- 5 years ago
- Views:
Transcription
1 DIGITAL LOGIC WITH VHDL (Fall 23) Unit 2 Use of std_logic_vector. CONCURRENT DESCRIPTION with-select, when-else statements Examples: multiplexor, decoder.
2 std_logic_vector In the example, we use the std_logic_vector tpe for an input signal. use ieee.std_logic_64.all; entit test is port ( A: in std_logic_vector (3 downto ); -- A: A3 A2 A A : out std_logic); A = A 3 A 2 A A end test; architecture struct of test is -- The circuit represents an AND gate -- with 4 inputs: A(3), A(2), A(), A() <= A(3) and A(2) and A() and A(); A(3) A(2) A() A()
3 std_logic_vector In the example, we use the std_logic_vector tpe for an output signal. use ieee.std_logic_64.all; entit tst is port ( A,B: in std_logic; F: out std_logic_vector (3 downto ); -- F: F3 F2 F F end tst; architecture struct of tst is A B F = F 3 F 2 F F F(3) F() <= A and B; F() <= A xor B; F(2) <= A or B; F(3) <= not(a); F(2) F() F()
4 CONCURRENT DESCRIPTION In this description, circuits are specified in an structured fashion. The order of the statements is irrelevant: all the statements represent circuits that are working at the same time. This tpe of description is well-suited for combinatorial circuits. The use of sentences with and, or, xor, nand, nor, xnor, and not is a basic instance of the concurrent description. It is sometimes called horizontal description. In Unit 4, the so-called structural description is just a generalization of the concurrent description. Since we alread know how to build circuits based on logic gates, we now present two concurrent assignment statements (with select, when else), which are far more powerful than the statements with logic gates when it comes to describe complex circuits.
5 CONCURRENT ASSIGNMENT STATEMENTS: a b Selected Signal Assignment: WITH-SELECT: This statement allows assigning values to a signal based on certain criterion. MUX 2-to-: s s a b = s(a b + a b) + s(a b + a b) = sa + sb with s select: 's'specifies the selection criterion when specifies the value assigned to '' for each value of 's' when others: we need to include all the possible values of 's', that are 9 according to std_logic tpe. s a b use ieee.std_logic_64.all; entit m_mux2 is port ( a, b, s: in std_logic; : out std_logic); end m_mux2; architecture st of m_mux2 is with s select <= a when '', b when others; end st;
6 Selected Signal Assignment (WITH SELECT): MUX 8-to- use ieee.std_logic_64.all; a b c d e f g h s 3 entit m_mux8 is port ( a,b,c,d,e,f,g,h: in std_logic; s: in std_logic_vector (2 downto ); : out std_logic); end m_mux8; architecture struct of m_mux8 is with s select <= a when "", -- note ',' instead of ';' b when "", c when "", d when "", e when "", f when "", g when "", h when others;
7 a b c d e f Selected Signal Assignment(WITH SELECT): MUX 6-to s 3 Value '-': Don't care output It helps the snthesizer to optimize the circuit use ieee.std_logic_64.all; entit m_mux6 is port ( a,b,c,d,e,f: in std_logic; s: in std_logic_vector (2 downto ); : out std_logic); end m_mux6; architecture struct of m_mux6 is with s select <= a when "", b when "", c when "", d when "", e when "", f when "", '-' when others;
8 bcd leds 7-segment DECODER (outputs >= inputs) use ieee.std_logic_64.all; entit sevenseg is port ( bcd: in std_logic_vector (3 downto ); sevenseg: out std_logic_vector (6 downto ); EN: in std_logic_vector (3 downto )); end sevenseg; EN 4 7-seg decoder architecture struct of sevenseg is signal leds: std_logic_vector (6 downto ); -- a b c d e f g -- leds6 leds5 leds4 leds3 leds2 leds leds with bcd select leds <= "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", " " when others; -- Nexs3: LEDs are active low. -- Each 7-seg displa has an active-low enable EN <= ""; sevenseg <= not(leds);
9 Decoder 2-to-4 with enable: use ieee.std_logic_64.all; w E 2 DECODER 4 entit dec2to4 is port (w: in std_logic_vector ( downto ); E: in std_logic; : out std_logic_vector (3 downto )); end dec2to4; architecture struct of dec2to4 is signal Ew: std_logic_vector (2 downto ); Ew <= E & w; -- concatenation with Ew select <= "" when "", "" when "", "" when "", "" when "", "" when others;
10 CONCURRENT ASSIGNMENT STATEMENTS : Conditional signal assignment: WHEN - ELSE: Similarl to the selected signal assignment, this statement allows a signal to take one out of man values based on a certain condition. The sntax however is different and it allows to describe circuits in a more compact fashion. Example: MUX 2-to- a b If the condition on when is FALSE, we assign a value to after else. This assignment can also be conditioned b another when-else clause (see next example) s use ieee.std_logic_64.all; entit mux2_cond is port ( a, b, s: in std_logic; : out std_logic); end mux2_cond; architecture est of mux2_cond is <= a when s = '' else b; end est;
11 Conditional signal assignment (WHEN - ELSE): Example: MUX 4-to- a b c d s Note that the assignment on b is conditioned b another when else clause. Same for c. Onl the assignemnt of d is not conditioned. There is no limit to the number of nested conditions use ieee.std_logic_64.all; entit mux4_cond is port (a, b, c, d: in std_logic; s: in std_logic_vector ( downto ); : out std_logic); end mux4_cond; architecture est of mux4_cond is <= a when s = "" else b when s = "" else c when s = "" else d; end est;
12 w3 w2 w w w 3 Conditional signal assignment (WHEN - ELSE): Example: Priorit Encoder 4-to-2 PRIORITY ENCODER when-else has a priorit level, thus it is eas to describe a priorit encoder. With with-select, describing this circuit would be ver tedious. z w 2 w w z x x x x x x use ieee.std_logic_64.all; entit m_prienc is port ( w: in std_logic_vector (3 downto ); : out std_logic_vector ( downto ); z: out std_logic); end m_prienc; architecture struct of m_prienc is <= "" when w(3) = '' else "" when w(2) = '' else "" when w() = '' else ""; z <= '' when w = "" else ''; -- If no input is '', z is ''
13 Conditional signal assignment (WHEN - ELSE): Example: 4-bit comparator A B COMPA- RATOR AeqB AgB AlB Note the use of the operators =, >, < to compare numbers Alwas indicate what tpe of numbers we are working with. In the example we are using unsigned numbers. For 2 s complement, use signed. use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; -- unsigned #s entit m_comp is port ( A,B: in std_logic_vector (3 downto ); AeqB, AgB, AlB: out std_logic); end m_comp; architecture struct of m_comp is AeqB <= '' when A = B else ''; AgB <= '' when A > B else ''; AlB <= '' when A < B else '';
14 Conditional Signal Assignment (WHEN - ELSE): Example: Demultiplexor use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; x 2 3 a b c d entit m_demux is port ( s: in std_logic_vector ( downto ); x: in std_logic; a,b,c,d: out std_logic); end m_demux; 2 s architecture struct of m_demux is a <= x when s = "" else ''; b <= x when s = "" else ''; c <= x when s = "" else ''; d <= x when s = "" else '';
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3 BEHAVIORAL DESCRIPTION Asynchronous processes (decoder, mux, encoder, etc): if-else, case, for-loop. BEHAVIORAL DESCRIPTION (OR SEQUENTIAL) In this design style,
More informationDigital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
More informationDIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 3
DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 3 BEHAVIORAL DESCRIPTION Asynchronous processes (decoder, mux, encoder, etc): if-else, case, for-loop. Arithmetic expressions inside asynchronous processes.
More informationECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University
ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design:
More informationSolutions - Homework 2 (Due date: October 9:30 am) Presentation and clarity are very important!
ECE-8L: Computer Logic Design Fall Solutions - Homework (Due date: October rd @ 9: am) Presentation and clarit are ver important! PROBLEM ( PTS) Complete the following table. Use the fewest number of bits
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationChapter 6 Combinational-Circuit Building Blocks
Chapter 6 Combinational-Circuit Building Blocks Commonly used combinational building blocks in design of large circuits: Multiplexers Decoders Encoders Comparators Arithmetic circuits Multiplexers A multiplexer
More informationELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University
ECE 545 Lecture 5 Data Flow Modeling in VHDL George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 2 Types of VHDL Description
More informationLecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1
Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The
More informationSolutions - Homework 4 (Due date: November 9:30 am) Presentation and clarity are very important!
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 Solutions - Homework 4 (Due date: November 6th @ 9:3 am) Presentation and clarity are very important!
More informationLab 3: Standard Combinational Components
Lab 3: Standard Combinational Components Purpose In this lab you will implement several combinational circuits on the DE1 development board to test and verify their operations. Introduction Using a high-level
More informationVHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2
VHDL 2 Combinational Logic Circuits Reference: Roth/John Text: Chapter 2 Combinational logic -- Behavior can be specified as concurrent signal assignments -- These model concurrent operation of hardware
More informationVery High Speed Integrated Circuit Har dware Description Language
Very High Speed Integrated Circuit Har dware Description Language Industry standard language to describe hardware Originated from work in 70 s & 80 s by the U.S. Departm ent of Defence Root : ADA Language
More informationACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1
ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2015-2016) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying
More informationAbi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
More informationHardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
More informationIntroduction to VHDL #1
ECE 3220 Digital Design with VHDL Introduction to VHDL #1 Lecture 3 Introduction to VHDL The two Hardware Description Languages that are most often used in industry are: n VHDL n Verilog you will learn
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines FINITE STATE MACHINES (FSMs) Classification: Moore Machine: Outputs depend only on the current state
More informationDIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6
DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines Algorithmic State Machine (ASM) charts FINITE STATE MACHINES (FSMs) Classification: Moore Machine:
More informationCHAPTER NINE - MSI Logic Circuits
CHAPTER NINE - MSI Logic Circuits 9. (a) All of the outputs are HIGH. (b) O =, O- O7 = (c) O - O6 =, O7 =. (d) Same as (a). 9.2 Inputs = 6: Outputs = 64 9.3 (a) [ O6] -> A2=, A=, A=, E3=, E2 =, E= (b)
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION
More informationCSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\
CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,
More informationContents. Appendix D VHDL Summary Page 1 of 23
Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data
More informationIntroduction to VHDL #3
ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential)
More informationLogic and Computer Design Fundamentals VHDL. Part 1 Chapter 4 Basics and Constructs
Logic and Computer Design Fundamentals VHDL Part Chapter 4 Basics and Constructs Charles Kime & Thomas Kaminski 24 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Overview
More informationExperiment 8 Introduction to VHDL
Experiment 8 Introduction to VHDL Objectives: Upon completion of this laboratory exercise, you should be able to: Enter a simple combinational logic circuit in VHDL using the Quartus II Text Editor. Assign
More informationLattice VHDL Training
Lattice Part I February 2000 1 VHDL Basic Modeling Structure February 2000 2 VHDL Design Description VHDL language describes a digital system as a set of modular blocks. Each modular block is described
More informationVHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit
VHDL VHDL Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL Alternative (Student Generated) Definition Very Hard Digital Logic language VHDL Design
More information!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"
!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"!!"#$%&'#()#*+"+#,-."/0110#230#4."50",+"+#)6# 6+-+#(.6+-0#)4475.8)60#0/#.65-0#230#9+**+"+# 2.48).-0#(.6+-0#! 2+"*5."5*:#,."/0110#;)**0! *),".6*:#-.99-0*0"5."+#2+660,.40"5)#;)*)2)#
More informationIntroduction to VHDL
Introduction to VHDL Agenda Introduce VHDL Basic VHDL constructs Implementing circuit functions Logic, Muxes Clocked Circuits Counters, Shifters State Machines FPGA design and implementation issues FPGA
More informationVHDL for FPGA Design. by : Mohamed Samy
VHDL for FPGA Design by : Mohamed Samy VHDL Vhdl is Case insensitive myvar = myvar = MYVAR IF = if = if Comments start with -- Comments can exist anywhere in the line Semi colon indicates the end of statements
More informationEEL 4712 Digital Design Test 1 Spring Semester 2007
IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. COVER SHEET: Problem: Points: 1 (15 pts) 2 (20 pts) Total 3 (15 pts) 4 (18 pts)
More informationReview of Digital Design with VHDL
Review of Digital Design with VHDL Digital World Digital world is a world of 0 and 1 Each binary digit is called a bit Eight consecutive bits are called a byte Hexadecimal (base 16) representation for
More informationENGIN 241 Digital Systems with Lab
ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided
More informationBasic Language Concepts
Basic Language Concepts Sudhakar Yalamanchili, Georgia Institute of Technology ECE 4170 (1) Describing Design Entities a sum b carry Primary programming abstraction is a design entity Register, logic block,
More informationUNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library :
UNIT I Introduction to VHDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming languages used to model a digital system by dataflow, behavioral
More information5. 0 VHDL OPERATORS. The above classes are arranged in increasing priority when parentheses are not used.
Filename= ch5.doc 5. 0 VHDL OPERATORS There are seven groups of predefined VHDL operators: 1. Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < >= 3. Shifts operators:
More informationControl Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN
Control Unit: Binary Multiplier Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Example: Binary Multiplier Two versions Hardwired control Microprogrammed
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationDepartment of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING. Fifth Semester. Subject: VHDL Programming
Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING Fifth Semester Subject: VHDL Programming Contact Hours/Week : 04 Contact Hours/Semester : 64 CONTENTS No. Of
More informationLecture 4. VHDL Fundamentals. George Mason University
Lecture 4 VHDL Fundamentals George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL 2 Design Entity ECE 448 FPGA and ASIC Design with
More informationEEL 4712 Digital Design Test 1 Spring Semester 2008
IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. Also, as always, the best answer gets the most points. COVER SHEET: Problem:
More informationDesign a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Output Sum(4 bits) Adder. Output carry(1 bit)
Csc 343 Lab 2 Sep 28. 07 Objective: Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Structure: Input A (4 bits) Input B (4 bit) Adder Output Sum(4 bits) Output carry(1 bit) input cin
More informationIntroduction to VHDL. Main language concepts
Introduction to VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Current standard is IEEE 1076-1993 (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab
More informationComputer-Aided Digital System Design VHDL
بس م اهلل الر حم ن الر حی م Iran University of Science and Technology Department of Computer Engineering Computer-Aided Digital System Design VHDL Ramin Rajaei ramin_rajaei@ee.sharif.edu Modeling Styles
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationChapter Three. Digital Components
Chapter Three 3.1. Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. The binary values of the outputs are a function of the binary
More informationLecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when
More informationDepartment of Electronics & Communication Engineering Lab Manual E-CAD Lab
Department of Electronics & Communication Engineering Lab Manual E-CAD Lab Prasad V. Potluri Siddhartha Institute of Technology (Sponsored by: Siddhartha Academy of General & Technical Education) Affiliated
More informationCSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014
CSE 260 Introduction to Digital Logic and Computer Design Jonathan Turner Exam 1 Your name 2/13/2014 1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C +D)(B+D ) directly (do not
More informationLecture 3. VHDL Design Units and Methods. Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory
Lecture 3 Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory BTF4220 - Digital Electronics 2 Mar. 06, 2015 Bern University of Applied Sciences Agenda Rev. ec317bd
More informationThe block diagram representation is given below: The output equation of a 2x1 multiplexer is given below:
Experiment-3: Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. multiplexer b. De-Multiplexer Objective: i. To learn the VHDL coding for Multiplexer and
More informationVHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit
More informationECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
More informationVHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents
VHDL Testbench Tutorial 1 Contents 1 VHDL Testbench 2 Test Bench Syntax 3 Testbench Example: VHDL Code for Up Down Binary Counter 4 VHDL Testbench code for up down binary counter 5 Testbench Waveform for
More informationPart 4: VHDL for sequential circuits. Introduction to Modeling and Verification of Digital Systems. Memory elements. Sequential circuits
M1 Informatique / MOSIG Introduction to Modeling and erification of Digital Systems Part 4: HDL for sequential circuits Laurence PIERRE http://users-tima.imag.fr/amfors/lpierre/m1arc 2017/2018 81 Sequential
More informationOutline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.
Outline CPE/EE 422/522 Advanced Logic Design L05 Electrical and Computer Engineering University of Alabama in Huntsville What we know Combinational Networks Sequential Networks: Basic Building Blocks,
More informationIntroduction to VHDL #2
ECE 322 Digital Design with VHDL Introduction to VHDL #2 Lecture 4 Signal Assignment Statements Forms of signal assignment statements: Simple Concurrent Assignment Selected Assignment Conditional Assignment
More informationLecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
More informationCS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
More informationInferring Storage Elements
Inferring Storage Elements In our designs, we usually use flip-flops as our storage elements. Sometimes we use latches, but not often. Latches are smaller in size, but create special, often difficult situations
More informationCMPT 250: Computer Architecture. Using LogicWorks 5. Tutorial Part 1. Somsubhra Sharangi
CMPT 250: Computer Architecture Using LogicWorks 5 Tutorial Part 1 Somsubhra Sharangi What is VHDL? A high level language to describe digital circuit Different that a programming language ( such as Java)
More informationExperiment 0 OR3 Gate ECE 332 Section 000 Dr. Ron Hayne June 8, 2003
Experiment 0 OR3 Gate ECE 332 Section 000 Dr. Ron Hayne June 8, 2003 On my honor I have neither received nor given aid on this report. Signed: Ronald J. Hayne Part I Description of the Experiment Experiment
More information14:332:331. Computer Architecture and Assembly Language Fall Week 5
14:3:331 Computer Architecture and Assembly Language Fall 2003 Week 5 [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] 331 W05.1 Spring 2005 Head s Up This week
More informationSynthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden
Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March
More information1. What is y-chart? ans: The y- chart consists of three domains:- behavioral, structural and geometrical.
SECTION- A Short questions: (each 2 marks) 1. What is y-chart? ans: The y- chart consists of three domains:- behavioral, structural and geometrical. 2. What is fabrication? ans: It is the process used
More informationLecture 3. VHDL Design Units and Methods. Notes. Notes. Notes
Lecture Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory BTF4220 - Digital Electronics 2 Mar. 06, 2015 Bern University of Applied Sciences Agenda Rev. ec17bd.2
More informationECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationthat system. weighted value associated with it. numbers. a number. the absence of a signal. MECH 1500 Quiz 2 Review Name: Class: Date:
Name: Class: Date: MECH 1500 Quiz 2 Review True/False Indicate whether the statement is true or false. 1. The decimal system uses the number 9 as its base. 2. All digital computing devices perform operations
More informationVHDL: RTL Synthesis Basics. 1 of 59
VHDL: RTL Synthesis Basics 1 of 59 Goals To learn the basics of RTL synthesis. To be able to synthesize a digital system, given its VHDL model. To be able to relate VHDL code to its synthesized output.
More informationCombinational Logic COMB. LOGIC BLOCK. A Combinational Logic Block is one where the outputs depend only on the current inputs
Combinational Logic A Combinational Logic Block is one where the outputs depend only on the current inputs COMB. LOGIC BLOCK A combinational logic block can be implemented using simple gates or lookup
More informationConstructing VHDL Models with CSA
Constructing VHDL Models with CSA List all components (e.g., gate) inclusive propagation delays. Identify input/output signals as input/output ports. All remaining signals are internal signals. Identify
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 4
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 4 Integer DATA TYPE STRUCTURAL DESCRIPTION Hierarchical deign: port-map, for-generate, ifgenerate. Eample: Adder, comparator, multiplier, Look-up Table, Barrel
More informationVHDL Examples Mohamed Zaky
VHDL Examples By Mohamed Zaky (mz_rasmy@yahoo.co.uk) 1 Half Adder The Half Adder simply adds 2 input bits, to produce a sum & carry output. Here we want to add A + B to produce Sum (S) and carry (C). A
More informationECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles
ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1
DIGITAL LOGIC WITH VHDL (Fall 23) Unit DESIGN FLOW DATA TYPES LOGIC GATES WITH VHDL TESTBENCH GENERATION DESIGN FLOW Design Entry: We specify the logic circuit using a Hardware Description Language (e.g.,
More informationCS303 LOGIC DESIGN FINAL EXAM
JANUARY 2017. CS303 LOGIC DESIGN FINAL EXAM STUDENT NAME & ID: DATE: Instructions: Examination time: 100 min. Write your name and student number in the space provided above. This examination is closed
More informationSRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI)
SRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI) VLSI LAB MANUAL ECE DEPARTMENT Introduction to VHDL It is a hardware description language that can be used to model a digital system
More informationThe University of Alabama in Huntsville ECE Department CPE Final Exam Solution Spring 2004
The University of Alabama in Huntsville ECE Department CPE 526 01 Final Exam Solution Spring 2004 1. (15 points) An old Thunderbird car has three left and three right tail lights, which flash in unique
More informationIE1204 Digital Design L7: Combinational circuits, Introduction to VHDL
IE24 Digital Design L7: Combinational circuits, Introduction to VHDL Elena Dubrova KTH / ICT / ES dubrova@kth.se This lecture BV 38-339, 6-65, 28-29,34-365 IE24 Digital Design, HT 24 2 The multiplexer
More informationChapter 2 Basic Logic Circuits and VHDL Description
Chapter 2 Basic Logic Circuits and VHDL Description We cannot solve our problems with the same thinking we used when we created them. ----- Albert Einstein Like a C or C++ programmer don t apply the logic.
More informationEECE-4740/5740 Advanced VHDL and FPGA Design. Lecture 3 Concurrent and sequential statements
EECE-4740/5740 Advanced VHDL and FPGA Design Lecture 3 Concurrent and sequential statements Cristinel Ababei Marquette University Department of Electrical and Computer Engineering Overview Components hierarchy
More informationReview. LIBRARY list of library names; USE library.package.object; ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type;
LIBRARY list of library names; USE library.package.object; Review ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type; signal_name(s) : mode signal_type); END ENTITY entity_name;
More informationVHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY. Design descriptions & design constructions examples are taken from foundation series examples
1 VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY Design descriptions & design constructions examples are taken from foundation series examples 2 What we have done in Lab 1 entity AND_Gate is port ( a : in
More informationHardware Modeling. VHDL Syntax. Vienna University of Technology Department of Computer Engineering ECS Group
Hardware Modeling VHDL Syntax Vienna University of Technology Department of Computer Engineering ECS Group Contents Identifiers Types & Attributes Operators Sequential Statements Subroutines 2 Identifiers
More informationECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University
ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential
More informationLecture 4. VHDL Fundamentals. Required reading. Example: NAND Gate. Design Entity. Example VHDL Code. Design Entity
Required reading Lecture 4 VHDL Fundamentals P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL George Mason University 2 Example: NAND Gate Design Entity a b z a b z 0
More informationECOM4311 Digital Systems Design
ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1 Agenda 1. VHDL : Data Types Cont d 2. VHDL : Operators 3. VHDL : Signal Assignments
More informationVHDL in 1h. Martin Schöberl
VHDL in 1h Martin Schöberl VHDL /= C, Java, Think in hardware All constructs run concurrent Different from software programming Forget the simulation explanation VHDL is complex We use only a small subset
More informationGetting Started with VHDL
Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component Entities can be primitive objects or complex objects Architectures are associated
More informationDESCRIPTION OF DIGITAL CIRCUITS USING VHDL
DESCRIPTION OF DIGITAL CIRCUITS USING VHDL Combinatinal circuits Sequential circuits Design organization. Generic design Iterative operations Authors: Luis Entrena Arrontes, Celia López, Mario García,
More informationSolutions - Homework 2 (Due date: February 5 5:30 pm) Presentation and clarity are very important! Show your procedure!
Solutions - Homework (Due date: Februar 5 th @ 5: pm) Presentation and clarit are ver important! Show our procedure! PROBLEM ( PTS) In these problems, ou MUST show our conversion procedure. a) Convert
More informationVHDL par Ahcène Bounceur VHDL
VHDL Ahcène Bounceur 2009 Plan de travail 1. Introduction au langage 2. Prise en main 3. Machine à état 4. Implémentation sur FPGA 1 VHDL Introduction au langage Ahcène Bounceur VHDL VHIC (Very High-speed
More informationCprE 583 Reconfigurable Computing
Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering
More informationObjective Design a 4*4 register file and test it on VSIM, QUARTUS, and UP3 board.
Csc343 LAB Register File Objective Design a 4*4 register file and test it on VSIM, QUARTUS, and UP3 board. What is a register file A register file is the central storage of a microprocessor. Most operations
More informationConcurrent Signal Assignment Statements (CSAs)
Concurrent Signal Assignment Statements (CSAs) Digital systems operate with concurrent signals Signals are assigned values at a specific point in time. VHDL uses signal assignment statements Specify value
More informationDeclarations of Components and Entities are similar Components are virtual design entities entity OR_3 is
Reserved Words component OR_3 port (A,B,C: in bit; Z: out bit); end component ; Reserved Words Declarations of Components and Entities are similar Components are virtual design entities entity OR_3 is
More information