Soft-error and Variability Resilience in Dependable VLSI Platform. Hidetoshi Onodera Kyoto University
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1 Soft-error and Variability Resilience in Dependable VLSI Platform Hidetoshi Onodera Kyoto University
2 Outline: Soft-error and Variability Resilience 1 Background Overview: Dependable VLSI Platform Circuit-level Resilience Soft-error tolerant FF Variation tolerant FF Variability compensation by localized body-biasing Architecture-level Soft-error Resilience by Reconfigurable Array Platform SOC and C-based Design Tools Summary
3 Id_sat Reduction Background: Overall Design Technology Challenges (ITRS2011) 2 Design productivity Power consumption Manufacturability Performance/power variability, device parameter variability, lithography limitations Interference Reliability and resilience Logic/circuit/physical: MTTF-aware design, built-in-self-repair, softerror correction Manufacturability Alpha particle Thermal High energy neutron neutron Nuclear reaction Variability Aging Soft Errors
4 Reliability Dependable VLSI Platform using Robust Fabrics Target: Resolving the challenges in Manufacturability, Variability, Aging, Soft errors, NRE-cost explosion Method: Collaborative researches for Layout/Circuit/Architecture/Mapping Layout: Robust structure for enhanced manufacturability Circuit:Adaptive performance tuning Architecture:Adaptive redundancy in reconfigurable architecture Mapping: dependability-aware HLS and mapping from C Goal: Dependability-aware VLSI Platform Dependable Processor DMAC Reconfigurable Cluster Array (FRRARY) Reconfigurable Array I/F SRAM (Local Memory) Dependable VLSI Platform WISHBONE External I/Fs Direct I/O Ext. I/O Application in C Digital Filter (FIR, IIR), CRC, FEC (LDPC,Viterbi), Cipher (AES), Reliability-aware Mapping (Controller, etc.) Mapping Reliability: Regular Area: Min. Reliability: Max Area Reliability: High Area: Small Reliability Area Tradeoff Area-effective Mapping (Datapath etc.) Reliability & Area aware Mapping (I/Os, etc.) Reconfigurable Array Architecture using Robust Fabrics 3
5 Target Applications 4 Application Streaming Automotive Space/Aero Base Station Storage Dependability Aspects Cost Performance Manufacturability Low Power Programmability Soft Error Resilience Proposed Key Technology Dependable VLSI Platform Robust Fabric Flexible Reliability Reconfigurable Array Reliability-aware Mapping Dependable Processor Conventional Technology Cell Library FPGA Place and Route Embedded Processor
6 Outline: Soft-error and Variability Resilience 5 Background Overview: Dependable VLSI Platform Circuit-level Resilience Soft-error tolerant FF Variation tolerant FF Variability compensation by localized body-biasing Architecture-level Soft-error Resilience by Reconfigurable Array Platform SOC and C-based Design Tools Summary
7 Soft-error Tolerant FF: BCDMR FF 6 Delayed Sampling for SET removal Data Redundancy in 2 latches and c-element Improvement of BISER Eliminate vulnerability to SET at the master C-element. BISER: Mitra, et.al., Computer, No.2, BCDMR: Furuta, et.al., VLSI Ckt., Yamanoto, et.al, Trans. Nuclear Sci., No6, 2011.
8 #Errors/1kbit Measured Resilience for Soft Errors # of errors in 50min. Neutron Irradiation for 202k BCDMR FFs M 300M 800M 1G Clock Frequency [Hz] D FF BCDMR FF well Clock Freq.[MHz] twin triple Conventional FF: #errors:260 a-particle irradiation test for 5 min. No error is observed in operating condition Neutron irradiation test for 50 min. No error is observed in 202,000 BCDMR FFs (65nm) At least 260x stronger than conventional FFs
9 Outline: Soft-error and Variability Resilience 8 Background Overview: Dependable VLSI Platform Circuit-level Resilience Soft-error tolerant FF Variation tolerant FF Variability compensation by localized body-biasing Architecture-level Soft-error Resilience by Reconfigurable Array Platform SOC and C-based Design Tools Summary
10 Variation Tolerant FF 9 Vulnerability of D-FF Timing Characteristics under WID Random Variation Simulated D-to-Q Delay and Setup Time at the SS and SKEW Corners Simulated D-to-Q Delay and Setup Time at the SS and SKEW Corners Due to the skewed delay characteristics between the latching loop and the clock drivers Fast Sunagawa, et.al. SOCC2009
11 Variation Tolerant FF Variation Tolerant FF Design Enhanced Clock Driver TSPC (Single Phase Clock) Oversized(x2) DFF Test Structure TSPC Standard Clock-Driver Enhanced TSPC 1.2V Operation 8% Faster 29% less variation 18% Faster 2% Less variation Clock-Driver Enhanced Standard TSPC 0.7V Operation 17% Faster 55% Less variation 43% Faster 37% Less variation Maximum Operating Frequency for 3240 FFs in 65nm 10
12 Outline: Soft-error and Variability Resilience Background Overview: Dependable VLSI Platform Circuit-level Resilience Soft-error tolerant FF Variation tolerant FF Variability compensation by localized body-biasing Architecture-level Soft-error Resilience by Reconfigurable Array Platform SOC and C-based Design Tools Summary 11
13 12 Variability Compensation by Localized Body Biasing Features Variability compensation by fine grain ( ~0.1mm 2 ) adaptive body biasing SS, SF, FS corner performance can be compensated to Typical Area overhead less than 3% Developed IPs All-digital pmos/nmos monitors Cell-base-designed body biasing circuits Other Features WID as well as D2D variability compensation Compatibility with Cell-base design 12
14 Variability Compensation by Localized Body Biasing Performance Compensation in Corner Chips(SS, SF, FS, FF, TT) at Vdd=0.7V 13 nmos/pmos FET Monitor Cell-based Design
15 Outline: Soft-error and Variability Resilience 14 Background Overview: Dependable VLSI Platform Circuit-level Resilience Soft-error tolerant FF Variation tolerant FF Variability compensation by localized body-biasing Architecture-level Soft-error Resilience by Reconfigurable Array Platform SOC and C-based Design Tools Summary
16 Reconfigurable Architecture with Flexible Reliability 15 Dependable Processor DMAC Reconfigurable Cluster Array (FRRAry) Reconfigurable Array I/F SRAM (Local Memory) WISHBONE External I/Fs SDRAM Ctrl PCI-e I/F GbE I/F etc. Direct I/O Ext. I/O Cluster array Cell Interconnect Cell Cluster core Cell Cluster Execution module Cell 0 Track0 Track1 Track2 Course/Fine-Grained Reconfigurable Architecture for Flexible Reliability Cluster core Execution module Execution module Cell 1 Cell 2
17 Reconfigurable Cluster Array Structure 16 Cluster array Cluster core Cell Interconnect Cell Cluster core Cell Cluster Execution module Execution module Execution module Cell 0 Cell 1 Cell 2 Track0 Track1 Track2 3 reliability levels TMR Context0 Context1 Context2 CFG0 CFG0 CFG0 CFG1 CFG1 CFG1 CFG2 CFG2 CFG2 triplicate d EM Cell 0 EM Cell 1 EM Cell 2 SMS CFG CFG CFG triplicate SMM CFG0 CFG1 CFG2 EM Level Redundancy Utilization Config. EM #contexts #cells TMR SMS SMM Cell 0 EM x3 Cell 0 x3
18 Combination of Coarse-grained and Finegrained Elements 17 Fine-grained element (LUT cluster) Dependable VLSI platform SoC Coarse-grained element (ALU cluster) Control Datapath Application mapping
19 Outline: Soft-error and Variability Resilience 18 Background Overview: Dependable VLSI Platform Circuit-level Resilience Soft-error tolerant FF Variation tolerant FF Variability compensation by localized body-biasing Architecture-level Soft-error Resilience by Reconfigurable Array Platform SOC and C-based Design Tools Summary
20 Dependable VLSI Platform SoC and C-based Design Tools 19 Dependable VLSI Platform Hardware Flexible Reliability Reconfigurable Array(FRRARY) Reliable Processor(DARA) Dependable VLSI Platform Software C-based High-Level Synthesis Reliability-aware Mapping Design Tools Dependable VLSI platform DARA - 65nm CMOS - 4.2mm x 4.2mm - #clusters: - ALU : 26 - Memory: 6 - LUT : 80 Memory clusters FRRARY LUT clusters ALU clusters DARA SpW SRAM FRRARY FRRARY I/F WISHBONE Ext. I/O Controller I/O FPGA Video I/O Camera In Display Dependable VLSI Platform SoC Evaluation system
21 Dependable VLSI Platform SoC and C-based Design Tools 20 ANSI-C Partitioning for acceleration and program translation ANSI-C for coarse grained reconfigurable array Selective redundancy configuration C program for processor Machine code program Behavioral synthesis (CWB) Data flow graph (DFG) Placement Routing Configuration data Reliable processor (DARA) Reconfigurable cluster array (FRRAry) Dependable VLSI platform C-based Design Flow Area-Reliability Trade-off by Partial TMR
22 a particle irradiation test 21
23 Soft-error and Variability Resilience in Dependable VLSI Platform 22 Reliability Target: Resolving the challenges in Manufacturability, Variability, Aging, Soft errors, NRE-cost explosion Solutions Fabrics: Soft-error and variation tolerant FFs Circuit:Adaptive performance tuning by localized body biasing Architecture:Adaptive redundancy in reconfigurable architecture Mapping: Dependability-aware HLS and mapping from C Reliability: Max Dependable Processor DMAC Reconfigurable Cluster Array (FRRARY) Reconfigurable Array I/F SRAM (Local Memory) Dependable VLSI Platform WISHBONE External I/Fs Direct I/O Ext. I/O Application in C Digital Filter (FIR, IIR), CRC, FEC (LDPC,Viterbi), Cipher (AES), Reliability-aware Mapping (Controller, etc.) Mapping Reliability: Regular Area: Min. Area Reliability: High Area: Small Reliability Area Tradeoff Area-effective Mapping (Datapath etc.) Reliability & Area aware Mapping (I/Os, etc.) Reconfigurable Array Architecture using Robust Fabrics
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