FPGA Power and Timing Optimization: Architecture, Process, and CAD

Transcription

1 FPGA Power and Timing Optimization: Architecture, Process, and CAD Chun Zhang 1, Lerong Cheng 2, Lingli Wang 1* and Jiarong Tong 1 1 State-Key-Lab of ASIC & System, Fudan University llwang@fudan.edu.cn 2 San Disk Corp

2 Outline Backgrounds FPGA Architecture Evaluation Low Power FPGA Architectures Conclusions References

3 Efficiency Comparison FPGA vs CPU 20+ speed-up: Elliptic curve cryptography: point multiplication operation 0.36 ms with a reconfigurable computing design implemented in an XC2V6000 FPGA at 66MHz ms for an optimized software implementation on a dualxeon computer at 2.6 GHz more than 540 times faster Factoring large numbers in breaking encryption schemes 28 times speed-up over a 200MHz UltraSparc workstation Significant speedups using FPGA-based reconfigurable hardware automatic target recognition string pattern matching transitive closure of dynamic graphs data compression etc With much lower power consumption

4 Our experiment: reconfigurable filter 总线宏 动态可重构区域 静态区域 PLB_DDR _CTRL SDRAM PPC 405 CPU ICAP

5 Reconfigurable Filter Specs and Results Hardware implementation on the Xilinx V4 FPGA Sampling frequency: 48 KHz; Low pass: fpass- 5K Hz, fstop- 9K Hz, Apass- 1 db, Astop- 80 db Band pass: fstop1-2k Hz, fpass1-6k Hz, fpass2-10k Hz, fstop2-14k Hz, Astop1, Astop2-80 db, Apass- 1 db High pass: fstop- 5.5K Hz, fpass- 10K Hz, Astop- 80 db, Apass- 1 db Filter modes are dynamically reconfigurable Software APIs provided for users Extend the OS to support hardware task scheduling Achieve 10+ speedup Including the configuration time compared with pure software implementation on the PPC

6 Typical CPU layout 6

7 Zoom-in to one core 7

8 Silicon area ratio for execution units ~10% only in the red area General-purpose architecture is not efficient for specific domains 8

9 Power Efficiency with CPUs Green Computing using CPUs? 下午 9 时 53 分 9

10 CPU vs GPU architecture GPU is very power-hungry!!! 10

11 From CPU to FPGA block array structure ALU memory break down Bus Routing connect up Coarse grain Fine grain configuration bits Logic block DFF (1-bit) routing resources FPGA basic block Advantage: avoid the bus communication bottleneck 11

12 FPGA block examples Hardware programming technology for configuration bits: SRAM, Anti-Fuse, Flash Logic: AND-OR/MUX/LUT Routing: various length and width of wires ALU memory 32-bit bus wire connections SRAM bits control: Functionality & connections SRAM bits AND/OR MUXLUT DFF (1-bit) routing wires 12

13 FPGA: programmable logic blocks in Quartus 13

14 FPGA routing resource in Xilinx FPGA Editor 14

15 Reconfigurable Hardware & Software Design at Fudan Chip Scale (K) FDP um FDP100K 0.35um FDP100K2 0.35um FDP250K-II 0.18um FDP um FDP um 30 FDP30K 0.6um

16 1 March 10, 2016 Dev. Board using our chip and software tools Used for the lab sessions for undergraduate/postgraduate courses Co-operating with a Taiwanese company

17 Outline Backgrounds FPGA Architecture Evaluation Low Power FPGA Architectures Conclusions References

18 Academic FPGA Architecture Island style Configurable IOs Configurable Logic Blocks (CLBs) Connection Boxes/blocks (CBs) Switch Boxes/blocks (SBs)

19 Configurable Logic Block (CLB)

20 Connection Block and Switch Block CB Connecting signals with CLBs SB Connecting signals of different routing channels

21 Mixed Level Power Model

22 Architecture Description Parameter Description N K Fc Fs W Cluster Size LUT Size Connectivity of Connection Box Connectivity of Switching Box Routing Channel Width.

23 Dynamic Power Equation & Optimization Dynamic power consumption Motivation Inter-CLB/LUT interconnects have much larger capacitance than intra-clb/lut resources Solution [J. Lamoureux, et al.] Absorbing those high transition density nodes into same CLB/LUT in different CAD tasks like technology mapping, placement, etc

24 Power Evaluation Framework fpgaeva-lp [Y. Lin et al.] Benchmark circuits Logic Optimization(ABC) Arch Spec Tech-Mapping (ABC) Timing-Driven Packing (TV-Pack) Placement & Routing (VPR) Parasitic Extraction Cycle-accurate Power Simulator Area Delay Power

25 Outline Backgrounds FPGA Architecture Evaluation Low Power FPGA Architectures Conclusions References

26 Low Power FPGA Architectures Static power reduction Region based power gating [A. Gayasen, et al.] Fine grained power gating [Y. Lin, et al.] Routing fabric power gating [S. Srinivasan, et al.][a. Lodi et al.] Dynamic power reduction Pre-defined dual-vdd architecture [F. Li, et al.] Configurable dual-vdd architecture [A. Gayasen et al.][f Li, et al.]

27 Power Gating

28 Vdd-programmable FPGA Vdd-programmable logic block Vdd selection Power-gating unused blocks Vdd-programmable switch Vdd-level conversion is needed when VddL drives VddH To avoid excessive leakage

29 Vdd-programmable Routing Switch Conventional routing switch Vdd-programmable routing switch Brute-force design [ICCAD 04] Two extra SRAM cells for each routing switch

30 Vdd-Programmable Connection Box Brute-force design [ICCAD 04] 2n extra SRAM cells for n connection switches

31 Total FPGA Energy (nj/cycle) Energy Breakdown & Optimization % 3.71% 16.03% 8.09% 49.89% 19.33% 2.70% 3.04% 26.22% 7.43% 42.84% 17.77% Logic Leakage Energy Logic Dynamic Energy Local Interconnect Leakage Energy Local Interconnect Dynamic Energy Global Interconnect Leakage Energy Global Interconnect Dynamic Energy 4.07% 3.92% 39.69% 9.81% 4.88% 37.62% Single-Vdd Dual-Vdd S-Vdd w/ PG D-Vdd w/o LS FPGA Architecture (N, K) = (12,4) 4.40% 4.32% 42.93% 10.81% 5.85% 31.70%

32 Outline Backgrounds FPGA Architecture Evaluation Low Power FPGA Architectures Conclusions References

33 Conclusions Timing efficiency FPGA-based reconfigurable computing provides efficiency About 20+ speed-up Compared with other platforms: CPU, GPU, DSP etc Power efficiency Low-power FPGA architectures Power-gating, Vdd-programmable architecture Process and architecture co-optimization Skipped here Shown in the paper

34 References References in the paper Architecture and CAD for deep-submicron FPGAs, Kluwer Academic Publishers, 1999 ( 深亚微米 FPGA 结构与 CAD 设计, 电子工业出版社, 2008 年 11 月 ) Low-Power Design of Nanometer FPGAs, Elsevier, 2010

35 Thank You! FPGA Power and Timing Optimization: Architecture, Process, and CAD Chun Zhang, Lerong Cheng, Lingli Wang* and Jiarong Tong

36 Comparison with ASICs Due to the large number of transistors to provide field programmability, FPGAs have more power, performance and area overhead Compared to ASICs for the same design, there are [T. Tuan et al.][i. Kuon et al.] 100x power difference 4.3x delay difference 40x area difference Low power solutions for FPGAs are therefore more important Better architectures Better CAD algorithms

37 Cycle-Accurate Power Simulator