Bank-interleaved cache or memory indexing does not require euclidean division

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1 Bak-iterleaved cache or memory idexig does ot require euclidea divisio Adré Sezec To cite this versio: Adré Sezec. Bak-iterleaved cache or memory idexig does ot require euclidea divisio. 11th Aual Workshop o Duplicatig, Decostructig ad Debukig, Ju 2015, Portlad, Uited States. Proceedig of the 11th Aual Workshop o Duplicatig, Decostructig ad Debukig, 2015, < <hal > HAL Id: hal Submitted o 2 Oct 2015 HAL is a multi-discipliary ope access archive for the deposit ad dissemiatio of scietific research documets, whether they are published or ot. The documets may come from teachig ad research istitutios i Frace or abroad, or from public or private research ceters. L archive ouverte pluridiscipliaire HAL, est destiée au dépôt et à la diffusio de documets scietifiques de iveau recherche, publiés ou o, émaat des établissemets d eseigemet et de recherche fraçais ou étragers, des laboratoires publics ou privés.

2 1 Bak-iterleaved cache or memory idexig does ot require euclidea divisio Adré Sezec, IRISA/INRIA, Campus de Beaulieu Rees Cedex, FRANCE adre.sezec@iria.fr Abstract Cocurret access to bak-iterleaved memory structure have bee studied for decades, particularly i the cotext of vector supercomputer systems. It is still commo belief that usig a umber of baks differet from 2 leads to isert a complex hardware icludig a o-trivial divider o the access path to the memory. I 1993, two idepedet studies [1], [2] were showig that through leveragig a very simple arithmetic result, the Chiese Remaider Theorem, this euclidea divisio is ot eeded whe the umber of baks is prime or simply odd. I the mid 90 s, the iterest for vector supercomputers faded ad the research topic disappeared. The iterest for bakiterleaved cache has reappeared recetly [3] i the GPU cotext. I this short paper, we exted the result from [1] ad we show that, regardless the umber of baks: Bak-iterleaved cache or memory idexig does ot require euclidea divisio. 1 INTRODUCTION The eed for cocurret access to data i memory structures has lead to the desig ad use of baked-iterleaved structures, first for mai memory, e.g. i vector supercomputers ad at secod step i caches. Optimizig parallel access to this bak-iterleaved memory structure has bee studied for decades particularly i the 80 s ad the early 90 s i the cotext of the access to strided vector processors [4], [5], [6], [7], [8], [9]. More recetly, similar studies have bee published i the cotext of bak-iterleaved caches for vector processors [10], [11] or GPU caches [3]. It was commo belief that for simple idexig of a bakiterleaved cache or memory, the umber of baks should be a power of 2, 2, sice otherwise complex arithmetic icludig a euclidea divisio ad euclidea modulo would be required [12], [6]. Two idepedet studies published i 1993 at the ISCA coferece [1], [2] poited out that for prime or odd umbers of baks such divisio is useless due a very simple arithmetic theorem, the Chiese Remaider Theorem. I a recet study, Diamod et al. [3] poit out that, i the cotext of GPU, the best umber of cache baks might ot be a power of two but may be ay other umber. They propose a optimized hardware mechaism to compute both modulo ad divisio at the same time. While their hardware proposal optimizes the implemetatio of bak-iterleaved cache or memory idexig if the euclidea divisio was required, such a euclidea divisio is useless. I this short paper, we exted the result from [1], [2] showig that the euclidea divisio is useless for idexig a bak-iterleaved memory or cache regardless the umber of baks. Notatio ad defiitio For coveiece, i the remaider of the paper, we will refer oly to a bak-iterleaved memory. The result i the paper also applies to bak-iterleaved caches. We will refer to a bak-iterleaved memory with a odd umber of baks as a odd memory system. Bak iterleavig i a memory or cache ca be implemeted at differet graularities; for istace 8-byte word o Cray vector supercomputers, cache blocks o vector microprocessor [11], 8-byte word for recet GPUs. For coveiece, we will refer to this graularity as word i the remaider of the paper. All the addresses that will be cosidered i this paper will be i words, therefore igorig offset i the word. 2 ODD MEMORY SYSTEMS DO NOT REQUIRE EU- CLIDEAN DIVISION This sectio summarizes the results published i [1]. 2.1 Usual data mappig i a bak-iterleaved memory The physical mappig of word at address A, 0 A < 2 c N o memory is defied by its bak umber m(a), 0 m(a) < N, ad its local address l(a), 0 l(a) < 2 c, i the bak. The most importat property that most maufacturers wat to guaratee whe usig i a N-bak iterleaved memory is the parallel access to cosecutive words i memory, i.e. ay N cosecutive words are stored. This leads to the covetioal mappig of data defied by: m(a) = A mod N

3 Fig. 1. mod-div mappig o a 5-bak iterleaved memory l(a) = A / N We will refer to this address mappig as the mod-div mappig. For N=2, the mod-div mappig, the bak umber cosists i the least sigificat bits while the high order bits costitute the local address. Figure 1 illustrates this mappig for N=5 ad a memory bak of 4 words. The old case for prime memory system Usig prime (or odd) memory system has bee kow to provide iterestig properties for vector supercomputers sice Budick [4] established the followig property o distributio of the elemets amog the memory baks. Theorem 2.1 (Distributio Theorem). Whe the bak distributio fuctio is defied by m(a) = A mod N, the for ay vector V stored with a stride R, V (i) ad V (j) are stored i the same memory bak iff i = j mod N/GCD(N, R) The for ay vector V stored with a stride R, N/GCD(N, R) cosecutive elemets of the vector are stored i distict memory baks.usig a prime umber of memory baks esures a coflict free distributio of ay slice of N cosecutive elemets for all the vectors stored with a stride R ot multiple of N. Moreover, usig a prime umber iduces simple cotrol for memory accesses; oly two distributios of elemets of a vector slice are possible: coflict free access is possible or all the elemets lie i the same memory bak. A last argumet i favor of usig a prime memory system is the demad for memory throughput o vector accesses with power-of-two strides i some specific applicatios. What was (believed to be) wrog with prime memory systems Ufortuately whe usig the usual data mappig, address computatio for a prime memory system requires arithmetic modulo a fixed prime umber: 1) Computig the memory bak umber for word at address A requires the computatio of A mod N. For specific values, very fast hardware evaluatios of such a modulo may be implemeted. 2) The computatio of the local displacemet i the memory bak requires a Euclidea Divisio by N ad this divisio is quite complex whe N is a odd umber. This Euclidea Divisio may leghte sigificatly the total memory idexig. Therefore, whe the usual low-order mappig o memory is used i a vector machie, the umber of memory baks was a power of two. I fact by chagig the choice of the local address fuctio, this Euclidea Divisio ca be avoided o memory systems with a odd umber of baks, but the result [1], [2] was probably published too late (1993) to be used i vector supercomputers. 2.2 Simple is better A very old arithmetic result kow as Chiese Remaider Theorem 1 iduces a very elegat way to map elemets oto a parallel memory cosistig i a odd umber N baks of 2 c elemets ad for which o hardware is eeded to compute the local address 2. Theorem 2.2 (Chiese Remaider Theorem). Let P ad Q be 2 relatively prime itegers, i.e. GCD(P,Q)=1 the for each pair (X, Y ) such that 0 X < P ad 0 Y < Q there exists oe ad oly oe 0 Z < P Q such that : Z X mod P ad Z Y mod Q The Chiese Remaider Theorem just guaratees that, 2 c beig the umber of memory words per bak, the fuctios 1. It seems that this result was kow more tha 2000 years ago by the old Chiese 2. O the Burroughs Scietific Processor [12], the Euclidea Divisio was also avoided, but 1 17 th of the memory was wasted.

4 Fig. 2. mod-mod mappig o a 5-bak iterleaved memory defied by m(a) = A mod N ad l(a) = A mod 2 c defie a mappig of the address space oto the physical memory sice N is odd ad therefore prime with 2 c. This mod-mod mappig is illustrated i Figure 2. The bak umber fuctio is exactly the same as for the mod-div mappig. Therefore the Distributio Theorem still holds for this mappig: coflict free access is possible to ay slice of N cosecutive elemets of a vector stored with a stride R ot multiple of N. The mai beefit of this mod-mod mappig is that the local address l(a) is the c least sigificat bits of the address: o hardware is required for derivig it from the address. The we ca state: Odd Memory Systems Do Not Require Euclidea Divisio 3 NO BANK-INTERLEAVED MEMORY SYSTEM RE- QUIRE EUCLIDEAN DIVISION I their experimets, Diamod et al [3] poits out that for GPUs powers of two are ot the best umber of baks for a GPU cache. I their particular experimets, they argue to use 62 ad 48 cache baks. These umbers are either odd or power of two. However, i this sectio we exted the result from the previous sectio to every umber N of baks. We cosider the geeral form of a iteger as N= 2 R with R odd. The particular cases of N beig a power of two (R=1) ad N beig odd ( = 0) have bee treated i the previous sectio. Therefore, we assume 0 ad R odd, but greater tha 1. We cosider the two fuctios m ad l defied by: m(a) = (A mod N) l(a) = A 2 mod 2 c These fuctios defie a mappig from the address space to the physical memory as show below: A = (A mod 2 ) + 2 A 2, therefore m(a) = (A mod 2 ) + 2 ( A 2 mod R). The applicatio of the Chiese Remaider Theorem esures that the fuctios l ad m 2 defie is a oe-to-oe mappig from {0,.., R 2 c 1} oto {0,.., 2 c 1} {0,.., R 1}. As a cosequece, the fuctios l ad m defie is a oe-to-oe mappig from the address space {0,.., N 2 c 1} oto the set of memory words of the memory system. This memory mappig is illustrated for a 6-bak iterleaved memory o Figure 3. Therefore we ca state : o euclidea divisio is eeded to idex a bak-iterleaved memory system. 4 BANK NUMBER COMPUTATION The computatio of modulo P is simple for P=2 p 1 or P= 2 p + 1, as well as N= 2 c (2 p 1) or N=2 c (2 p 1). This ca implemeted very simply through cascaded carry save adders followed by last p bits adder ad very limited logic. For example, a GPU with 32 warps would feature 32 to 64 cache baks. I that rage, may umbers are of the form N= 2 c (2 p 1) or N =2 c (2 p + 1): 33, 34, 36, 40, 48, 56, 60, 62 ad CONCLUSION Despite publicatios i 1993 [1], [2], it is still commo belief that idexig a bak iterleaved memory or cache requires a euclidea divisio whe the umber of baks is ot a power of two. I [1], [2], it was show that euclidea divisio is ot required for prime or odd umbers of baks. I this short paper, we have trivially exteded this result to ay umber of baks. Therefore, regardless the umber of baks: Bak-iterleaved cache or memory idexig does ot require euclidea divisio.

5 Fig. 3. Euclidea divisio free mappig o a 6-bak iterleaved memory ACKNOWLEDGEMENT This work was partially supported by the Europea Research Coucil Advaced Grat DAL No REFERENCES [1] A. Sezec ad J. Lefat, Odd memory systems may be quite iterestig, i Proceedigs of the 20th Aual Iteratioal Symposium o Computer Architecture. Sa Diego, CA, May 1993, 1993, pp [Olie]. Available: [2] Q. S. Gao, The chiese remaider theorem ad the prime memory system, i Proceedigs of the 20th Aual Iteratioal Symposium o Computer Architecture, ser. ISCA 93. New York, NY, USA: ACM, 1993, pp [Olie]. Available: [3] J. Diamod, D. Fussell, ad S. W. Keckler, Arbitrary modulus idexig, i Proceedigs of the 47th ACM/IEEE symposium o Microarchitecture, Dec [4] P. Budik ad D. J. Kuck, The orgaizatio ad use of parallel memories, IEEE Tras. Comput., vol. 20, o. 12, pp , Dec [Olie]. Available: C [5] D. T. Harper, III ad J. R. Jump, Vector access performace i parallel memories usig skewed storage scheme, IEEE Tras. Comput., vol. 36, o. 12, pp , Dec [Olie]. Available: [6] B. R. Rau, Pseudo-radomly iterleaved memory, i Proceedigs of the 18th Aual Iteratioal Symposium o Computer Architecture, ser. ISCA 91. New York, NY, USA: ACM, 1991, pp [Olie]. Available: [7] A. Sezec ad J. Lefat, Iterleaved parallel schemes: Improvig memory throughput o supercomputers, i Proceedigs of the 19th Aual Iteratioal Symposium o Computer Architecture, ser. ISCA 92. New York, NY, USA: ACM, 1992, pp [Olie]. Available: [8] M. Valero, T. Lag, ad E. Ayguadé, Coflict-free access of vectors with power-of-two strides, i ICS, 1992, pp [Olie]. Available: [9] B. D. de Diechi, A ultra fast euclidea divisio algorithm for prime memory systems, i Proceedigs of the 1991 ACM/IEEE Coferece o Supercomputig, ser. Supercomputig 91. New York, NY, USA: ACM, 1991, pp [Olie]. Available: [10] A. Sezec ad R. Espasa, Coflict-free accesses to strided vectors o a baked cache, IEEE Tras. Computers, vol. 54, o. 7, pp , [Olie]. Available: [11] R. Espasa, F. Ardaaz, J. Gago, R. Gramut, I. Heradez, T. Jua, J. S. Emer, S. Felix, P. G. Lowey, M. Mattia, ad A. Sezec, Taratula: A vector extesio to the alpha architecture, i 29th Iteratioal Symposium o Computer Architecture (ISCA 2002), May 2002, Achorage, AK, USA, 2002, p [Olie]. Available: [12] D. H. Lawrie ad C. R. Vora, The prime memory system for array access, IEEE Tras. Comput., vol. 31, o. 5, pp , May [Olie]. Available: