Appendix SystemC Product Briefs. All product claims contained within are provided by the respective supplying company.

Transcription

1 Appendix SystemC Product Briefs All product claims contained within are provided by the respective supplying company.

2 Blue Pacific Computing BlueWave Blue Pacific s BlueWave is a simulation GUI, including waveform viewer that can be used to view and analyze VCD results on Linux, Unix, Windows, including SystemC outputs. BlueWave Student version is free. Enables visualization and analysis of SystemC modeling Contact Blue Pacific at: info@bluepc.com of find us on the web at phone: (858)

3 Blue Pacific Computing SystemC Classes Three-day SystemC On-Site Classes focussing on SystemC for VHDL and Verilog Designer with additional two-day foundational course on C and C++ Teaches SystemC modeling and simulation to people with traditional Verilog or VHDL background. Contact Blue Pacific at info@bluepc.com or find us on the web at phone: (858)

4 IP Block Authoring Hardware Development Full System Specification Block Level Specification SPW DSP Behavioral Specification SPW Floating Point Algorithm Analysis SPW Fixed Point Algorithm Analysis Software Development SPW 4.6-SystemC 1.0 Co-simulation True Co-simulation Synchronization maintained between SPW/HDS and SystemC simulators Debugging may be done in either SPW and/or in SystemC debugger Breakpoints can be set in either system Will work with any SystemC 1.0 simulator SPW HDS Block Implementation SystemC 1.0 Implementation Flow 50

5 SYSTEMSIM Multilingual simulator, supporting Verilog, Superlog, C, C++ and SystemC, without interfaces or co-simulation C / C++ HDL Superlog SYSTEMSIM SystemC Allows SystemC models to be called from alternative language constructs to provide a fast, usable method to solve alternative language IP and legacy code issues Contact Co-Design Automation, Inc, info@co-design.com 51

6 Vip Library: a wide set of customizable and flexible system level Intellectual Property Soft Cores to answer Information and Communication Technologies Product requirements Availability of SystemC Core description to stress architectural exploration before HW/SW partitioning is performed. Contact CSELT S.p.A, viplibrary@cselt.it, 52

7 CoWare N2C TM CoWare N2C - Napkin to Chip in Half the Time. Full SystemC Co-Design Environment featuring: Specification Partitioning }Analysis at every stage Co-implementation Co-verification Read in and write out SystemC from CoWare N2C CoWareC or SystemC in CoWareC, SystemC, VHDL and Verilog out Visit 53

8 CoWare N2C System-Level Design Flow Algorithms, Control and Testbench ANSI C/C++, SystemC or CoWare C IP and Performance Models Function Refine Refine Architecture Behavioral C/C++ System Design and Partitioning Executable Implementable Spec Cycle-Accurate C/C++ HW-SW Co-design and Multi-level Co-verification "Traditional" HW-SW Co-verification Interface Synthesis Testbench SW Optimization Interface Synthesis HW Design RTLC Generate HDL SW Image + RTL Implementation 54

9 Databahn Memory Subsystem Generator Databahn, an on-line tool, generates synthesizable memory controller cores and automatically produces all C-level verification support for the associated memory subsystem Produces SystemC models of these cores Contact: Steven Shrader (208) , or visit our website at 55

10 (in-system Algorithm Verification Engine) Dynalith s isave technology combines the benefits of C- based design with the ability of H/W emulation running with the real target system at real speed. isave framework supports hardware models in high-level programming languages including SystemC. Contact Dynalith Systems ( at: info@dynalith.com (H.Q.) jinlee@dynalith.com (World Wide) edbarnett@dynalithusa.com (USA) info@i-vis.co.jp (Japan) 56

11 isave design flow with SystemC Algorithm in SystemC PrepIFM (designates interface modules and protocols) An example of MPEG2 Decoding Automated isave Design Environment PSGbuilder PAGbuilder Synthesizer Synthesizer TIE Configuration Data iscconfig Modified SC code Compiler Executable Code

12 Proven SystemC-based architectural exploration Interactive C-to-HDL design flow Optimized implementation High level design re-use ASIC and FPGA Silicon proven for : ultra-low power applications telecom base-band processing consumer speech processing Contact info@frontierd.com 58

13 Inputs Automatic SystemC-to-HDL What You Write Is What You Get Produces hierarchical Mealy Machine VHDL and Verilog output ASIC and FPGA Automatic test-bench generation Contact Compute process (combinatorial) Compute Update Update process (sequential) Clk Reset Enable Outputs 59

14 Fixed-point data types contributed to SystemC Bit-accurate modeling Any width and precision Overflow and quantization behavior Analysis and statistics Fix<w,d> Fix<w,d> Int<w> Int<w> Abstract Abstract Base Base Class Class Fix<5,2> Ufix<w,d> Ufix<w,d> Uint<w> Uint<w> For LINUX, SUN Solaris, Microsoft Windows, HP-UX For Microsoft, Borland, Sun, HP and GNU C++ compilers Downloadable from Contact S S Int<5> Ufix<5,2> Uint<5> 60

15 VStation Co-Modeling Ultra high-performance Co-Modeling between behavioral models running on a workstation and implementation models running on IKOS VStation. Based on the world s first high-performance transaction interface System verification productivity at emulation speed Enables SystemC models to be used in conjunction with emulation Bring the value of high performance emulation earlier in the verification process Utilizing your SystemC environment throughout the design cycle 61

16 Closing The Verification Productivity Gap Design Flow Untimed C Mixed-Level C RTL HDL Run 4 seconds real-time verification in 5 minutes Overnight 1.5 months Gate-Level 1.25 years Real Hardware 4 seconds 62

17 Visual SLD Systems-Level Design environment for defining and verifying system architecture, Hardware/Software co-verification, Register Definition. Includes Embedded Systems support, Complete code-coverage debug and analysis. Built upon the strongest graphic entry tool in the industry, Visual HDL. Truth-table, flowchart, Finite- State Machine, Block Diagram Language design via SystemC, C/C++, Verilog, VHDL or (800)

18 64 Visual SLD

19 TestBencher Pro Graphical environment for generating bus-functional models TestBencher generates SystemC test benches from language independent timing diagrams. Generates all the class code for each diagram, including port mappings and sensitivity lists Visit and download an evaluation version Contact SynaptiCAD at or

20 TestBencher Pro Generates SystemC Code

21 CoCentric TM Tools Architecture Functionality CoCentric TM System Studio SystemC CoCentric TM SystemC Compiler + a.out

22 integrated system level tool for performance analysis of system architecture and function concurrent design of HW and SW at multiple levels of abstraction Contact or visit for more information CoCentric TM System Studio HW/SW Co-Design propelled by SystemC 68

23 CoCentric TM SystemC Compiler Complete synthesis from SystemC to hardware C/SystemC synthesis refine & synthesize from C/C++ executable spec path to FPGAs for system designers powerful constructs for RTL designers Complete behavioral & RTL SoCs, ASICs, FPGAs Contact or visit for more information Behavioral or RTL CoCentric SystemC Compiler Design Compiler Physical Compiler FPGA Compiler II 69

24 SystemC-HDL Co-Simulation HDL Interface Library HDL VCS, Scirocco, MTI-VHDL Model import & export Contact or visit for more information 70

25 SystemC-VERA I/F High performance, direct kernel interface for integrating VERA with SystemC Uses the powerful, verification related features in VERA to verify system designs described in SystemC Contact or visit the website at for more information 71

26 TT VTOC Converts from Synthesisable Verilog to C/C++ Compiles multiple Verilog modules totalling up to about 100K gates into one large, highly-efficient, cycle-based C or C++ implementation. Provides a mechanism for efficient linking of separately compiled modules. Main applications are fast simulation and generation of a system-level emulator for the software team. SystemC is one of the output formats Web site is 72

27 SuperC A very fast SystemC Simulator that writes a highly compressed data format. This wave form data is compressed by 15-50X and can be displayed almost instantly by the Undertow waveform viewer regardless of file size. Veritools provides the SuperC C++ class compile library for the Veritools SuperC simulator Contact Veritools at inquiry@veritools.com or Robert Schopmeyer at schop@veritools.com 73

28 Undertow Suite A waveform viewer and Source Code debugging program for the SystemC/SuperC Simulator that reads the the highly compressed data format that is written directly by the SuperC simulator. This waveform data can be displayed almost instantly by the Undertow waveform viewer regardless of file size while providing linkage and synchronization with the SystemC source code. Undertow uses the highly compressed Fast file format from SuperC while providing Source Code debug facilities for SystemC Source Code. Contact Veritools at inquiry@veritools.com, or Robert Schopmeyer at schop@veritools.com 74

29 Undertow A very powerful waveform viewer for the SystemC/SuperC Simulator. This wave form data can be displayed almost instantly by the Undertow waveform viewer regardless of file data size Undertow uses the SystemC native waveform data or the highly compressed Fast file format from SuperC Contact Veritools, Inc. at inquiry@veritools.com or Robert Schopmeyer at schop@veritools.com 75

30 From Virtual Prototyping to SystemC Evaluate, experience, and design embedded IP platforms from your browser! Explore pre-configured embedded platforms, create high-level system models, and generate SystemC to link your designs to implementation. For more information contact or visit our web site at 76

31 World ClassTraining Modeling with SystemC Introduction to modeling with C/C++ and the SystemC class libraries Learn how to write, compile, execute, and debug system and hardware descriptions with SystemC SystemC for High Level Synthesis(HLS) Learn HLS concepts, SystemC coding style required for HLS, testbenches, and RTL co-simulation For more information or for class schedules 77

32 Semantic Rule Checking for SystemC Based Designs Full language support for C/C++ SystemC support with ongoing updates to support any changes confirmed by OSCI, Open SystemC Initiative Complete language rule checker Syntax and netlist SystemC coding style Behavioral & RTL synthesis coding style accuratec TM and Willamette HDL information 78

33 System-based Design Flow Software Untimed Functional Refine Timed Functional Partition System System Level Nonsynthesizable Abstractions Define and Simulate System Hardware Refine accuratec TM supports code refinement tasks System level Behavioral level RTL level Synthesis Refine Bus Cycle Accurate Code (Synthesizable) Behavioral Level Synthesize Synthesize Software Cycle Accurate RTL Code (Synthesizable) Register Transfer Level Synthesize 79

34 Open SystemC Initiative Delivers! Fast Innovation cross industry contribution Common, Open Industry Solution OSCI incorporating NOW as non profit organization OSI-compliant Open Source license Broad industry adoption and success! 80