Intro to High Level Design with SystemC
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1 Intro to High Level Design with SystemC Aim To introduce SystemC, and its associated Design Methodology Date 26th March 2001 Presented By Alan Fitch
2 Designer Challenges Design complexity System on Chip Gates High level Behavioral Synthesis Cycle-Based Simulation Design Reuse Deep Submicron Logic Synthesis Polygons Transistors SPICE Pattern Generation IC CAD ASICs Place & Route Logic Simulation
3 Silicon Complexity vs. Software Complexity Silicon complexity is growing 10x every 6 years Software in systems is growing faster than 10x every 6 years Log scale 1 G 100 M 10 M 1M 4M 16M 64M 256M 1 M 256K 80486TMS320C K 100 K LSI Logic gate array TMS320C240 16K K 8086 TMS320C30 10 K 1K 8085 TMS320C K P7 P6 IBM gate array Pentium Mitsubishi gate array Memory (DRAM) Microprocessor/ Logic DSP Growth in software complexity in consumer products Microprocessors Microcontrollers year
4 Attacking Complexity Work at a higher level of abstraction blocks RTL gates Reuse existing designs Cut n paste Virtual components (VCs) Capture Intellectual Property inhouse Platform based design up core ROM RAM DSP ATM MPEG INTERFACE
5 Levels of Abstraction System analysis System level modeling H/W S/W partitioning Architectural exploration Many of these steps are presently manual! H/W spec S/W spec Analog spec Gates Digital spec Integration and verification
6 Crossing the Gap Different sorts of engineers have different areas of expertise They think differently They use a different design language Each area of design (analogue, digital, physical, software) requires a different (but overlapping) set of skills Within an area of design there is a series of steps from high levels of abstraction to low levels of abstraction. Each level May use different languages May require a different mindset May be capable of automatic translation to the next lower level
7 Main requirements of hardware systems Concurrency: hardware systems are parallel. Almost all hardware systems include concurrency Reactivity: hardware systems react at transition on signals in the system Distributiveness: hardware systems are made of a set of basic computation units that may process data at different speeds use different clock rates Timing: specification of hardware systems includes timing concepts for the synchronisation of parallel and distributed behaviour
8 Language Comparison SystemC System-Level Languages C/C++-based VHDL/Verilog Replacements Higher-Level Languages Entirely New Languages Cynlib SoC++ A RT VHDL+ SDL SLDL SUPERLOG Java-based Java
9 C/C++ Based Languages Software/System engineer Conceptualize C/C++ simulation Write specification doc Hand over specification doc Executable spec Testbench Hardware engineer Understand Refine in C++, SystemC Verify reusing testbench Synthesize from C++, SystemC Faster simulation speed Tools already on the market C/C++ familiar to system and S/W engineers
10 Development of SystemC Synopsys Scenic IMEC SystemC Version 0.9 Synopsys Fridge Frontier Design A RT Library CoWare N2C SystemC Version 1.0 Fixed Point Types Abstract Modelling SystemC Version 1.1 SystemC Version Onward to Version 2!
11 SystemC Methodology Version 1 Version 2 Version 3 Abstract (UTF) refinement S O F T W A R E Generic RTOS refinement BCA H A R D W A R E RTOS RTL
12 Levels of Abstraction Untimed Functional (UTF) separates communication from behaviour uses Remote Procedure Call (RPC) paradigm Timed Functional (TF) allows allocation of time to behavioural blocks Bus Cycle Accurate models interfaces accurately using three handshaking methods Cycle Accurate (CA) essentially Register Transfer Level (RTL)
13 RTL Example EXOR gate built hierarchically from 4 NAND gates Each design created using header file (contains C++ constructor) source code file (contains algorithm) // nand2.cc #include "nand2.h" void nand2::do_nand2() { F =!(A & B); } C++ Function
14 NAND Gate Constructor Module // nand2.h #include "systemc.h" SC_MODULE(nand2) { // ports sc_in<sc_bit> A; sc_in<sc_bit> B; sc_out<sc_bit> F; void do_nand2(); Header Ports Constructor SC_CTOR(nand2) { SC_METHOD(do_nand2); sensitive << A << B; } }; Register do_nand2 with kernel
15 EXOR Gate // exor2.h #include "systemc.h" #include "nand2.h" SC_MODULE(exor2) { sc_in<sc_bit> A; sc_in<sc_bit> B; sc_out<sc_bit> F; Ports // 4 nand2 instances nand2 n1; nand2 n2; nand2 n3; nand2 n4; Hierarchy sc_signal<sc_bit> S1; sc_signal<sc_bit> S2; sc_signal<sc_bit> S3; Internal Signals
16 EXOR Gate (2) SC_CTOR(exor2): n1("n1"), n2("n2"), n3("n3"), n4("n4") { n1.a(a); n1.b(b); n1.f(s1); n2.a(a); n2.b(s1); n2.f(s2); n3.a(s1); n3.b(b); n3.f(s3); Instance Label Wire ports to signals } }; n4 << S3 << S3 << F;
17 EXOR Implementation // // exor2.cc // // This file has nothing in it: // the design structural // #include "exor2.h"
18 Conclusions C/C++ languages seems to be gaining acceptance Presently, synthesis techniques from C to hardware are appearing (e.g. A RT Designer) But the link to software is informal Taking SystemC as an example The present state of SystemC is that certain tools can synthesise hardware - SystemC allows you to write C++ descriptions that behave like VHDL or Verilog A formal link to software (e.g. perhaps some kind of generic RTOS API) remains in the future SystemC has industry momentum But methodology and tools need to evolve
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ESE Back End 2.0 D. Gajski, S. Abdi (with contributions from H. Cho, D. Shin, A. Gerstlauer) Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu 1 Technology advantages
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Contemporary Design We have been talking about design process Let s now take next steps into examining in some detail Increasing complexities of contemporary systems Demand the use of increasingly powerful