COEN-4720 Embedded Systems Design Lecture 3 Intro to ARM Cortex-M3 (CM3) and LPC17xx MCU

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1 COEN-4720 Embedded Systems Design Lecture 3 Intro to ARM Cortex-M3 (CM3) and LPC17xx MCU Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University Outline Overview of ARM Cortex-M3 processor Main features, pipeline, memory space Assembly NXP LPC17xx microcontroller unit (MCU) APPENDIX A: Instruction Set Architecture (ISA) APPENDIX B: ARM Instruction Set 1

2 Cortex-M3 Processor RISC general purpose 32-bit microprocessor Released in 2006 Cortex-M3 differs from previous generations of ARM processors by defining a number of key peripherals as part of the core: interrupt controller system timer debug and trace hardware (including external interfaces) This enables for real-time operating systems and hardware development tools such as debugger interfaces be common across the family of processors Various Cortex-M3 based microcontroller families differ significantly in terms of hardware peripherals and memory Cortex-M3 Processor Greater performance efficiency: more work to be done without increasing the frequency or power requirements Implements the new Thumb-2 instruction set architecture 70% more efficient per MHz than an ARM7TDMI-S processor executing Thumb instructions 35% more efficient than the ARM7TDMI-S processor executing ARM instructions for Dhrystone benchmark Low power consumption: longer battery life, especially critical in portable products including wireless networking applications Improved code density: code fits in even the smallest memory footprints Core pipeline has 3 stages Instruction Fetch Instruction Decode Instruction Execute 2

3 Simplified Cortex-M3 Architecture Simplified Cortex-M3 Architecture 3

4 Cortex-M3 Processor Architecture Harvard architecture: it uses separate interfaces to fetch instructions (Inst) and (Data) Processor is not memory starved: it permits accessing data and instruction memories simultaneously From CM3 perspective, everything looks like memory Only differentiates between instruction fetches and data accesses Interface between CM3 and manufacturer specific hardware is through three memory buses: ICode, DCode, and System (for peripherals), which are defined to access different regions of memory Cortex-M3 Processor Cortex-M3 is a load/store architecture with three basic types of instructions 1. Register-to-register operations for processing data 2. Memory operations which move data between memory and registers 3. Control flow operations enabling programming language control flow such as if and while statements and procedure calls 4

5 Cortex-M3 Pipeline This is Slide #27 of ARM Cortex-M3 Introduction, ARM University Relations. Download from: 5

6 Processor Register Set Cortex-M3 core has 16 user-visible registers All processing takes place in these registers Three of these registers have dedicated functions program counter (PC) - holds the address of the next instruction to execute link register (LR) - holds the address from which the current procedure was called the stack pointer (SP) - holds the address of the current stack top (CM3 supports multiple execution modes, each with their own private stack pointer). Processor Status Register (PSR) which is implicitly accessed by many instructions Processor Register Set 6

7 Cortex-M3 Memory Address Space ARM Cortex-M3 processor has a single 4 GB address space The SRAM and Peripheral areas are accessed through the System Bus The Code region is accessed through the ICode (instructions) and DCode (constant data) buses Memory Map 7

Memory Map - Details Program Memory Model RAM for an executing program is divided into three regions 1. Data in RAM are allocated during the link process and initialized by startup code at reset 2.

8 Memory Map - Details Program Memory Model RAM for an executing program is divided into three regions 1. Data in RAM are allocated during the link process and initialized by startup code at reset 2. The (optional) heap is managed at runtime by library code implementing functions such as the malloc and free which are part of the standard C library 3. The stack is managed at runtime by compiler generated code which generates per-procedure-call stack frames containing local variables and saved registers 8

Operating Modes Cortex-M3 processor has two modes and two privilege levels The operation modes - determine whether the processor is running a normal program or running an exception handler thread

9 Operating Modes Cortex-M3 processor has two modes and two privilege levels The operation modes - determine whether the processor is running a normal program or running an exception handler thread mode handler mode The privilege levels - provide a mechanism for safeguarding memory accesses to critical regions as well as providing a basic security model privileged level user level Nested Vector Interrupt Controller (NVIC) A programmable device that sits between the CM3 core and the microcontroller CM3 uses a prioritized vectored interrupt model the vector table is defined to reside starting at memory location 0 First 16 entries in this table are defined for all Cortex-M3 implementations while the remainder, up to 240, are implementation specific NVIC supports dynamic redefinition of priorities with up to 256 priority levels Two entries in the vector table are especially important: address 0 contains the address of the initial stack pointer address 4 contains the address of the reset handler to be executed at boot time 9

10 Nested Vector Interrupt Controller (NVIC) Provides key system control registers including the System Timer (SysTick) that provides a regular timer interrupt Provision for a built-in timer across the Cortex-M3 family has the significant advantage of making operating system code highly portable all operating systems need at least one core timer for time-slicing Registers used to control the NVIC are defined to reside at address 0xE000E000 and are defined by the Cortex- M3 specification These registers are accessed with the system bus Thumb-2 Instruction Set Thumb-2 instruction set is a superset of the previous 16-bit Thumb instruction set Provides A large set of 16-bit instructions, enabling 2 instructions per memory fetch A small set of 32-bit instructions to support more complex operations Specific details of this ISA not our focus (we ll mostly program in C) See APPENDIX A of these slides for more details on ISA 10

11 Outline Overview of ARM Cortex-M3 processor Main features, pipeline, memory space Assembly NXP LPC17xx microcontroller unit (MCU) APPENDIX A: Instruction Set Architecture (ISA) APPENDIX B: ARM Instruction Set Unified Assembly Language (UAL) UAL supports generation of either Thumb-2 or ARM instructions from the same source code same syntax for both the Thumb code and ARM code enable portability of code for different ARM processor families Interpretation of code type is based on the directive listed in the assembly file Example: For GNU Assembler, the directive for UAL is.syntax unified For ARM assembler, the directive for UAL is THUMB See comprehensive listing of Cortex-M3 instruction set in Appendix A of book: Joseph Jiu, The Definitive guide to the ARM Cortex-M3, 2009 (download from link provided here: ). 11

12 Example 1 data:.byte 0x12, 20, 0x20, -1 func: mov r0, #0 mov r4, #0 movw r1, #:lower16:data movt r1, #:upper16:data top: ldrb r2, [r1],1 add r4, r4, r2 add r0, r0, #1 cmp r0, #4 bne top From ARM Architecture Reference Manual There are similar entries for move immediate, move shifted (which actually maps to different instructions) etc. 12

13 Example 2 int counter; int Counter_Inc(void) { return counter ++; } Resulting (annotated) assembly language with corresponding machine code: Counter_Inc: 0: f movw r3, #:lower16:counter // r3 = &counter 4: f2c movt r3, #:upper16:counter 8: 6818 ldr r0, [r3, #0] // r0 = *r3 a: 1c42 adds r2, r0, #1 // r2 = r0 + 1 c: 601a str r2, [r3, #0] // *r3 = r2 e: 4740 bx lr // return r0 13

14 Two 32-bit instructions (movw, movt) are used to load the lower/upper halves of the address of counter (known at link time, and hence 0 in the code listing) Then, three 16-bit instructions load (ldr) the value of counter, increment (adds) the value, and write back (str) the updated value Finally, the procedure returns the original counter Key points: Cortex-M3 utilizes a mixture of 32-bit and 16-bit instructions (mostly the latter) and the core interacts with memory solely through load and store instructions While there are instructions that load/store groups of registers (in multiple cycles) there are no instructions that directly operate on memory locations How does an assembly language program get turned into a executable program image? Binary program file (.bin) Assembly files (.s) Object files (.o) Executable image file as (assembler) ld (linker) Memory layout Linker script (.ld) Disassembled code (.lst) 14

15 Outline Overview of ARM Cortex-M3 processor Main features, pipeline, memory space Assembly NXP LPC17xx microcontroller unit (MCU) APPENDIX A: Instruction Set Architecture (ISA) APPENDIX B: ARM Instruction Set Cortex-M3 processor vs. CM3-based Microcontroller Units 15

While there is significant overlap between the families and their

course we focus on the NXP s LPC17xx family LPC17xx LPC17xx (of NXP)

basis for microcontrollers from other manufacturers including TI, ST,

LPC1768 operates at up to a 100 MHz CPU frequency Sophisticated clock

of data memory Ethernet MAC a USB interface that can be configured as

4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface 3 I2C

10-bit DAC, motor control PWM Quadrature Encoder interface, 4 general

16 While there is significant overlap between the families and their peripherals, there are also important differences In the lab of this course we focus on the NXP s LPC17xx family LPC17xx LPC17xx (of NXP) is an ARM Cortex-M3 based microcontroller The Cortex-M3 is also the basis for microcontrollers from other manufacturers including TI, ST, Toshiba, Atmel, etc. LPC1768 operates at up to a 100 MHz CPU frequency Sophisticated clock system Peripherals include: up to 512 kb of flash memory, up to 64 kb of data memory Ethernet MAC a USB interface that can be configured as either Host, Device, or OTG 8 channel general purpose DMA controller 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface 3 I2C interfaces, 2-input plus 2-output I2S interface 8 channel 12-bit ADC, 10-bit DAC, motor control PWM Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM ultra-low power RTC with separate battery supply up to 70 general purpose I/O pins 16

17 LPC1768 Abstract Representation of a Development Board (such as LandTiger 2.0) Recall from lecture#1: 17

18 LPC1768 LPC1768 microcontrollers are based on the Cortex-M3 processor with a set of peripherals distributed across three buses Advanced High-performance Bus (AHB) and its two Advanced Peripheral Bus (APB) sub-buses APB1 and APB2. These peripherals: are controlled by the CM3 core with load and store instructions that access memory mapped registers can interrupt the core to request attention through peripheral specific interrupt requests routed through the NVIC Data transfers between peripherals and memory can be automated using DMA Labs will cover among others: basic peripheral configuration how interrupts can be used to build effective software how to use DMA to improve performance and allow processing to proceed in parallel with data transfer LPC1768 Peripherals are memory-mapped core interacts with the peripheral hardware by reading and writing peripheral registers using load and store instructions The various peripheral registers are documented in the user and reference manuals documentation include bit-level definitions of the various registers and info on how to interpret those bits actual physical addresses are also found in the reference manuals Examples of base addresses for several peripherals (see page 14 of the LPC17xx user manual): 0x UART1 0x SPI 0x GPIO interrupts 0x ADC No real need for a programmer to look up all these values as they are defined in the library file lpc17xx.h as: LPC_UART1_BASE LPC_SPI_BASE LPC_GPIOINT_BASE LPC_ADC_BASE 18

19 LPC1768 Typically, each peripheral has: 1. Control registers to configure the peripheral 2. Status registers to determine the current peripheral status 3. Data registers to read data from and write data to the peripheral LPC1768 In addition to providing the addresses of the peripherals, lpc17xx.h also provides C language level structures that can be used to access each peripheral For example, the SPI and GPIO ports are defined by the following register structures: typedef struct { IO uint32_t SPCR; I uint32_t SPSR; IO uint32_t SPDR; IO uint32_t SPCCR; uint32_t RESERVED0[3]; IO uint32_t SPINT; } LPC_SPI_TypeDef; 19

20 LPC1768 typedef struct { union { IO uint32_t FIODIR; struct { IO uint16_t FIODIRL; IO uint16_t FIODIRH; }; struct { IO uint8_t FIODIR0; IO uint8_t FIODIR1; IO uint8_t FIODIR2; IO uint8_t FIODIR3; }; }; uint32_t RESERVED0[3]; union { IO uint32_t FIOMASK; struct { IO uint16_t FIOMASKL; IO uint16_t FIOMASKH; }; struct { IO uint8_t FIOMASK0; IO uint8_t FIOMASK1; IO uint8_t FIOMASK2; IO uint8_t FIOMASK3; }; }; union { IO uint32_t FIOPIN; struct { IO uint16_t FIOPINL; IO uint16_t FIOPINH; }; struct { IO uint8_t FIOPIN0; IO uint8_t FIOPIN1; IO uint8_t FIOPIN2; IO uint8_t FIOPIN3; }; }; union { IO uint32_t FIOSET; struct { IO uint16_t FIOSETL; IO uint16_t FIOSETH; }; struct { IO uint8_t FIOSET0; IO uint8_t FIOSET1; IO uint8_t FIOSET2; IO uint8_t FIOSET3; }; }; union { O uint32_t FIOCLR; struct { O uint16_t FIOCLRL; O uint16_t FIOCLRH; }; struct { O uint8_t FIOCLR0; O uint8_t FIOCLR1; O uint8_t FIOCLR2; O uint8_t FIOCLR3; }; }; } LPC_GPIO_TypeDef; LPC1768 The register addresses of the various ports are defined in the library (see lpc17xx.h): #define LPC_APB0_BASE (0x UL) #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE) For example, to turn on the LED marked as D11 on the LandTiger 2.0 board (which is driven by the pin P2.1 of the MCU), the following code can be used: LPC_GPIO1->FIOSET = 1 << 1; 20

21 Memory On-chip flash memory system Up to 512 kb of on-chip flash memory Flash memory accelerator maximizes performance for use with the two fast AHB-Lite buses Can be used for both code and data storage On-chip Static RAM Up to 64 kb of on-chip static RAM memory Up to 32 kb of SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus Devices with more than 32 kb SRAM have two additional 16 kb SRAM blocks LPC17xx system memory map 21

22 References & Credits Joseph Jiu, The Definitive guide to the ARM Cortex-M3, 2007 LPC17xx microcontroller USER MANUAL Cortex-M3 Processor TECHNICAL REFERENCE MANUAL Lab manual (G. Brown, Indiana) EECS-373, UMich See website of class for links to download any of the above: Outline Overview of ARM Cortex-M3 processor Main features, pipeline, memory space Assembly NXP LPC17xx microcontroller unit (MCU) APPENDIX A: Instruction Set Architecture (ISA) APPENDIX B: ARM Instruction Set 22

23 APPENDIX A: Instruction Set Architecture (ISA) Instruction set Addressing modes Word size Data formats Operating modes Condition codes Thumb-2 Instruction Set Thumb-2 instruction set is a superset of the previous 16-bit Thumb instruction set Provides A large set of 16-bit instructions, enabling 2 instructions per memory fetch A small set of 32-bit instructions to support more complex operations Specific details of this ISA not our focus (we ll mostly program in C) 23

32-bits Major Elements of ISA 32-bits mov r0, #1 ld r1,

increasing numeric significance with increasing memory

24 32-bits Major Elements of ISA 32-bits mov r0, #1 ld r1, [r0,#5] r1=mem((r0)+5) bne loop subs r2, #1 Endianess Endianess Addressing: Big Endian vs Little Endian Endian-ness: ordering of bytes within a word Little - increasing numeric significance with increasing memory addresses Big The opposite, most significant byte first MIPS is big endian, x86 is little endian 24

25 ARMv7 ARM Instruction Encoding Instructions are encoded in machine language opcodes Instructions movs r0, #10 movs r1, #0 Register Value Memory Value (LSB) (MSB) (msb) (lsb) 0a bit Thumb-2 Some of the changes used to reduce the length of the instructions from 32 bits to 16 bits reduce the number of bits used to identify the register less number of registers can be used reduce the number of bits used for the immediate value smaller number range remove options such as S make it default for some instructions remove conditional fields (N, Z, V, C) no conditional executions (except branch) remove the optional shift (and no barrel shifter operation introduce dedicated shift instructions remove some of the instructions more restricted coding 25

26 Thumb-2 Implementation 32bit Instruction Encoding 26

27 ARM and 16-bit Instruction Encoding Thumb Instruction Set See 6_THUMB_Instr_Set_pt3.pdf included in lab2_files.zip 27

Application Program Status Register (APSR) Reminder on saturating operations: Saturation means that when a calculation overflows, the result is set to the largest

28 Application Program Status Register (APSR) Reminder on saturating operations: Saturation means that when a calculation overflows, the result is set to the largest positive or most negative number, rather than a modulo calculation a in 2 s complement arithmetic. Useful in multimedia apps (e.g., volume knob) Conditional Execution 28

29 Conditional Execution Conditional Execution and Flags 29

30 Conditional execution examples Outline Overview of ARM Cortex-M3 processor Main features, pipeline, memory space Assembly NXP LPC17xx microcontroller unit (MCU) APPENDIX A: Instruction Set Architecture (ISA) APPENDIX B: ARM Instruction Set 30

31 ARM Instruction Set Data Processing Instructions Arithmetic and logical operations 3-address format: Two 32-bit operands (op1 is register, op2 is register or immediate) 32-bit result placed in a register Barrel shifter for op2 allows full 32-bit shift within instruction cycle 31

32 Data Processing Instructions Arithmetic operations: ADD, ADDC, SUB, SUBC, RSB, RSC Bit-wise logical operations: AND, EOR, ORR, BIC Register movement operations: MOV, MVN Comparison operations: TST, TEQ, CMP, CMN Data Processing Instructions 32

33 Data Processing Instructions Multiply Instructions Integer multiplication (32-bit result) Long integer multiplication (64-bit result) Built in Multiply Accumulate Unit (MAC) Multiply and accumulate instructions add product to running total 33

Word, Half Word and Byte to and from registers Can be used

34 Multiply Instructions Data Transfer Instructions Load/store instructions Used to move signed and unsigned Word, Half Word and Byte to and from registers Can be used to load PC (if target address is beyond branch instruction range) 34

35 Addressing Modes Offset Addressing Offset is added or subtracted from base register Result used as effective address for memory access [<Rn>, <offset>] Pre-indexed Addressing Offset is applied to base register Result used as effective address for memory access Result written back into base register [<Rn>, <offset>]! Post-indexed Addressing The address from the base register is used as the EA The offset is applied to the base and then written back [<Rn>], <offset> <offset> options An immediate constant #10 An index register <Rm> A shifted index register <Rm>, LSL #<shift> 35

36 Block Transfer Instructions Swap Instruction 36

37 Modifying the Status Registers Software Interrupt 37

38 Branching Instructions Branch (B): jumps forwards/backwards up to 32 MB Branch link (BL): same + saves (PC+4) in LR Suitable for function call/return Condition codes for conditional branches Branching Instructions 38

39 IF-THEN Instruction Barrier instructions 39

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