A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip

Transcription

1 J Electron Test (2017) 33: DOI /s A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip Babak Aghaei 1 & Ahmad Khademzadeh 2 & Midia Reshadi 1 & Kambiz Badie 2 Received: 22 January 2017 /Accepted: 10 May 2017 /Published online: 5 June 2017 # Springer Science+Business Media New York 2017 Abstract In this paper, a new BIST based test approach to detecting short faults on the communication channels data links in network-on-chip is proposed. The rationale underlying the novelty of the proposed approach is that it is capable of locating the faulty channels while simultaneously performing the testing as well as updating the Routing Tables (RT) in which irregular Mesh-based and fault tolerant NoCs that are using Table-based routing. The proposed approach encompasses TPG and TRA located in the Network Adapter (NA) as well as a Packet Comparing Module (PCM) embedded in the routers. The approach, in addition, with a high scalability leads to 100% Test Coverage (TC) and 82.3% capability of diagnosing faulty channels in NoCs with a high scale. Furthermore, the approach is capable of being performed within one Round (two phase) run with a total time of 70 clocks which is considered as cost-effective compared with the preceding methods. The simulation results demonstrate that the hardware cost of PCM is trivial Responsible Editor: X. Li * Kambiz Badie k_badie@itrc.ac.ir 1 2 Babak Aghaei B.aghaei@iaut.ac.ir Ahmad Khademzadeh Zadeh@itrc.ac.ir Midia Reshadi Reshadi@srbiau.ac.ir Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran Telecommunication Research Center, Tehran, Iran compared with the hardware of RASoC, HERMES, Æthereal and Vici routers. Keywords Network on Chip. Communication test. Built in self testing. Fault diagnosis. Test coverage 1 Introduction In response to the demand of today s world for a high and efficient computing, the semi-conductor industry has managed to supply simple chips within which a couple of separate processors are processed together. These chips, however, have been experiencing a serious bottleneck in their internal communications due to the shrunk sizes of silicon innovation, delay, and power consumption [13, 48, 54]. To solve these problems, about 1999, the concept of Network-on-Chip (NoC) with the packet-switching structure emerged and hence replaced buses with outdated structures in Systems-on-Chip (SoCs) [1, 9, 21]. NoC is composed of numerous routers (switches) and channels which provide a vigorous communication infrastructure for the elements in the chip [22]. The Intellectual property cores (IP cores) attached to NoC by Network Adapters (NA) and communicate with together. Unique features such as wiring resources, various traffic models, integration of heterogeneous elements, efficient power consumption, scalability, resource reusing, and testability have made NoC a convenient approach to tackle with the bottleneck in the contemporary crowded integrated systems [29]. The shrinking chip size on the one hand and the increasing number of routers and channels on the other hand to meet the needs of bandwidth have made NoC prone to such manufacturing defects and lifetime faults on channels that classified in two main subcategories namely permanent faults such as stuck at fault, shorts, opens, and delay [28, 36, 38, 39]

2 502 J Electron Test (2017) 33: as well as transient faults such as crosstalk [20]. The NoC has borrowed some of these concepts from previous researches on System on Board (SoB). Each fault puts a distinctive effect upon the network. In one channel, the short fault results in packet duplication, overloading, misrouting, delay, and dropping; and these therefore negatively affect the network performance (i.e., power consumed, delay, and throughput). Accordingly, it seems essential to test, detect and locate short faults on channels to hinder the diminution in NoC efficiency. Generally, the test of an NoC-based SoC for detecting is usually divided into two parts: the test of the IP cores and the test of the communication infrastructure [49]. The test of the cores is typically based upon the reuse of the NoC as TAM to reduce the test overhead. There are hard works that are carried in this field [2, 7, 17, 27, 37, 48, 50, 51, 53]. The test of the communication infrastructure encompasses routers test and communication channels test. A bulk of investigations e.g. [4 6, 8, 19, 33, 41, 42] has been conducted to test the routers. A substantial number of investigations have been conducted in the field of communication test, which are surveyed in [3]. One approach toward NoC testing is to employ the Built-in Self-Test (BIST). Although, this mechanism is believed to be costeffective and prevalent for such various reasons as the unnecessity of external test equipment, test performance with circuit speed, high testability, and online and offline test performance [15], BIST can still be not enough for testing of NOC elements (routers, channels, and IP cores). In this structure, Test Pattern Generator (TPG) on the one hand of the unidirectional channel generates test patterns and applies to it; and on the other hand, Test Response Analyzer (TRA) receives and analyzes the test results. To test bi-directional channels between the routers i.e. (Ri,Rj), therefore, the two units are required to be embedded both in Ri router and Rj router [26]. Moreover, to test the bi-directional channel between the router and NA i.e. (NAi, Ri), both units can be located in NA [18]. In NoC, each router and NA requires a pair of TPG and TRA. With an increase in the network dimension, however, hardware redundancy increases substantially. The approaches proposed for communication testing, unfortunately, which have been capable of reducing hardware overload; have not managed to hinder the increase or decrease of such factors as testing time, test coverage, and fault diagnosis capability and network efficiency. Each investigation, however, is expected to provide a tradeoff between these factors. In addition, the approaches proposed so far for testing NoC have not obviously discussed how to utilize the test results (fault information) in order to elevate its fault tolerance capability. The initial step, however, to fault tolerant methods productivity is to detect and locate the occurred faults [24]. Employing a testing strategy with a high fault location capability can increase the fault tolerant capability of a system as well. Having discussed the ins and outs of communication testing, its thorough examination can promise fruitful results provided that the test time, fault diagnosis capability, network efficiency, and hardware overload are cost-effective. In addition, we can assimilate the testing communication with the strategies proposed to increase the NoC fault tolerant capability. This paper proposes a BIST-based approach for NoC-based communication channels with high test coverage and fault location, and a low hardware redundancy which is capable of targeting the short faults in data links. The proposed approach is capable of 100% testing the channels and 84% locating faulty channels via establishing a Single Hub Traffic Pattern (SHTP) in the network as well as embedding a simple comparator circuit in the router. The contributions of the approach proposed are fourfold: 1. In the proposed approach, TPG and TRA have been eliminated from the router; this significantly reduces the hardware overhead in the preceding methods. 2. The mechanism provided can simultaneously perform testing as well as update routing tables. This is performed by PCM. 3. In the proposed approach, the test time is reduced and the test rounds are minimized through simultaneous implementation of testing process on all channels. This paper is organized as follows: Section 2 reviews the recent related work. Section 3 explicates the short fault model. The proposed approach is presented in Section 5 with detailed explanations. Section 6 investigates fault coverage and scalability, Section 7 explains hardware; and Section 8 examines test time. The paper, eventually, comes to an end with the simulation results and comparisons presented in Section 9 and the conclusion and future work discussed in Section Related Work Raik et al. [47]haveproposedanexternaltestmethodwhichis capable of functionally testing the switches and the channels to detect delay faults, opens, and shorts. Grecu et al. [26] propose a BIST methodology for at-speed testing the channels of the communication platform among the routers. The proposed methodology aims at targeting crosstalk faults assuming the MAF fault model [20] and short faults can be detected as well. The test patterns are located in the payload packets

3 J Electron Test (2017) 33: and then are transmitted to the channels being tested. The authors have therefore managed to reduce the test time using test parallelism. Petersen et al. [43] developed a functional and scalable online-structural methodology for a two-dimensional mesh which works with system speed. In this method, similarly, a BIST structure at chip initialization tests the communication channels among the routers to detect the physical faults. To the best of our knowledge, the paper by Cota et al. [18] is one of the most thorough works in the communications test in which a functional test strategy has been proposed to detect shorts in the data links, handshake in an NoC channel with a grid topology. The researchers embedded the TPG and TRA in the NA and then detected the network shorts through generating test packets, transmitting them to neighbors, and analyzing the results. In this method, although the hardware overload is diminished, the faults are not located. Herve et al. [30], having understood this, could manage to detect 93% of the shorts in the communication channels following their development of the previous method and proposing a fault detection method. This detection requires 16 times of configuration and 5 rounds of test cost in a 5*5 grid network. Their proposed method, hence, faced drawbacks in the fault location. Concatto et al. [16], similarly, employed this methodology for a mesh network. The method suggested encompasses the detection and diagnosis of shorts in the communication channels through employing a BIST as well as activating an alternative path for the faulty channels. Herve et al. in their subsequent work [31] integrated the functional test presented in their former paper with the routers test. Strano et al. [45] proposed a BIST and self-diagnosis structure for stuck at fault test. Kakoee et al. [34] proposed an on-line test mechanism in which each router with the neighboring routers assistance was capable of detecting all stuck at faults and shorts only on the channels among the routers. Ghofrani et al. [24] assertthatthey have proposed a comprehensive and cost-effective solution for the detection and diagnosis of permanent online faults on channels. Employing an error syndrome collection and flit/packet counting technique, they are capable of detecting the faults on the control and data lines. Kakoee et al. [35] in another work proposed a detection and diagnosis structure for delay, shorts, and stuck at faults in the NA and the communication channels. Bhowmik et al. in their works [10 12], recently, suggested an on-line test structure for the detection of shorts in the communication channels. Their works are mainly characterized by a high level simulation that is abletoassesstheeffectofnumberoftestroundsupon such network efficiency parameters as power consumed, delay, and throughput. To the best of our knowledge, the works conducted by [24, 34] can be regarded as more comprehensive investigations on faults location in the NoC channels. These papers, however, have not addressed the fault detection in the channels between the router-na. Their proposed methodology, on the other hand, greatly increases the system hardware overhead and also various configurations are required for the complete implementation of the approach. Other papers, similarly, have not addressed how the test results are employed for faults location. In Table 1, a thorough comparison has been made among the previous methods. In this paper, we propose a scalable test strategy for the detection and location of short faults on the communication channels which, compared with previous methodologies, is more cost-effective with respect to the test coverage, test time and hardware overhead, and test rounds. S: scalability, FC: fault coverage, HR: hardware redundancy, TT: test time, TR: test round, Na: not available. 3 Short Fault Model Short fault refers to a situation in which the number of k wires is connected to each other within a single channel. This type of fault leads to wires connection in both communication channels of router-to-router (Ri, Rj) and router-to-na (NAj, Ri) in two directions. Short faults are twofold: OR-short, and ANDshort. With respect to their physical location, these faults are classified into two categories of intra-channels shorts and inter-channels shorts [11]. Both categories of faults influence the network efficiency. The present paper concentrates upon intra-channels short faults. Figure 1 illustrates short faults in intra communication channel (Ri, Rj). Table 1 Previous methods evaluation and comparison Methods Year S FC (%) HR (Gate or %) TT (cycle) Grecu et al. [26] *8 Na 166, Peterson et al. [43] * % 5100 Na Cota et al. [18] *5 na Herve et al. [30] * Concatto et al. [16] * ,8% Na 9 Raik et al. [47] * % Herve et al. [31] * Strano et al. [45] * % Kakoee et al. [34] * % Na 9 Ghofrani et al. [24] * % Na 4 Kakoee et al. [35] * % Na 9 Bhowmik et al. [11] *4 100 na TR

4 504 J Electron Test (2017) 33: Fig. 1 Short faults in the (Ri, Rj) channel l 1 l 2 l 3 l 1 l 2 l 3 R i l 4 l 5 l 6 l 7 l 8 l 4 l 5 l 6 l 7 l 8 R j In Fig. 1, fsab is used to define a short fault between the two l b. and l a wires. N S, the number of short faults on the channel with the n wires is obtained by the following eq. [12]: Ns ¼ n k¼2 n! k! ðn kþ! ð1þ Considering Eq. (1), the number of short faults in a unidirectional channel with 10 wires equals with 1013 shorts. The number of short faults, generally, in an NoC with 퐶 h channels can be computed by the following equation: Nnoc ¼ Ns Ch 4 The Proposed Approach ð2þ As mentioned, in this paper we aim at detecting and locating the short faults within the wires of a channel. Our proposed methodology is scalable ranging from a 2 2 to n*n mesh network for every channel width. The rationale underlying our selection of mesh topology is that it possesses such advantages as regularity, concurrent data transmission, and controlled electrical parameters [32]. The majority of NoC architectures employed, in addition, in the industries and research environments utilize this topology [14, 48]. The approach proposed in this investigation consists of a set of the following concepts: 1) Packet structure, 2) Single Hub Transfer Pattern, 3) fault location in the channels, 4) Packet Comparing Module, and 5) test mechanism. Each of these concepts will be addressed in the upcoming sections. 4.1 Test Packet Structure The test pattern for the detection of short faults within a channel with n wire including n number of Walking-One () sequence [46], which is referred to as, is generated by TPG. The NA capsulates this patterns within a packet by adding the head and tail, and hence its routing to the channels under test is applied under navigating of routing algorithm. The head includes such monitoring and routing information as destination address, packet commencement, and access demand to the channel, the current control, and the packet type. The tail, furthermore, encompasses the packet end and releasing the channel. Payload follows the head and the payload is followed with the tail. The packet size depends upon channel width n. We consider n=10here. Figure 2 represents a test packet sample. 4.2 Single Hub Traffic Pattern This term, which is introduced for the first time in this paper, is a type of broadcasting. Making this traffic is a pre-stage to implement our proposed methodology. SHTP is characterized by the following features: 1. The packets are generated equally by TPGs 2. The NA distributes the packet to the entire neighbors. 3. Each packet passes three channels to be drained. Figure 3 depicts a 2 2 Mesh based NoC with a SHTP. The routers are considered as one of the primary elements of communication infrastructure in the NoC, and in designing various routers an attempt is made to target such issues as power consumption, buffers space, area, fault tolerance, Design-for-Test (DfT), and reliability. Regardless of their functionality, the routers can be generally classified into three types in terms of the port numbers: 1) Three-port routers, 2) Four-port routers and 3) Five-port routers. These routers possess three, four, and five input channels and three, four, and five output channels, respectively. Since all IP cores are generating packets in the SHTP, all router ports are either transmitting or receiving the packet as well. Suppose that equally identical packets flow in the network; each router then will receive similar packets of its ports. By similarity, we mean the equality of packets payload. Accordingly, the three-port router, the four-port router, and the five-port router will receive three, four, and five equal packets, respectively. If a router receives a different packet from one of its ports, this suggests that: BA fault has occurred in the path that the packet has passed. This issue will be discussed later in the paper.

5 J Electron Test (2017) 33: R0 Fig. 2 Test packet structure containing walking-one sequence i1 R2 i2 R3 4.3 Fault Location in the Channels Consider Fig. 4. The routes a packet passes to reach R 2 router (i.e. i 0, i 1, and i 2 ) are illustrated by the dotted lines. The i 0 includes a single channel of (NA 2,R 2 ), i 1 includes two channels of (NA 0,R 0 ) and (R 0,R 2 ),andi 2 includes two channels of (NA 3,R 3 ) and (R 3,R 2 ). It is safe to claim that there is no fault in the aforementioned five channels if the similar packet is received from three routes. If, however, a packet differs from the other ones, a fault has therefore occurred in the route. If, for instance, the packet entering from i 1 route differs from other packets, then there is a fault on either one or both channels (NA 0,R 0 ) and (R 0,R 2 ). In Table 2, the possible situations are presented for four router inputs of Fig. 3 with the possible fault locations. It is worth noting the assumption that all NoC channels be faulty does not appear realistic [18]. If, generally, we consider the number of router inputs as p,then p-2 faults can be located since, at least, an equality exists among the packets. We present this amount as diagnosis threshold in this paper. The diagnosis threshold, simply put, relies upon the number of router inputs. Based on the diagnosis threshold of each router, some R0 R2 Fig. 3 The 2 2 Mesh based NoC with SHTP R1 R3 i0 Fig. 4 A router input routes in the HSTP states is generated in the PCM (See Table 2). In some states the faults can be located, however, in some cannot be. If we consider the number of diagnosable states as S diagnosable and the number of non-diagnosable situations as S nondiagnosable, then the diagnosis capability in each router can be computed by the following equation: S diagnosable D capability ¼ S diagnosable þ S Nodiagnosable ð3þ In Table 3, the diagnosis capability rate for each router has been computed. 4.4 Packet Comparing Module In order to compare the packets arrived in each router; a flit comparator circuit is required, which is known as PCM in this paper. The module is a combinational circuit which is composed of XOR gates. The module possesses serial and parallel inputs and outputs. Using its parallel input, the module receives the flits from the router input ports. The PCM parallel output is connected to the output ports. When a fault occurs in the (NAi,Ri) channel, the PCM, to prevent the fault propagation into other routes, multicasts the faultless route packet identified by comparison to the output ports exclusive of local ports. Table-based routing is a common approach for a fault-tolerant NoC. A Mesh-based NoC with faulty links is an irregular architecture [29, 36] and a well-known routing technique for irregular architecture based on Routing Tables (RT) [28, 39]. The PCM possesses another output connected to the routing table. Employing this output, the RT gets immediately informed of faulty channels list and is hence updated. Knowing the faulty routes and updating the tables are considered as the main necessities to increase a NoC fault tolerance capability. Due to the module s test, the serial input and output are considered based upon scan-based test. The testing of PCM

6 506 J Electron Test (2017) 33: Table 2 Faultlocationinthe2 2MeshbasedNoC States R0 R1 R2 R3 i2 i1 i0 F_ch Fl_ch F_ch Fl_ch F_ch Fl_ch F_ch Fl_ch No diagnosis No diagnosis No diagnosis (NA2,R2) (R2,R3) (NA1,R 1 )(R 1,R 3 )(NA 3,R 3 ) (NA3,R3) (R3,R2) (NA0,R0) (R0,R2) (NA2,R2) (NA0,R0) (R0,R1) (NA3,R3) (R3,R1) (NA1,R1) (NA1,R1)(R1,R0) (NA2,R2) (R2,R0) (NA0,R0) No diagnosis (NA1,R1) (R1,R3) (NA2,R 2 )(R 2,R 3 )(NA 3,R 3 ) (NA0,R0) (R0,R2) (R3,R2) (NA3,R3) (NA2,R2) (NA2,R2)(R2,R0) (NA1,R1)(R1,R0)(NA0,R0) (NA3,R3)(R3,R1) (NA0,R0) (R0,R1) (NA1,R1) (NA3,R3) (NA1,R1) (R1,R3) (NA2,R2) (R2,R3) - (NA1,R1) (R1,R3) (NA2,R2) (R2,R3) (NA3,R3) (NA2,R2) (NA0,R0) (R0,R2) (NA3,R) (R3,R2) (NA1,R1) (NA0,R0) (R0,R1) (NA3,R3) (R3,R1) (NA0,R0) (NA1,R1)(R1,R0)(NA2,R2) (R2,R0) - (NA0,R0) (R0,R2) (NA3,R3) (R3,R2) (NA2,R2) - (NA0,R0) (R0,R1) (NA3,R3) (R3,R1) (NA1,R1) (NA1,R1)(R1,R0)(NA2,R2) (R2,R0) (NA0,R0) 1: faultless 0: faulty F_ch: faulty channels Fl_ch: faultless channels Table 3 Routers threshold and diagnosis capability in the proposed methodology Router Diagnosis threshold (p-2) States Diagnosable is not our focus in this paper. Figure 5 illustrates PCM connections inside a router. It might occur to mind that the faults with quite identical impacts can take place on the routes and PCM considers rout as faultless by mistake. An answer that can be presented here is that as we explained the number of shorts for a single channel with the wire number of n=10equals N S =1013shorts. Accordingly, the possibility for the effect similarity of two faults in one channel equals 1/1013. Let s suppose that the two packets entered from i 0 and i 1 routes are identical; then, the probability that a similar fault occurs on i 0 and i 1 inputs P(i0 faulty = i1 faulty )equals: Pi0 faulty ¼ i1 faulty ¼ Pi0ch ð i1 ch1 i1 ch2 Þ ¼ Pi0 ð ch Þ Pi1 ð ch1 Þ Pi1 ð ch2 Þ ¼ ¼ 9:6e 10 If we want to compute the occurrence probability of a similar fault on i 1 and i 2 inputs; that is P(i1 faulty = i2 faulty ), then we have: Pi1 faulty ¼ i2 faulty ¼ Pi1ch1 ð i1 ch2 i2 ch1 i2 ch2 Þ ¼ Pi1 ð ch1 Fig. 5 Packet Comparing Module Þ Pi1 ð ch2 Þ Pi2 ð ch1 Þ Pi2 ð ch2 Þ ¼ ¼ 9:5e 13 Routing Table PCM No diagnosable Diagnosis capability 3-port % 4-port % 5-port %

7 J Electron Test (2017) 33: Of 1013 faults, needless to say, there are faults that tend to have identical effects on the channel. It can be concluded that, even knowing this position, when the PCM indicates two packets equality; it does not necessarily mean two routes with similar faults but rather two faultless routes. This conclusion can be generalized to four-port and five-port routers as well. 4.5 Test Mechanism and Fault Diagnosis Two practical mechanisms can be utilized to perform the approach proposed: 1) Zonal test and 2) global test. In the zonal mechanism, the entire network is divided into several sub-networks in which the fault searching is accomplished. The entire NoC, in this method, can be divided into 2 2 sub-networks through various configurations; and each sub-network can be tested in differing test rounds. This is the work employed in such investigations as [16, 18, 30, 31]. This methodology enables the possibility of online functional test. In the global test, however, the entire network is tested by a single configuration. All channels, in this method, are simultaneously filled up with test patterns and then the results are received. This methodology allows the possibility of non-concurrent online and offline structural. Selecting one of these mechanisms is accomplished based on the trade-off between the test time and the network efficiency. In this paper, we employed the global test mechanism to perform the proposed approach. This selection is true for the simulations as well. One round (two execution phases) are required to complete the test: First phase: In this step, TPG 0,TPG 1,.., TPG n generate test packets with identical contents of 0, 1,, n and release them in the network. The response analyzer unit, on the other side, receives the results of TRA 0, TRA 1,.., TRA n. The packet containing 0, according to HSTP, passes through the three channels of (NA 0, R 0 ), (R 0, R 1 ), and (R 1, NA 1 ) to move from TPG 0 and reach TRA 1. Each router, besides, receives test packets for the number of its inputs. The PCM, then, checks the table situations. In this step, the two states of table (i.e. B111^ and B110^) are checked. If the B111^ state is established, it means that all route s channels are faultless. If the module confirms the B110^, then a fault has occurred in the (NA i, R j ) channel. In Table 3, it should be noted that the (R i,na i ) channel has not been checked. The reason behind this is that this channel checking is the responsibility of TRA located in the NA. The PCM after detecting a flit as faultless healthy directs it to the (R i, NA i ) channel and then the TRA decides on it as either being faulty or faultless as soon as receives the flit. In this way, the (R i,na i ) and (NA i,r i ) channels task in the entire network is determined. Second phase: This step resembles the first one. The only difference is that here the B011^ and B101^ are checked. This happens in this step since the fault presence in the (NA i,r i ) has been checked. The two states, therefore, indicate the fault on the (R i, R j ) channel. In the second phase, generally, the channels task among the routers is determined. To remind, if a fault is detected in the first round on the (NA i,r i ) channel, the PCM then distributes the faultless packet, which has detected in the first phase, to the output ports (exclusive of local ports). Generally, the faults on the channels between the Router- NA and Router-Router are detected and located in the first and second phases, respectively. 5 Fault Diagnosis Capability and Scalability Implementing the proposed approach, as discussed, in a three-port router two channels are tested in the first and second phases of test process, respectively. In the fourportroutersinthefirstandsecondphasestwoandthree channels are tested while in the five-port routers in the first and second phases two and four channels are tested, respectively. Test coverage is a capability by which the number of channels being tested in a round is computed. The test coverage in the approach proposed, generally, equals 100% in the execution round. Figure 6 depicts the test coverage in the phases for different NoC size. The Mesh based NoCs diagnosis capability can be computed in various dimensions provided that each router s diagnosis TEST COVERAGE first phase second phase NOC SIZE Fig. 6 Test coverage percentage in the various network dimensions

8 508 J Electron Test (2017) 33: capability is considered. In Table 4, the diagnosis capability has been computed for each network. Scalability refers to a method s efficiency in differing scales. In Fig. 7, the increase rate of diagnosis capability has been illustrated. The diagram clearly demonstrates when the NoC size increases; the NoC diagnosis capability does as well. This is because by enhancing the NoC sizes the number of 5- port routers will be increased. Whereas the fault diagnosis capability of 5-port routers is higher than 4-port and 3-port routers (see Table 3). DIAGNOSIS CAPABILITY NOC SIZE Fig. 7 The proposed approach scalability 6 Hardware Considerations To implement the proposed approach on an NoC-based system, generally, three hardware units are imposed on the system: 1) PCM, 2) TPG, and 3) TRA. To compute the hardware overhead, the PCM is simulated, synthesized, and implemented on ISE Xilinx [52] with Spartan 3E platform [44]. The simulation results are indicated in Table 5 for all three routers. Additionally, the hardware redundancy in the approach proposed has been compared with the previous routers hardware. The TPG and TRA, in the proposed approach, have been eliminated from the routers and replaced with a PCM. In each NA, however, there is a constant pair of TPG and TRA. If the work [30] is considered as the reference for the TPG implementation (341 gates) and test manufacturing unit (401 gates), the entire hardware added for each network can be computed. In Table 6, the hardware overhead in the proposed approach for various network dimensions has been demonstrated. 7 Test Timing In our proposed approach, we considered the tester as a distributed test program on all functional cores. Accordingly, starting and ending the test operations are accomplished in the software. To compute the test time, packet generation start time in the TPG and the final packet analysis by the TRA are considered as the criteria. As discussed in the test mechanism section, in the first and second test phases the test packet containing patterns is required to pass through all routes. In each phase, subsequently, one test packet is generated and released in the network. Both packets are incessantly generated to parallelize and decrease the test time. In Fig. 8, the transmitted signals and data in a 2 2 Mesh based NoC being tested can be observed. All the TPGs generate the test packets and the TRA analyzes them in a parallel fashion. The point seen in the TRA waveform is that, in the first round, this unit receives the faultless flits and then detects the fault on the (R i,na i ) channel. In the second phase, the PCM takes the unit inactive times to its own advantage and transmits its analysis results to the NA (fault information). The tester, in this way, gets benefited from the results obtained by the PCM. If we consider the number of wires in the channel equal to n = 10,then we need 10 patterns to detect the short faults. Each test packet, accordingly, consists of 12 flits (two flits are added for the head and tail). If each flit in the TPG is generated in a single clock; then, to compute the packet manufacturing time in the TPG, T TPG, we have: Table 4 Fault diagnosis capability in the proposed approach Size All Bidirectional channels #Routers #Core Locatable faulty 5-p channels 3- p 4- p Diagnosis capability % % % % 8* % 16* %

9 J Electron Test (2017) 33: Table 5 The hardware overhead in the proposed approach Router Packet Comparing Module (PCM) RASoC (1688 Gates) [55] LUT BELS Hermes (631 LUT) [40] Aetheral (27,000 LUT) [25] Vici (20,413 gates) [23] 3-port % 10.9% 0.28% 0.37% 4-port % 22.8% 0.61% 0.8% 5-port % 49.6% 1.1% 1.5% T TPG ¼ no:of test packet flits time to generate one flit ð4þ On the other hand, the test packet passes through two routers and three channels. If we suppose switching mechanism to be a Wormhole and we consider the packet passage time from the channel to be one clock and the packet passage time from the router to be five clocks, then the T TPT test packet time is: T TPT ¼ t router þ t channels ð5þ If the time required for the TRA to analyze a single flit to be one, then, to compute the packet analysis time in the TRA, T TRA,wehave: T TRA ¼ no:of flits time to analyze one flit ð6þ The T phase, the phase time equals the test packet manufacturing total time, test packet transmission time, and response analysis time: T phase ¼ T TPG þ T TPT þ T TRA ð7þ The test time T test is the total times of the first and second phases: T test ¼ 2 T phase ð8þ Finally, since all IP cores perform the test functions in a parallel fashion, NoC channels test time equals: T NoCChannels ¼ 70 clock 8 Simulation Results and Comparisons To evaluate the proposed test method, we implemented a 5*5 Mesh based NoC on the SystemC-based cycle accurate simulator with the settings in Table 7. ThissizeofNoC,inthe investigations, can suggest more stable results for the simulation. Then we run the NoC and inject the faults to channels. We increased the fault injection till the threshold (i.e. p-2); and even, this went over the threshold and we injected p number of faults in each router to evaluate the performance quality in the approach proposed. In Fig. 9, the proposed approach effect on the network evaluation parameters has been compared with random traffic. As indicated by the results above, an up and down can be observed in the delay and power consumption diagram. This point reveals the diagnosis threshold in the proposed approach. The ups and downs occurred, in other words, are those faults that the proposed approach can locate them. The figure depicts that the diagram has approximately reached its peak at 75. Owing to the fact that 25 (R, NA) channel faults are detected Table 6 The hardware overhead in the proposed approach Mesh All channels Our method NHR (Gates) TPG TRA PCM P3 P4 P , , , ,842 NHR Network Hardware Redundancy, P3: 3-port, P4: 4-port, P5: 5-port.

10 510 J Electron Test (2017) 33: Fig. 8 Timing in the proposed approach NA0/TPG Head 0 )local( i0 Head 0 Tail 0 Head 0 Tail 0 Head 0 Tail 0 Tail 0 R0 i1 Head 1 Head 1 i2 Head 2 Head 2 NA0/TRA Time to transfer the result from PCM to NA NA1/TPG Head 1 Head 1 )local( i0 Head 1 Head 1 R1 i1 Head 0 Tail 0 Head 0 Tail 0 i2 Head 3 Head 3 NA1/TRA Time to transfer the result from PCM to NA NA2/TPG Head 2 Head 2 )local( i0 Head 2 Head 2 R2 i1 Head 0 Tail 0 Head 0 Tail 0 i2 Head 3 Head 3 NA2/TRA Time to transfer the result from PCM to NA NA3/TPG Head 3 Head 3 )local( i0 Head 3 Head 3 R3 i1 Head 1 Head 1 i2 Head 2 Head 2 NA3/TRA Time to transfer the result from PCM to NA PCM Test packet First phase PCM Test packet Second phase Test time in TRA; a total of 100 faults whose proposed diagnosis threshold is for a 5 5 Mesh based NoC will be accordingly detected. The approach proposed has managed to discover the faults injected and detect their locations occurred from the inception till this point. The reason the network delay and power consumption have increased to this point is that the PCM has been active for the faults below the threshold. The network delay and power consumption has therefore increased. After the number of faults has exceeded the threshold, the PCM has failed to detect the faults and hence deactivated. The PCM, subsequently, treats the faulty packet as it does the ordinary network packets. For this reason, the network delay and power consumption has dropped at this point. The second diagram illustrates a network implementation results with the same dimensions but with random traffic. The diagram is displayed to compare the proposed method s performance with a random traffic. The network throughput will approximately remain stable since the number of flits arrives have been considered similar for all situations. The proposed methodology has been, eventually, compared with the previous methods in terms of scalability, fault coverage, hardware redundancy, test time, and test rounds that has been illustrated in the Table 8. By a brief look at the Table 8, it can be realized that the proposed methodology excels all the previous ones in terms of the scalability, test rounds and test time; and it works better than the previous methods with respect to the hardware redundancy and fault coverage. Table 7 Simulation settings Mesh Flit size Packet length Channel width Injection rate Drained packet Simulation time Warm up 5* ,

11 J Electron Test (2017) 33: Fig. 9 The proposed approach effect upon 5 5 Mesh based NoC efficiency parameters AVR. DELAY proposed random traffic POWER CONSUMTION proposed random traffic NO. FAULTY CHANNELS NO. FAULTY TRAFFIC 9 Conclusion In the current paper, a BIST-based test approach was proposed to detect and locate the short faults in the communication data links. To implement the approach, it requires creating a SHTP as well as injecting test packets with test pattern payload in the network. The TPG generates and distributes the test packets to its destination neighbors in the network. Owing to the fact that the packets entering the router from a couple of routes possess an identical pattern, one can realize the fault presence in a route through comparing the packets. The comparison is accomplished by the PCM. The proposed methodology is performed in one round (two phases); in the first phase the faults on the (NA i,r i ) bidirectional channel and in the second phase the short faults on the (R i,r j ) bidirectional channel are detected and located. The proposed methodology, therefore, demonstrates 100% test coverage and 84% fault diagnosis capability on channels for the NoCs with a high scale. The key to the methodology proposed is its scalability which is confirmed when the network dimension increases. The simulation results indicate that the PCM tends to be very insignificant when compared with RASoC HERMES Æthereal و Vici routers hardware. Implementing this methodology, in addition, increases the network power consumption and delay to the threshold in a 5 5 Mesh based NoC; and having exceeded the threshold, the network power consumption and delay decreases. Our proposed methodology has managed to decrease the test time for the entire NoC to 70 clocks through parallel test implementation on the channels. This test time remains stable for various network dimensions. As an upcoming work, one can concentrate on the combining of this method with the router testing methods and PCM self-testing method and PCM designing to employ the routers own resources and hence to impose lower overhead on the system. More importantly, novel investigations can be conducted to increase the proposed methodology s diagnosis capability. Table 8 Comparing the proposed approach by previous works in terms of scalability, fault coverage, hardware redundancy, test time, and test rounds Methods Year S FC (%) HR (gate or %) TT (cycle) TR Grecu et al. [26] *8 Na 166, Peterson et al. [43] * % 5100 Na Cota et al. [18] *5 na Herve et al. [30] * Concatto et al. [16] * ,8% Na 9 Raik et al. [47] * % Herve et al. [31] * Strano et al. [45] * % Kakoee et al. [34] * % Na 9 Ghofrani et al. [24] * % Na 4 Kakoee et al. [35] * % Na 9 Bhowmik et al. [11] *4 100 na Our approach * % 70 1

12 512 J Electron Test (2017) 33: References 1. Agarwal A, Iskander C, Shankar R (2009) Survey of network on chip (NoC) architectures & contributions. Journal of Engineering, Computing and Architecture 3(1): Aghaei B, Babaei S (2009) The new test wrapper design for core testing in packet-switched micro-network on chip. In: Proceedings 2nd IEEE International Conference on Power Electronics and Intelligent Transportation System, pp Aghaei B, Khademzadeh A, Reshadi M, Badie K (2017) Link testing: a survey of current trends in network on chip. J Electron Test 33(2): Alaghi A, Karimi N, Sedghi M, Navabi Z (2007) Online NoC switch fault detection and diagnosis using a high level fault model. In: Proc. 22nd IEEE International Symposium on Defect and Fault- Tolerance in VLSI Systems (DFT), pp Alamian SS, Fallahzadeh R, Hessabi S, Alirezaie J (2013) A novel test strategy and fault-tolerant routing algorithm for NoC routers. In: Proc. 17th IEEE CSI international Symposium on Computer Architecture & Digital Systems (CADS), pp Amory AM, Brião E, Cota É, Lubaszewski M, Moraes FG (2005) A scalable test strategy for network-on-chip routers. In: Proc. IEEE International Test Conference (ITC), pp Amory AM, Goossens K, Marinissen EJ, Lubaszewski M, Moraes F (2007) Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. Comp Digit Tech, IET 1(3): Babaei S, Mansouri M, Aghaei B, Khadem-Zadeh A (2011) Online-structural testing of routers in network on chip. World Appl Sci J 14(9): Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. Computer 35(1): Bhowmik B, Deka JK, Biswas S (2015) An odd-even model for diagnosis of shorts on NoC interconnects. In: Proc. Annual IEEE India Conference (INDICON), pp Bhowmik B, Biswas S, Deka JK (2016) Impact of NoC interconnect shorts on performance metrics. In: Proc. 22nd IEEE National Conference on Communication (NCC), pp Bhowmik B, Deka JK, Biswas S (2016) An on-line test solution for addressing interconnect shorts in on-chip networks. In: Proc. 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pp Borkar S (2007) Thousand core chips: a technology perspective. In: Proceedings 44th ACM Annual Design Automation Conference, pp Chen G (2013) SPAcENoCs: a scalable platform for FPGA accelerated emulator of NoCs. Texas A&M University 15. Cheng AC (2002) Comprehensive study on designing memory BIST: algorithms, implementations and trade-offs. Ann Arbor 1001: Concatto C, Almeida P, Kastensmidt F, Cota E, Lubaszewski M, Herve M (2009) Improving yield of torus NoCs through faultdiagnosis-and-repair of interconnect faults. In: Proc. 15th IEEE International On-Line Testing Symposium, pp Cota É, Carro L, Lubaszewski M (2004) Reusing an on-chip network for the test of core-based systems. ACM Trans Des Autom Electron Syst 9(4): Cota E, Kastensmidt FL, Cassel M, Hervé M, Almeida P, Meirelles P, Amory A, Lubaszewski M (2008) A high-fault-coverage approach for the test of data, control, and handshake interconnects in mesh networks-on-chip. IEEE Trans Comput 57(9): Cota É, de Morais AA, Lubaszewski MS (2012) Test and diagnosis of routers. In: Reliability, Availability and Serviceability of Networks-on-Chip. Springer, pp Cuviello M, Dey S, Bai X, Zhao Y (1999) Fault modeling and simulation for crosstalk in system-on-chip interconnects. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceeding IEEE Design Automation Conference, pp Dally WJ, Towles BP (2004) Principles and practices of interconnection networks. Elsevier, Amsterdam (Imprint: Morgan Kaufmann) 23. Fick D, DeOrio A, Hu J, Bertacco V, Blaauw D, Sylvester D (2009) Vicis: a reliable network for unreliable silicon. In: Proceeding 46th ACM Annual Design Automation Conference, pp Ghofrani A, Parikh R, Shamshiri S, DeOrio A, Cheng K-T, Bertacco V (2012) Comprehensive online defect diagnosis in on-chip networks. In: Proc. 30th IEEE VLSI Test Symposium, pp Goossens K, Dielissen J, Radulescu A (2005) Æthereal network on chip: concepts, architectures, and implementations. IEEE Design Test Comput 22(5): Grecu C, Pande P, Ivanov A, Saleh R (2006) BIST for network-onchip interconnect infrastructures. In: Proc. 24th IEEE VLSI Test Symposium, pp Han T, Choi I, Oh H, Kang S (2014) A scalable and parallel test access strategy for NoC-based multicore system. In: 23rd IEEE Asian Test Symposium (ATS), pp Hassan A, Rajski J, Agarwal VK (1988) Testing and diagnosis of interconnects using boundary scan architecture. In: Proceeding IEEE International Test Conference, New Frontiers in Testing, pp Henkel J, Wolf W, Chakradhar S (2004) On-chip networks: a scalable, communication-centric embedded system design paradigm. In: Proceeding 17th IEEE International Conference on VLSI Design, pp Herve M, Cota E, Kastensmidt FL, Lubaszewski M (2009) Diagnosis of interconnect shorts in mesh NoCs. In: Proc. 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp Hervé M, Almeida P, Kastensmidt FL, Cota E, Lubaszewski M (2010) Concurrent test of network-on-chip interconnects and routers. In: Proc. 11th Latin American Test Workshop 32. Holsmark R, Kumar S (2005) Design issues and performance evaluation of mesh NoC with regions. In: Proc IEEE NORCHIP, pp Hosseinabady M, Dalirsani A, Navabi Z (2007) Using the inter-and intra-switch regularity in NoC switch testing. In: Proc. European Conference on Design, Automation and Test and EDA Consortium, pp Kakoee MR, Bertacco V, Benini L (2011) A distributed and topology-agnostic approach for on-line NoC testing. In: Proc. Fifth ACM/IEEE International Symposium on Networks-on- Chip, pp Kakoee MR, Bertacco V, Benini L (2014) At-speed distributed functional testing to detect logic and delay faults in NoCs. IEEE Trans Comput 63(3): Kautz WH (1974) Testing for faults in wiring networks. IEEE Trans Comput 100(4): Kim J-S, Hwang M-S, Roh S, Lee J-Y, Lee K, Lee S-J, Yoo H-J (2004) On-chip network based embedded core testing. In: Proceeding IEEE International SoC Conference, pp Krstic A, Cheng K-T (1998) Delay fault testing for VLSI circuits, Springer Science & Business Media 39. Lien J-C, Breuer MA (1991) Maximal diagnosis for wiring networks. In: Proceeding International Test Conference, pp Moraes F, Calazans N, Mello A, Möller L, Ost L (2004) HERMES: an infrastructure for low area overhead packet-switching networks on chip. VLSI J Integ 38(1):69 93

13 J Electron Test (2017) 33: Nazari M, Zolfy Lighvan M, Daie Koozekonani Z, Sadeghi A (2016) A novel HW/SW based NoC router self-testing methodology. arxiv preprint arxiv: Nazarian G (2008) On-line testing of routers in networks-on-chip. PhD thesis, Delft University of Technology 43. Petersén K, Öberg J (2007) Toward a scalable test methodology for 2D mesh network-on-chips. In: Proc. European Conference on Design, Automation and Test and EDA Consortium, pp Spartan XD (2013) 3E FPGA family data sheet. DS312 (July 19) 45. Strano A, Gómez C, Ludovici D, Favalli M, Gómez ME, Bertozzi D (2011) Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In: Proc. IEEE Design, Automation & Test in Europe, pp Stroud CE (2002) A Designer's guide to built-in self-test. Springer Science & Business Media 47. Ubar R, Raik J (2003) Testing strategies for networks on chip. In: Networks on Chip. Springer, pp Vermeulen B, Dielissen J, Goossens K, Ciordas C (2003) Bringing communication networks on a chip: test and verification implications. IEEE Commun Mag 41(9): Xiang D, Shen K (2016) A new unicast-based multicast scheme for network-on-chip router and interconnect testing. ACM Trans Des Autom Electron Syst 21(2): Xiang D, Zhang Y (2011) Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme. IEEE Trans Compr-Aided Design Integ Circ Syst 30(1): Xiang D, Chakrabarty K, Fujiwara H (2016) Multicast-based testing and thermal-aware test scheduling for 3D ICs with a stacked network-on-chip. IEEE Trans Comput 65(9): Xilinx I (2014) Design Suite version: Ying Z, Ning W, Fen G, Xin C, Lei Z (2013) Novel Core test wrapper design supporting multi-mode testing of NoC-based SoC. Inter J Control Autom 6(5): Zeferino CA, Kreutz ME, Carro L, Susin AA (2002) A study on communication issues for systems-on-chip. In: Proc. 15th IEEE Symposium on Integrated Circuits and Systems Design, pp Zeferino CA, Kreutz ME, Susin AA (2004) RASoC: a router softcore for networks-on-chip. In: Proc. IEEE Design,, Automation and Test in Europe Conference, pp Babak Aghaei received the B.Sc. degree in Computer Engineering- Hardware major in Shomal University, Amol, Iran in 2007 and the M.Sc. degree in computer architectures in Islamic Azad University, Tabriz Branch, Iran in Currently, he is Ph.D. candidate in computer engineering-hardware in Islamic Azad University, Science and research Branch, Tehran, Iran. His field studies are system on chip, Network on chip test and testability, fault tolerant, reliability, embedded systems. Ahmad Khademzadeh was born in Mashhad, Iran, in He received the B.Sc. degree in applied physics from Ferdowsi University, Mashhad, Iran, in 1969 and the M.Sc., Ph.D. degrees respectively in Digital Communication and Information Theory and Error Control Coding from the University of Kent, Canterbury, U.K. He is currently the Head of Education and National Scientific and Informational Scientific Cooperation Department at Iran Telecom Research Center (ITRC). He was the head of Test Engineering Group and the director of Computer and Communication Department at ITRC. He is also a lecturer at Tehran Universities and he is a committee member of Iranian Computer society and also a committee member of the Iranian Electrical Engineering Conference Permanent Committee. Dr. Khademzadeh has been received four distinguished national and international awards including Kharazmi International Award, and has been selected as the National outstanding researcher of the Iran Ministry of Information and Communication Technology. Midia Reshadi received his M.Sc. degree in computer architecture from Science and Research Branch of Islamic Azad University (SRBIAU), Tehran, Iran in He also received his Ph.D. degree in computer architecture from SRBIAU, Tehran, Iran in He is currently Assistant Professor in Faculty of Electrical and Computer Engineering of SRBIAU. His research interests include Photonic NoCs, fault and yield issues in NoCs, routing and switching in on-chip communication networks. He is a member of IEEE. Kambiz Badie is currently Knowledge Management and e- Organizations Group, IT Research Faculty, Research Institute for ICT, Tehran, Iran. He received all his degrees from Tokyo Institute of Technology, Japan, majoring in pattern recognition. His interest for pattern recognition lies mostly in his motivation for grasping the mechanisms behind cognitive processes such as perception, intuition, imagination and interpretation. Dr. Badie is one of the active researchers in the areas of interdisciplinary and interdisciplinary studies in Iran, and has a high motivation for applying intelligent/ cognitive modeling methodology to the human issues.