E&CE 429 Computer Structures

Transcription

1 E&CE 429 Computer Structures Winter 2010 P. Dasiewicz, x32866, DC-2530 E&CE 429 W'10 1

2 ECE 429 Course References: D. A. Patterson and J. L. Hennessy, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, CA Second edition OR Third Edition OR Fourth Edition E&CE 429 Computer Structures Winter 2010, Lecture Transparencies and Readings, V4. Available in UW Bookstore. E&CE 429 W'10 2

3 DC Library Reserves D. A. Patterson and J. L. Hennessy, Computer Architecture: A Quantitative Approach, Second edition, Morgan Kaufmann, San Mateo, CA, (library call number: QA76.9.A73P ) D. A. Patterson and J. L. Hennessy, Computer Architecture: A Quantitative Approach, Third edition, Morgan Kaufmann, (library call number: QA76.9.A73 P ) E&CE 429 W'10 3

4 ECE 429 Teaching Assistant: Mohammed Majed Al-Shawa Lecture Times: Mon., Wed., Fri.: 11:30-12:20PM; RCH Tutorial Times: Wed 4:30-5:20PM ; RCH-105 No tutorial this week. E&CE 429 W'10 4

5 Sending s NOTE: when sending to a TA or the course instructor, the must be sent from a University of Waterloo mail server (e.g. engmail, ec , etc.) with your official UofW userid. from 'hotmail' and the like will most likely be ignored, deleted, filtered out as 'junk' or a reply sent to resend the from a University of Waterloo server with a valid UofW userid. If the is important to you, then follow the correct procedure. E&CE 429 W'10 5

6 ECE 429 Course web site: You will find: problem set solutions, old exams, etc. Freely accessible from.uwaterloo.ca domain, but from outside may need: Userid: xxxxxx Password: xxxxxx E&CE 429 W'10 6

7 Marking Scheme Marking Scheme: (no project) Midterm 40%, final 60% or Midterm 20%, final 80% Take the best mark OR... E&CE 429 W'10 7

8 Course Overview Case studies of various processor architectures throughout the course derived from the course readings DLX overview Introduction to Pipelining Execution cycles Basic pipeline for DLX Hazards Structural : resource conflicts Data : forwarding, instruction interdependence Control : branches, jumps, changes to PC Pipeline stalls E&CE 429 W'10 8

9 Course Overview[2] Static branch prediction strategies No prediction Predict not taken Predict taken Delayed branch Instruction / Pipeline Scheduling Hazard detection, reduce control hazard stalls, branch penalties Delayed branch scheduling strategies E&CE 429 W'10 9

10 Course Overview[3] Dealing with interrupts Multicycle execution floating point units Dealing with out-of-order execution Dynamic vs. Static pipeline scheduling Scoreboard approach Tomasulo s algorithm Dynamic branch prediction strategies Superscalar and VLIW architectures E&CE 429 W'10 10

11 Course Overview[4] Caches placement strategies identification strategies replacement strategies write strategies sources of misses E&CE 429 W'10 11

12 Course Overview[5] Virtual Memory Mapping schemes 0-level, 1-level, 2-level, Address translation caches (translation lookaside buffers) Virtual memory and caches Segmented VM Protection and VM Improving the performance of VM E&CE 429 W'10 12

13 Course Overview[6] I/O Interfacing I/O performance measures some queueing theory Architecture overview: SISD, SIMD, MIMD, MISD Performance models: 2-processor, N-processor E&CE 429 W'10 13

14 Course Overview[7] Cache coherence protocols: Snooping, Directory, MESI based Sequential consistency Strong/weak ordering of storage access Cache based multiprocessor scenarios Multiprocessor synchronization E&CE 429 W'10 14

15 Course Overview[8] Java Virtual Machine -> picojava architecture Overview of Past/Present Intel and AMD processors Intel: 8086 to Pentium 4, and P6 family architecture AMD: K6 2/3, Athlon architectures Others... E&CE 429 W'10 15

16 from: In 1965, Intel co-founder Gordon Moore saw the future. His prediction, now popularly known as Moore's Law, states that the number of transistors on a chip doubles about every two years. E&CE 429 W'10 16