Memory: Past, Present and Future Trends Paolo Faraboschi

Transcription

1 Memory: Past, Present and Future Trends Paolo Faraboschi Fellow, Hewlett Packard Labs Systems Research Lab

2 Quiz ( Excerpt from Intel Developer Forum Keynote 2000 ) ANDREW GROVE: is there a role for more powerful computers? GUEST: More memory especially is very useful for us, you can start to think about having, like, the whole Web in RAM. ANDREW GROVE: Say that again. GUEST: We'd like to have the whole Web in memory, in random access memory. ANDREW GROVE: That requires a fair amount of memory (Laughter) GUEST: The Web, a good part of the Web, is a few terabytes. So it's not unreasonable. (Laughter)

3 The Good Ol Days Source:

4 The Good Ol Days Today $6-$10/GB NAND $0.3-$0.5/GB Source:

5 Things are becoming Very unbalanced! Argonne National Labs plans for leading-edge supercomputer Peak FLOP/s 10 PF 100 PF 1000 PF 2000 PF Memory 0.5 PB 5 PB 32 PB 50 PB Flops/Bytes

6 Challenges Bits are now electrons in boxes: The boxes are getting really small Can t make the boxes bigger Electrons are quantum particles They escape from small boxes It costs energy to keep electrons in boxes Using electrons to reliably store bits is getting very hard. 10 nm

7 more challenges has had a remarkable 40+ year life DDRx frequency: impressive - cell latency less impressive Intel Kbit die 8,000,000 x Today s 8 Gbit die DDRx capacity: fundamentally limited - DDR channels: 4 (common), 6-8 (stretch) - Single-ended DDR: 2-4 ranks/channel - Capacity/performance tradeoffs

8 and even more challenges supplier consolidation 23 in 1980, 6 in 2010, 3 in 2014 Source : TheMemoryGuy 2014 Mobile wagging the world Performance, cost, volume Source : SK Hynix

9 Memory in a Compute-Centric World Heavyweight node Lightweight node Memory is enslaved to the CPU memory channels A few channels per socket, bandwidth limited by off-chip pins Capacity limited by DDR standard Beyond few sockets, complexity causes diminishing return THE DATA-CENTRIC WORLD NEEDS SOMETHING BETTER!

10 Memory in a Data-Centric world Bigger data More system capacity Lower cost More chip density Deeper analysis More bandwidth Random access Byte addressability Energy efficiency More near-data intelligence Flatter hierarchy Fast NV, storage features Diverse use cases Flexible compute ratio

11 More bandwidth (beyond DDRx): Serially-attached Memory Example: Micron HMC Performance tier Small, fast, nearby, Processor private (probably) volatile Capacity Tier Large, resilient, persistent, a bit further away, complex interconnect fabric (in the future) nonvolatile

12 More bandwidth: 2.5D-3D integration to the rescue? 2.5D packaging on Silicon Interposer System-in-Package: Combination of 3D die stacking and 2.5D interposer integration 3D die stacking 8x93% stack 55% yield what your mom did not tell you about 3D stacking

13 Beyond : 3 technology candidates (all NV) Source: Yuan Xie, DoE Blackcomb project

14 Why we like ReRAM (memristors): ions to store information Ions (charged atoms) are much better behaved than electrons Heavier, and can be pushed by an electrical field Stay where you park them, even in a very small box (4F 2 ) A bit can be represented by the location of an ion in a box 0 + 1nm 1 + kω M Ω

15 Hot from the press

16 Architecting I/O attached PCIe Local + (or NAND) attached to I/O + Highest density + Storage properties + Independent fault domain CPU CPU NIC - Block access interface (KBs) - Poor random access - Long latency

17 RAM Buffer Architecting as Memory Load/Store, Block ( Type 1 or NVDIMM-N ) Load/Store Event Triggered No data copy required during access Capacity = Performance = ~ Block, (guarded) Load/Store ( Type 3 or NVDIMM-F ) Load/Store Async Block Some data copy required during access Capacity = Performance = (hit), (miss) Load/Store, Block ( Type 4 or NVDIMM-x ) Load/Store Sync No data copies required during access Capacity = Performance =

18 Architecting Direct Attach Local + NVC NVC + Shortest latency + Byte addressable + Fits scale-out model NVC CPU NVC CPU - DDRx limited (size, timing) - CPU unbalanced (fixed ratio) - Non-emancipated memory (same fault domain as CPU) - No storage features - Sharing requires NIC help NIC

19 Architecting Fabric Attach Fabric attached + Decoupled from CPU + Flexible GB/core ratio + Shareable + Storage properties + Random addressing + Separate fault domain - Longer latency - Memory fabric cost - 2-tier mem organization - Limited scale (is it still memory at 1us?) FC CPU NIC FC CPU Other Nodes Other Nodes Other Nodes Memory Fabric NVC

20 Open question #1 Converging Memory and Storage? Memory SoC Local Local Storage SoC Local Low Latency Load/Store Network SoC High-throughput SoC SoC Local +... Persistence Physical Server High Availability Local RAID Hot-swap Local Shared Local Manageable Local Scalable Physical Server Survives failures Local Shared nothing Physical Server Physical Server SoC SoC SoC Local... Local Local Network Shared something? Shared something Memory Pool

21 Open question #2: Memory-Side Acceleration? It may be time to revisit two decades of PIM / Active Memory/Smart Memory/Near data processing research - Example: Micron AP (Automata Processor)

22 Questions?