EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 10: Three-Dimensional (3D) Integration

Transcription

1 1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 10: Three-Dimensional (3D) Integration Instructor: Ron Dreslinski Winter 2016 University of Michigan 1 1 1

2 Announcements Upcoming lecture schedule Today: 3D-Integration, what is it? Thursday: Architecting in 3D 2/23: On-chip Interconnects 2/25: Off-chip Interconnects 3/1 & 3/3: Spring Break 3/8: Midterm Review, Structure for rest of lectures, Project Specification Midterm Exam: In-Class March 10 th, closed notes Reading Assignments: Suggested: 3D System Integration Technologies, E. Beyne. VLSI 06 For next lecture: Centip3De: A cluster-based NTC architecture with 64 ARM Cortex-M3 Cores in 3D Stacked 130nm CMOS Fick et al., IEEE Journal of Solid-State Circuits University of Michigan 2 2

3 What is 3D Integration Really just putting together individual dies into a larger package Earliest examples are wire-bonded stacks Class Discussion: What do you think the potential advantages are? What might be disadvantages? What segments does it make sense in? University of Michigan 3 3

4 3D Integration Advantages Better form-factor (size of the device) Great for integrating into small systems, or improving density of large systems Shorter Interconnects (better bandwidth) Don t have to go off-package, which can be slow, power hungry, and low bandwidth Heterogeneous Integration Different technology nodes (fast CMOS, low-power CMOS, DRAM, Battery, MEMS (sensors) Fine-grained testing, better yield of system Each layer can be tested before integration, ensuring working systems University of Michigan 4 4

5 3D Integration Disadvantages Cost (extra steps and/or materials to package it all together) Yield, depending on how it is done Thermal Constraints Already having issues with thermal (dark silicon), now they are on top of each other Tools support (CAD/EDA, verification) University of Michigan 5 5

6 Types of 3D Integration Wire-bonding [Source:Weerasekera-ICCAD 07] 2.5D Integration (Interposer based) 3D Integration (Through-Silicon Vias) [Source:Synopsis] Monolithic 3D Integration (Growth) [Source:Topol-ECTC 04] [Source:HP] University of Michigan 6 6

7 How About An Example University of Michigan 7 7

8 3D_IC for Real Chips Bob Patti, CTO Tezzaron Semiconductor 06/14/2011 8

9 What can 3D do for us? Why We Scale? Advantages Speed Power Cost Size >180nm 130nm 90nm 65nm 45nm 28nm 22nm 16nm 9

10 How Real is 3D??? 560µ Samsung 16Gb NAND flash (2Gx8 chips), Wide Bus DRAM Micron Wide Bus DRAM Intel CPU + memory OKI CMOS Sensor Xilinx 4 die 65nm interposer Raytheon/Ziptronix PIN Detector Device IBM RF Silicon Circuit Board / TSV Logic & Analog Toshiba 3D NAND 10

11 Span of 3D Integration Packaging Analog Wafer Fab Flash DRAM DRAM CPU 3D Through Via Chip Stack IBM/Samsung 3D-ICs 100-1,000,000/sqmm M Interconnects/device CMOS 3D IBM 1s/sqmm Peripheral I/O Flash, DRAM CMOS Sensors 100,000,000s/sqmm Transistor to Transistor Ultimate goal 11

12 A Closer Look at Wafer-Level Stacking Oxide Silicon Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) W (Tungsten contact & via) Al (M1 M5) Cu (M6, Top Metal) Super-Contact 12

13 Next, Stack a Second Wafer & Thin: 13

14 Stacking Process Sequential Picture Two wafer Align & Bond Course Grinded Fine Grinded High Precision Alignment Misalign=0.3um After CMP Si Recessed Top wafer Bottom wafer 14

15 Then, Stack a Third Wafer: 3rd wafer 2nd wafer 1st wafer: controller 15

16 Finally, Flip, Thin & Pad Out: This is the completed stack! 1st wafer: controller 2nd wafer 3rd wafer 16

17 3 rd Si thinned to 5.5um 2 nd Si thinned to 5.5um SiO 2 1 st Si bottom supporting wafer 17

18 3D Interconnect Characteristics SuperContact TM I 200mm Via First, FEOL SuperContact TM II 300mm Via First, FEOL SuperContact TM III 200mm Via First, FEOL SuperContact TM 4 200mm Via First, FEOL Bond Points Size L X W X D Material 1.2 µ X 1.2 µ X 6.0µ W in Bulk 1.6 µ X 1.6 µ X 10.0µ W in Bulk 0.85 µ X 0.85 µ X 10µ W in Bulk 0.40 µ X 0.40 µ X 2µ W in SOI 1.7 µ X 1.7 µ Cu Minimum Pitch <2.5 µ <3.2 µ 1.75 µ 0.8 µ 2.4 µ (1.1 µ) Feedthrough Capacitance 2-3fF 6fF 3fF 0.2fF << Series Resistance <1.5 Ω <1.8 Ω <3 Ω <1.5 Ω < 18

19 Relative TSV Size 19

20 Pitch and Interconnect SuperContact TM is 500f 2 (including spacing) Face to face is 350f 2 (including spacing) Chip on wafer I/O pitch is 35,000f 2 Standard cell gate is 200 to 1000f 2 3 connections Standard cell flip-flop is 5000f 2 5 connections 16 bit sync-counter is 125,000f 2 20 connections Opamp is 300,000f 2 4 connections f 2 is minimum feature squared 20

21 R8051/Memory 5X Performance 1/10th Power Tezzaron Semiconductor 06/14/

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23 New Apps New Architectures 23

24 Tezzaron 3D DRAM The Killer App: Split-Die Ø Ø Embedded Performance with far superior cost/density. 110nm DRAM node has better density than 45nm embedded DRAM. Ø 1000x reduction in I/O power. DRAM Customer Host Device I/O Pad area : Bumping or wire bonding 24

25 Die to Wafer With Stencils Diced Memory Stack Stencil Window CPU die 25

26 Logic on Memory 172 pads 199 I/O Bondpoints/ side Memory also acts as interposer 92 pads (528 total pads at edge, stagger 250um pad, 125um pitch ~1500 available pads) 8 DRAM ports 16x21 pad array >10µf bypass caps SS ~4,000pf 26

27 2-4 layer logic device Face to Face Bond 5x5 mm Octopus memory device 21.8x12.3 mm (2-5 layer) Controller Memory Memory Hyper-Integration 5-9 layer stacks Bond pads 528 available Stagger 125um pitch TSVs Layer 5 Layer 7 Layer 9 Layer Poly Copper Wire 21 (25) 32 (38) 34 (42) Al/W Wire Trans. Count 3B 3.1B 5.5B 27

28 Challenges 23 customer designs. Tools Partitioning tools 3D P&R Access Testing IEEE 1500 IEEE 1149 Standards Die level JEDEC JC-11 Wide bus memory Foundry interface 28

29 Summery 3D has numerous and vast opportunities!! New design approaches New ways of thinking New tools Poised for explosive growth Sensors Computing MEMS Communications 29

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31 Variations on a Theme Styles of bonding: Face-to-Face Face-to-Back Back-to-Back Styles of Stacking: Wafer-Level (Has yield issues) Die-Level (Has alignment issues, size of via) When do I insert the TSV FEOL (Front-end-of-line): Tezzaron style insert the TSV before metalization BEOL (Back-end-of-line): Etch a whole after the entire stack is made University of Michigan 31 31

32 Issues with Through-Silicon-Vias Silicon stress from thermal expansion Keep-out regions Strange metal choices (Tungsten and Copper donuts) Minimum density to prevent cupping/dishing when thinned University of Michigan 32 32