Research Statement. 1. On-chip Wireless Communication Network for Multi-Core Chips

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1 Research Statement Current Research Interests: My current research principally revolves around the broad topic of Network-on-Chip (NoC), which has emerged as the communication backbone for multi-core chips. In summary, my on-going research projects can be classified under three broad categories: (1) On-chip Wireless Communication Network for Multi-Core Chips (2) NoC-based hardware accelerators for bioinformatics and (3) Sustainable Computing. Below I present details of each of these projects and my future research plan. 1. On-chip Wireless Communication Network for Multi-Core Chips Introduction: Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multi-core Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between two distant cores causes high latency and power consumption. There have been efforts to improve NoC performance by introducing ultra-low-latency and low power express channels between highly separated nodes, where the performance gain is achieved by bypassing intermediate NoC switches/routers. These communication channels can be made even more efficient in terms of power and delay compared to their conventional counterparts, but they are still, basically, metal wires. According to the International Technology Roadmap for Semiconductors (ITRS) for the long term, improving characteristics of metal wires will no longer satisfy performance requirements and new interconnect paradigms are needed. Different revolutionary approaches such as optical interconnects, on-chip multi-band RF transmission lines and wireless interconnects with CMOS ultra wide band (UWB) technology have been explored. Photonic and RF NoCs insert single-hop communication links between distant cores and thereby significantly reduce latency and power dissipation. However, photonic links must overcome significant technological and manufacturing challenges to become viable for mass production. Though NoCs with RF interconnects can be built using existing CMOS technology, they require long on-chip transmission lines that serve as waveguides. UWB wireless NoC must employ multi-hop communication due to the short range of its on-chip wireless channels. In this project, we have proposed an innovative and novel approach, which simultaneously addresses the latency, power consumption and interconnect routing problems of NoCs: replacing multi-hop wireline paths with high-bandwidth single-hop long-range wireless links. Recent research has established characteristics of silicon integrated antenna operating in the millimeter (mm) wave range of a few tens to hundreds of GHz and it is now a viable technology for intra- and inter-chip communication. Moreover excellent emission and absorption characteristics leading to antenna- like behavior in carbon nanotubes (CNTs) operating at optical frequencies have been observed recently. These open up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas. Such a NoC presents unique opportunities and challenges, which should be investigated to make it mainstream. The transformational aspect of this research lies in addressing the on-chip interconnect problem from a fundamentally new perspective, namely by developing a wireless network at the nanoscale, as opposed to pursuing incremental improvements of relatively traditional methods of wired interconnection. Work done: In this project we are investigating design methodologies and technology requirements for scalable WiNoC architectures. We have proposed a hybrid small-world NoC architecture where closely spaced cores communicate through traditional metal wires, but long distance communication is predominantly achieved through the wireless links. We have already demonstrated that this hybrid WiNoC outperforms its wired counterparts in terms of network 1

2 throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC has been shown to be better than other emerging alternative NoCs. Findings of this work have been published in many papers already [4-6, 8, 11, 29-38]. I have given invited talks on this topic in various conferences. I have organized special sessions in conferences and also edited special issue in journals on this topic. Accomplishment: I am leading an interdisciplinary team consisting of experts on analog circuits, digital communications, antenna design and CNTs to work on the various aspects of WiNoCs. This team consists of researchers from WSU and also researchers from universities outside of WSU. Through this project, I have gained significant experience in leading large multidisciplinary research groups. The National Science Foundation (NSF) and the Army Research office (ARO) through multiple research grants support my group s work to carry out the investigations regarding WiNoCs. We are also in the process of establishing a state-of-the-art test and measurement facility at WSU through a NSF CRI grant. I have also won the NSF CAREER award in 2009 and the Anjan Bose outstanding researcher award from the College of Engineering and Architecture (CEA), WSU in 2013 for my work on WiNoCs. I have presented the outcomes of my group s work on WiNoC in special or hot-topic sessions in several reputed conferences. I participated in hot topic sessions at the IEEE Design, Automation and Test in Europe (DATE) conference in 2011 and I organized special sessions addressing novel interconnect architectures for multicore chips in IEEE International Symposium on Circuits and Systems (ISCAS) 2008 and in IEEE International Symposium on Network-on-Chips (NOCS) I was one of the speakers in a special session on this topic in CODES+ISSS 2010 and NOCS I also presented a tutorial on WiNoC in NOCS I also participated in a panel on wireless NoC at The 15th ACM/IEEE System Level Interconnect Prediction (SLIP) 2013 workshop. By organizing or participating in these special sessions and panels I have been able to create awareness regarding WiNoCs among a broad range of researchers both from academia and industry. Future direction: My group is currently extending the WiNoC research in a new direction by addressing reliability and security aspects of this emerging architecture. The wireless interconnect technology is capable of improving latency and power dissipation of NoC architectures. However, this emerging interconnect paradigm is in its formative stage and it imposes significant challenges pertaining to dependability. We are investigating various cross-layer design methodologies to address the reliability and security aspects of WiNoC-based multicore chips. We plan to (i) design the WiNoC network layer based on natural complex networks that will be fault tolerant even using an inherently unreliable emerging interconnect technology and (ii) develop countermeasure units in the data-link layer of the on-chip network stack that enable resilience against malicious attacks, which might result in under utilization or misuse of the on-chip wireless bandwidth. Initial findings of this work have been published in a few recent papers [5, 41, 43]. Another new project we are exploring is to study the capabilities of WiNoC-based multicore chips as the nodes for wireless multimedia sensor networks (WMSN). We propose the design and development of dependable and energy-efficient WMSNs with reliable WiNoC-enabled multicore processor-based nodes. Reliability and dependability of WiNoC-based multicore processors is going to be one of the major thrusts of my group for the next few years. 2. NoC-based hardware accelerators for bioinformatics Introduction: For this subset of research projects my aim is to design NoC-based chips for Bioinformatics. I am exploring the capability of NoCs to achieve the massive scale of computation power required by biocomputing applications. In this project, we propose to design, implement and evaluate hybrid wireless/wireline NoC architectures suitable for two major Please refer to my CV for the list of references 2

3 application classes in bioinformatics: (i) genomic/dna sequence analysis, and (ii) phylogenetics. Both of these classes are at the heart of the next generation biocomputing research. Work done: The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially growing sequence databases, computing this operation at a large-scale is becoming expensive. An effective approach to speed up this operation is to integrate a very high number of processing elements in a single chip so that the massive scales of fine-grain parallelism inherent in several bioinformatics applications can be exploited efficiently. NoC is a very efficient method to achieve such large-scale integration. In this work, we propose to bridge the gap between data generation and processing in bioinformatics applications by designing NoC architectures for the sequence alignment operation. Specifically, we (i) propose optimized NoC architectures for different sequence alignment algorithms that were originally designed for distributed memory parallel computers, and (ii) provide a thorough comparative evaluation of their respective performance and energy dissipation. While accelerators using other hardware architectures such as FPGA, General Purpose Graphics Processing Unit (GPU) and the Cell Broadband Engine (CBE) have been previously designed for sequence alignment, the NoC paradigm enables integration of a much larger number of processing elements on a single chip and also offers a higher degree of flexibility in placing them along the die to suit the underlying algorithm. The results show that our NoC-based implementations can provide above fold speedup over other hardware accelerators and above fold speedup over traditional CPU architectures. This is significant because it will drastically reduce the time required to perform the millions of alignment operations that are typical in large-scale bioinformatics projects. To the best of our knowledge, this work embodies the first attempt to accelerate a bioinformatics application using NoC [12, 49]. Phylogenetics is the study of evolutionary relationships between organisms based on their underlying genetic content. The term genome is used to collectively refer to all DNA in the living cell of an organism. Phylogenetic tree construction is the process of constructing an evolutionary tree based on the similarities and differences observed among the genomic DNA of a set of species. It is a fundamental problem in computational molecular biology with important applications that include drug discovery. In the tree the leaves represent species (known) and internal nodes represent common ancestral species (unknown). The heart of Maximum Parsimony-based phylogenetic reconstruction is the breakpoint median problem. It relies on breakpoint distance, which is a measure of how different two genomes are by their gene ordering. Principally, this reduces the problem to one of solving numerous instances of Traveling Salesman Problem (TSP) on graphs with bounded integer edge weights. However, even this restricted version of the TSP problem has been shown to be NP-Hard. Due to the compute-intensive nature, this problem has the potential to immensely benefit from the incorporation of the latest advancements in circuit design and evolving hardware architectures. An effective approach to speed up this operation is to integrate a very large number of processing elements in a single chip in order to efficiently exploit the inherent fine-grained massive parallelism. We have already demonstrated the design and performance evaluation of a NoC-based implementation for solving TSP under the bounded edge-weight model, as used in the computation of breakpoint phylogeny. Our approach takes advantage of fine-grain parallelism from the multiple processing elements (PEs) and uses efficient NoC architecture for inter-pe communication. To accelerate the application on hardware, our PE design optimizes a particular lower bound calculation operation, which typically tends to be the serial bottleneck in computation of a TSP solution. Experimental results show that this new implementation is able to achieve speedups of up to three orders of magnitude over state-of-the-art multithreaded software implementations. In phylogenetic inference, statistical estimation approaches such as Maximum Likelihood (ML) and Bayesian Inference provide more accurate estimates than other non-statistical 3

4 approaches. However, the improved quality comes at a higher computational cost, as these approaches, even though heuristic driven, involve optimization over multi-dimensional real continuous space. The number of possible search trees in ML is at least exponential, thereby making run-times on even modest-sized datasets to clock up to several million CPU hours. Evaluation of these trees, involving node-level likelihood vector computation and branch-length optimization, can be partitioned into tasks (or kernels), providing the application with the potential to benefit from hardware acceleration. The range of hardware acceleration architectures tried so far offer limited degree of fine-grain parallelism. In this project, we are exploring the design and performance evaluation of 2-D and 3-D NoC architectures for RAxML, which is one of the most widely used ML software suites. Specifically, we have implemented the computation kernels of the top three functions consuming more than 85% of the total software run-time. Simulations show that through appropriate choice of NoC architecture, and novel core design, allocation and placement strategies, our NoC-based implementation can achieve individual function-level speedups of 390x to 847x, speed up the targeted kernels in excess of 6500x, and provide end-to-end run-time reductions up to 5x over state-of-the-art multithreaded software [7]. Accomplishment: We are the first group to demonstrate capabilities of NoC-based hardware accelerators for a large spectrum of bioinformatics applications. The NSF currently funds our bioinformatics related project. We have also organized special sessions at International conferences on this topic. I am currently editing a special issue titled Hardware Acceleration in Computational Biology for IEEE Design and Test of Computers. Future direction: Currently, we are extending our bioinformatics related investigations by evaluating the performance of small-world network enabled WiNoC architectures for both sequence alignment and phylogenetics. In this work, our aim is to use bioinformatics applications as test cases to benchmark the performance of WiNoCs. Another related project that I am pursuing is efficient single-chip processor architectures that work as enablers for data processing and information extraction as part of the cyber physical system (CPS) framework targeted for biomedical and biological applications. I am collaborating with experts from the domains of body sensor networks (BSN) and CPS control algorithms to work on this project. 3. Sustainable Computing Introduction: Continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips widely adoptable in multiple domains. In the design of high-performance massive multicore chips, power and heat are dominant constraints. The increasing power consumption is of growing concern due to several reasons, e.g., cost, performance, reliability, scalability, and environmental impact. Increased power consumption not only raises chip temperature and cooling cost, but also decreases chip reliability and performance. In this work, we propose analytical and experimental methodologies and toolsets for the design and evaluation of sustainable multicore systems addressing power efficiency and thermal management while provisioning for the necessary performance trade-offs. Work done: In this work our aim is to demonstrate how the power and thermal efficiencies of multi-core chips designed with on-chip wireless links can improve even further by incorporating suitable dynamic voltage and frequency scaling (DVFS) schemes in the wireline links and processing cores. The overall energy dissipation of the WiNoC can be improved if the characteristics of the wireline links and the processing cores are optimized according to the traffic patterns and workloads respectively. DVFS is a popular methodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance. We are developing DVFS schemes to be applied to both the processing cores and the wireline links of WiNoCs to establish the power/thermal profile-performance trade-off for the multicore systems. Our aim is to develop an experimental toolset to establish the power-thermalperformance (PTP) trade-offs. We also plan to complement this effort by incorporating task 4

5 migration in the processing cores to improve the temperature profile of the multicore chips. The small-world WiNoC is shown to be capable of improving the overall latency and energy dissipation characteristics compared to the conventional mesh-based counterpart. While there is a significant temperature reduction in the network due to the WiNoC architecture, a loadimbalanced network is still susceptible to local thermal hotspots. We address the problem of network-induced temperature hotspots in WiNoC by incorporating a thermal-aware rerouting strategy. While the WiNoC itself can reduce the maximum mesh network temperature significantly, the thermal-aware rerouting strategy can successfully reduce hotspot temperatures even further without compromising the achievable performance benefits. Accomplishment: Initial findings of this project have been published in a few recent papers [2, 30, 33-35]. I have also presented some of the outcomes of this research in a hot topic session titled Energy-Efficient Design and Test Techniques for Future Multi-Core Systems at the IEEE Design, Automation and Test in Europe (DATE) conference in March of I was also the guest editor for a special issue on sustainable and green computing systems for the ACM Journal on Emerging Technologies in Computing Systems. I am also editing a book to be published by Springer on this topic. Future direction: I am actively pursuing new funding opportunities from various federal agencies to support this project. I am collaborating with several researchers both from WSU and outside WSU working on parallel processing, computer architecture and control theory to assemble a multidisciplinary team to work on this project. I am also working on NSF a REU proposal on this topic. This work is going to be one of the main thrust areas of my group for the next few years in addition to the reliability of WiNoC architecture related investigations mentioned above. Dissemination of Research Contributions: I try to widely disseminate outcomes of different research projects I am undertaking. I have published more than 70 peer-reviewed papers so far. I always target highly reputed peer-reviewed journals, such as IEEE Transactions on VLSI (TVLSI), IEEE Transactions on Computers (TC), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Journal of Electronic Testing: Theory and Applications (JETTA) etc for publishing outputs of my research projects. Additionally I always target very competitive conference proceedings for publishing my research contributions. In regards to publishing I try to publish initial findings in conference proceedings. Subsequently by incorporating comments received from the conferences I enhance the quality of the work and submit to journals. I make sure the graduate students working with me participate in publishing research papers. All of my graduate students have multiple publications. I have already graduated 5 PhD and many MS students. All of my PhD graduates are well established either in academia or in Industry. I have also given multiple invited talks at various conferences and IEEE chapters to present results of various research projects I am undertaking. 5