Architectures for Networks on Chips with Emerging Interconnect Technologies

Transcription

1 CMPE 750 Project Presentation Architectures for Networks on Chips with Emerging Interconnect Technologies Sagar Saxena 1

2 Content System on chip : Idea & overview Need for Multi-Core chip NOCs Paradigm Traditionally used & Limitation 2D Conventional NOCs architecture Wiring complexity Emerging interconnect technology 3D NOCs Photonic NOCs CORONA ARCHITECTURE FIREFLY ARCHITECTURE On- chip RF/wireless interconnect On-chip Antennas used Small world network : Wattz Strogatz Model 2

3 System on chip Technology Scaling Transistor count: exponential growth Prohibitive manufacturing costs Over 100 millions for today s SoCs 10M$ - 100M$ 0.13micron designs Reusability + Platform Based Design 3

4 System on Board vs. System on Chip Conceptually System on Chip refers to integrating the components of a board onto a single chip. Looks straightforward but productivity levels are too low to make it a reality 4

5 Examples of IP Blocks in Use today RISC: ARM, MIPS, PowerPC, SPARC CISC: 680x0 x86 Interfaces: USB, PCI, UART, Rambus Encryptions: DES, AES Multimedia JPEG coder, MPEG decoder Networking: ATM switch, Ethernet Microcontroller: HC11, etc. DSP: Oak, TI, etc. SoC is forcing companies to develop high-quality IP blocks to stay in business. 5

6 Overview of Design and Technology Trends 1.5GHz Itanium chip (Intel), 410M tx, 374mm 2, 1.1 GHz POWER4 (IBM), 170M tx, if these trends continue, power will become unmanageable 150Mhz Sony Graphics Processor, 7.5M tx (logic) + 280M tx (memory) = 288M tx, 400mm 2 10W@1.8V if trend continues, most designs in the future will have a high percentage of memory

7 Contd Interconnects are the biggest bottleneck We need to look beyond the metal/dielectric based planar architectures Optical, 3D integration and Wireless are the emerging alternatives Single chip Bluetooth transceiver (Alcatel), 400mm 2, required 30 designers over 2.5 years (75 person years) if trend continues, it will be difficult to integrate larger systems on a single chip in a reasonable time

8 The number of transistors in a chip doubles approximately every two years This provide the computational power demanded so far Moore s Law Challenge : Scaling up of frequency causes elevated power dissipation. Source : Intel Original Moore's Law graph, 1965

9 Power Dissipation Scaling up speed/frequency is impossible 10,000 1,000 Nuclear Reactor Sun s Surface Rocket Nozzle Power Density (Watts/cu. m) Hot Plate Pentium processors Source: Intel

10 Multi Core Systems Era Challenge : Keeping up the demand of computational power as clock frequency cannot be scaled. Solution: Increase number of cores parallelism Intel, AMD dual core and quad core CPUs Custom Systems on Chip (SoCs) Number of cores will increase manifold in the next 5 10 years Intel processor New challenge: interconnection of the cores! Single-chip Cloud Computer

11 Noc: The Network on Chip Paradigm Packet switched on chip network Route packets, not wires Bill Dally, Dedicated infrastructure for data transport Decoupling of functionality from communication NoC infrastructure Multiple publications in IEEE ISSCC, 2010 from Intel, IBM, AMD, Renesas Tech. and Sun Microsystems show that multi-core NoC is a reality

12 Multi hop wireline communication Limitations of a Traditional NoC High Latency and energy dissipation source destination -core -NoC interface -NoC switch 80% of chip power will be from on-chip interconnects in the next 5 years ITRS, 2007

13 Novel Interconnect Paradigms for Multicore designs Optical Interconnects Three Dimensional Integration Wireless/RF Interconnects High Bandwidth and Low Energy Dissipation

14 Driven by The network-on-chip paradigm Increased levels of integration Complexity of large SoCs New designs counting 100s of IP blocks Need for platform based design methodologies DSM constraints (power, delay, time tomarket, etc ) 14

15 Some Common Architectures (a) Mesh, (b) Folded-Torus (FT) and (c) Butterfly Fat Tree (BFT) (a) (b) (c) - Functional IP - Switch 15

16 Data Transmission Packet based communication Low memory requirement Packet switching Wormhole routing Packets are broken down into flow control units or flits which are then routed in a pipelined fashion 16

17 Connecting Different IP Blocks Using Tree Architecture 17

18 2D Network on Chips Current SoC contains several different microprocessor components, memory sub systems and I/Os together on single chip. Fast developing SoC Market Development of Multi processor SoC platforms for embedded processors. MP SoC contains combination of numerous IPs performing computation on different clock frequencies which communicate with each other. 18

19 Challenges & Need Integration of all the blocks on the single chip. Non-scalable global wires, as delay increases exponentially with increase in the length. In ultra-deep sub-micron process 80 % of delay is due to interconnects FIFO are used for data synchronization but it becomes costly due to process variability and power dissipation for achieving cross chip signaling in single clock cycle. Thus there is a need for on chip interconnect architecture: frequently used are shared medium arbitrated bus. Hence use of network on chip : parallelism, exhibits modularity, less power consumption. High throughput and low latency, low energy consumption with little area overhead. 19

20 SPIN (Scalable, Programmable Interconnect Network) Guerrier and Greiner proposed SPIN Parent is represented four times at the entry. Picture shows N = 16 nodes, hence 16 IP blocks can be connected. Network growth = (NlogN)/8. Switches are placed at vertices and number of switches = (3N)/4 20

21 CLICHÉ (Chip level Integration of communicating heterogeneous Elements) mxn Mesh of switches interconnecting Ips Every switch is connecting to the neighboring four switches. 21

22 2D Torus Dally and Towles proposed 2D Torus 22

23 Folded Torus Enhanced version of 2D Torus. Can suitably be implemented in the VLSI implementation. The length of each segment remains same. 23

24 OCTAGON Karim et al. Proposed OCTAGON for MP SoC Picture shows 8 nodes and 12 bidirectional links. Communication between pair of nodes will take atleast 2 hops within the basic orthogonal unit. For more large systems orthogonal unit is extended to multidimensional space. 24

25 Butterfly Fat Tree (BFT) Ipsareplacedintheleavesandswitchesareplacedat the vertices. Nodes are denoted by (l,p) where l denotes level and p denotes position. Switch is denoted by S(l,p). Four down links corresponding to child ports and two uplinks for parent port, so total number of switches (at levelj=n/2^(j+1))atj=1isn/4. As we go on going up the switches required will reduce by 2. 25

26 Performance Metrics Architecture should exhibit > high throughput, low latency, energy efficiency, & low area overhead. Message Throughput > Transport Latency > Occurrence of message header from source to occurrence of tail at the destination. Energy > Energy consumed due to the use of interconnects and switches. Area Requirements > The area consumed by the switches and the interconnects. Some interconnects need to be buffered, this also increases the area. 26

27 Evaluation Methodology Developed Simulator for flit level event driven worm hole routing to study characteristics of interconnect architectures. Traffic injection is based on two distributions namely poisson and self similar. Each simulation run for 1000 cycles to allow transient effects to stabilize and then executed for 20,000 cycles. Throughput calculated as number of flits reaching each destination per unit time. Average latency and energy is calculated as shown in previous slide. For area complete VHDL model was synthesized using 0.13 micro meter technology and calculated for area. To determine interconnect energy capacitance was calculated for each topology. 27

28 No. of Channels & throughput Variation throughput under spatially uniform distribution Variation of latency with virtual channels 28

29 Energy Dissipation profile for uniform traffic

30 Chip area based on Topology Wire length between switches in BFT and SPIN architectures To keep inter switch delay within one clock cycle some wires need to be buffered. In CLICHÉ and Folded Torus, all the inter switch wires are of equal length and delay is within one clock cycle. In Octagon, the inter switch wires connecting functional IP blocks in disjoint octagon units needs to be buffered. 30

31 Area Overhead Silicon area overhead for all platforms under consideration across different technology nodes, assuming die size of 20mm x 20mm and each functional IP block consists of 100k gates equivalent of 2 input NAND gates. SPIN and Octagon has higher silicon area overhead due to higher degree of connectivity. The percentage of silicon area overhead for different platforms increases slightly with technology scaling but relative area remains unchanged. 31

32 Wiring complexity Wire lengths between switches in the BFT and SPIN depends upon level of switches. Inter switch wire length is given by: For CLICHÉ and Folder Torus all the wire segments are of same length. For CLICHÉ is given by and folded torus is all the wire lengths are double than CLICHÉ. In Octagon links are differentiated as long links (0 4, and 7 3), medium links(0 7, 3 4, 1 5, 2 6) and short links(0 1, 1 2, 2 3, 4 5, 5 6, and 6 7). 32

33 Wiring Octagon 33

34 Wiring SPIN 34

35 Wiring BFT 35

36 Conclusion NoC based architecture with respect to topology, various topologies such as SPIN, Folded Torus, CLICHÉ, Octagon and BFT are discussed with effect to various factors power consumption, Latency, effect on area, wiring complexity, throughput, bandwidth, etc. Results showing some can achieve high data rate with an expense of high energy while others can provide lower data rate with low energy consumption. Locality also is an important aspect while designing NoC as it can reduce power consumption and increase throughput significantly. These are important aspects of characterizing emerging network on chip architecture. 36

37 SO FAR. NOC Paradigm Traditionally used & Limitation 2D Conventional NOC architecture Wiring complexity Now. Emerging interconnect technology 3D NOCs Photonic NOCs CORONA ARCHITECTURE FIREFLY ARCHITECTURE On- chip RF/wireless interconnect On-chip Antennas used 37

38 Why go 3D?????? Reduction in total power consumption Smaller footprint Shorter interconnects Circuit Security and many more.. Figure 1. Stacked IC [2] 38

39 Three-Dimensional Integrated Circuits Developing very fast Active devices stacked in many layers Reasons Limited floor planning choices 2D IC Desire to integrate disparate technologies (GaAs, SOI, SiGe, BiCMOS) and diparate signals (analog, digital,rf) As small as 20µm Interconnect bottleneck 3D IC 39

40 3D NoC Stacking multiple active layers Manufacturability Mismatch between various layers Yield is an issue Temperature concerns Despite power advantages, reduced footprint increases power density Pavlidis et al., 3-D topologies for Networks-on-Chip, IEEE Transactions on Very Large Scale Integration (TVLSI),

41 Architectures 41

42 Photonic NoC High bandwidth photonic links for high payload transfers Challenges: On going research On chip integration of photonic components A. Shacham et al., Photonic Network-on-Chip for Future Generations of Chip Multi-Processors, IEEE Transactions on Computers,

43 Corona Architecture HP Labs Serpentine Waveguide 3D layer for photonic devices 43 43

44 Firefly Architecture *Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, and Alok Choudhary Firefly: illuminating future network-on-chip with nanophotonics. In Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09). ACM, New York, NY, USA,

45 On-Chip RF/Wireless Interconnects Replace long distance wires Use of waveguides out of package or IC structures like parallel metal wires Chang et al. demonstrated Transmission Line based RF interconnect for on chip communication Not really wireless 45

46 STATE OF ART OF NoC 46

47 Several types Metal Carbon Nanotube (CNT) On Chip Antennas High B/W, frequency light (IR, visible, UV) Small wavelength: small antennas less area CNTs as Optical Antennas Directional radiation characteristics Agrees with radio antenna theory Laser excitation Kempa, et al., "Carbon Nanotubes as Optical Antennae," Advanced Materials, Slepyan, et al., "Theory of optical scattering by achiral carbon nanotubes and their potential as optical nanoantennas," Physical Review B. 47

48 Reliability of CNT Antennas Various uncertainties in CNT growth Length Diameter Electronic properties Semiconducting vs. Metallic Rates of uncertainties tend to be high Much higher than CMOS processes Can lead to poor performance Failure of wireless links 48

49 Design Constraints Limited wireless bandwidth Off chip laser sources Design of metal antennas/transceivers On chip wireless nodes have associated overhead Transceiver Modulator/demodulator antennas How to efficiently distribute the wireless resources? 49

50 Hybrid nature of the WiNoC Augment wireline with wireless Not completely wireless Can use wireless links only for long distance communication >10mm 50 50

51 Architectural Solutions in Nature Natural Complex Networks Brain: Efficient function and memory retention Microbes: Biological Networks social networks Paul Erdös 51

52 Topology Small-World graphs: The Watts-Strogatz Model Often found in nature Scales well: low average distance Few high speed shortcuts: Wireless Local, shorter links: Wireline regular lattice L: Hi C: Hi Small-world L: Lo C: Hi random graph L: Lo C: Lo 52

53 Small World and Scale-Free Network Model Stochastic links Power-tail probability distribution SF: Degree/node SW: Link Length P l or d 9 May

54 Fault-Tolerant Wireless NoC Small-World topology Inherently fault-tolerant Link Insertion Following adjacent probability distribution Few high speed shortcuts: Wireless Interconnects Local, shorter links: Wireline P(i, j) l ij f ij i j l ij f ij 54

55 Experimental Setup Topology Small World wire line and wireless System Size 64 & 256 cores Representative of current industry designs Wireless links 24 links B.G. Lee et al., Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks, IEEE Photonics Technology Letters,

56 This image cannot currently be displayed. Throughput Flits/core/cycle Experimental Results 64 cores 256 cores Minimal effect on performance with wireless link failures A. Ganguly, et al., Complex Network Inspired Fault-tolerant NoC Architectures with Wireless Links, Proc. Of IEEE/ACM International Symposium on Networks-on-Chip (NOCS), May,

57 This image cannot currently be displayed. This image cannot currently be displayed. Comparison of Saturation Throughput Hierarchical Wireless NoC (WiNoC) Same CNT wireless links 64 cores 256 cores Better fault-tolerance than hierarchical NoC 57

58 Packet Energy Dissipation Significantly less than wireline NoCs Packet Energy Dissipation Increase is insignificant with wireless link failures 58

59 This image cannot currently be displayed. This image cannot currently be displayed. Wiring & Area Overheads Wiring requirements for 64 core systems Area overheads for 64 core systems Insignificant real estate overheads 59

60 Conclusion On-chip wireless communication with CNT antenna Efficient NoC architecture can be built But emerging interconnect technologies are defect-prone Inherent resilience of natural complex networks Wireless NoC topologies inspired by the small-world architecture Better power-performance trade-off Fault-Tolerance Security 60

61 REFERENCE PAPERS Networks on Chip in a Three Dimensional Environment: A Performance Evaluation. Scalable Hybrid Wireless Network on Chip Architectures for Multi Core. Systems Co design of 3D Wireless Network on Chip Architectures with Microchannel Based Cooling. Performance Evaluation and Design Trade Offs for Network on Chip Interconnect Architectures. Corona: System Implications of Emerging Nanophotonic Technology. Firefly: IlluminatingFuture Network on Chip with Nanophotonics. It s a Small World After All : NoC Performance Optimization Via Long Range Link Insertion. 61

62 62