Chapter 8. Coping with Physical Failures, Soft Errors, and Reliability Issues. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P.

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1 Chapter 8 Coping with Physical Failures, Soft Errors, and Reliability Issues System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 1 1

2 What is this chapter about? Gives an Overview of and Promising Solutions to the Causes of Manufacturing Defects and Soft Errors Focus on Signal Integrity Defect-Based Tests Process Sensors and Adaptive Design Soft Errors BISER Circuit-Level Approaches Defect and Error Tolerance System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 2 2

3 Coping with Physical Failures, Soft Errors, and Reliability Issues Introduction Signal Integrity Manufacture Defects, Process Variations, and Reliability Soft Errors Defect and Error Tolerance Concluding Remarks System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 3 3

4 Introduction Defects Random defects Caused by manufacturing imperfections and occur in random places Systematic defects Caused by process or manufacturing variations Defect level (DL) is a function of process yield (Y) and fault coverage (FC) DL= 1 Y ( 1 FC) System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 4 4

5 Concept of Signal Integrity Signal integrity is the ability of a signal to generate correct responses in a circuit. A signal with good integrity stays within safe margins for its voltage amplitude and transition time. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 5 5

6 Basic Concept of Integrity Loss Integrity Loss: any portion of signal that exceeds amplitude-safe and time-safe margin. ( IL ( IntegrityLoss) = V f ( t) dt) i where Vi is one of the acceptable amplitude levels and b i, e i is a time frame during which integrity loss occurs. ei bi i [ ] System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 6 6

7 Sources of Integrity Loss Interconnects Power Supply Noise Process Variations System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 7 7

8 Integrity Loss Sensors/Monitors (1) Current Sensor Current sensors are often used to detect the completion of asynchronous circuits. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 8 8

9 Integrity Loss Sensors/Monitors (2) Power Supply Noise Sensor V x The voltage depends on the power/ground bounces: the higher the PSN is, the longer the propagation and the higher the voltage V x will be. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 9 9

10 Integrity Loss Sensors/Monitors (3) Noise Detector (ND) Sensor ND sensor is designed to detect integrity loss due to voltage violations. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

11 Integrity Loss Sensors/Monitors (4) Integrity Loss Sensor (ILS) The integrity loss sensor is a delay violation sensor. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

12 Integrity Loss Sensors/Monitors (5) Jitter Monitor Jitter is often defined as the time deviation of a signal from its ideal location in time. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

13 Integrity Loss Sensors/Monitors (6) A ring oscillator can work as a Process Variation Sensor The variation of delay caused by PV-faults in any of the inverters in the loop results in deviation in the frequency of the oscillator, which can be detected. 1 2 f µεw ( )( ) 2 RO VGS Vt (1 N V C 2T + inv dd Load ox K L eff V DS ) RO = ( N invtinv ), where N inv is an odd number of inverters and is the delay of one inverter. f 1 T inv System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

14 Readout Architectures (1) BIST-Based Architecture BIST Architecture Readout Circuitry When a noise or delay violation occurs (flag=1), the contents of all scan cells are then scanned out through Sout for further reliability and diagnosis analysis. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

15 Readout Architectures (2) Scan-Based Architecture At the driving side of an interconnect, pattern generation BSC(PGBSC) is used to generate test patterns. At the receiving side of the interconnect, an observation BSC(OBSC) is used to detect integrity loss. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

16 Readout Architectures (3) Basic Concept of PV-Test Architecture On-chip ROs with counters, embedded in a test chip are used to detect process variation by measuring the RO s frequency shifts. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

17 Manufacture Defects, Process Variations, and Reliability 100% single stuck-at fault coverage cannot guarantee perfect product quality, because there are remaining defects that are: Timing-dependent Sequence-dependent Attributed to timing-dependent, non-single-stuck-at faults System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

18 Structural Tests A Defect-Based Test Architecture RTL Library RC Extraction Layout ATPG Synthesis Modeling Timing Analysis Defect-Based Fault Enumeration Structural Tests Gate-level Netlist Path Extractor Physical Faults Defect-Based Fault Simulator Critical Path List Fault Mapping Functional Tests Fault List Logical Fault List Defect-Based ATPG Defect-Based Tests System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

19 Defect-Based Tests Small Delay Defect Tests Bridge Defect Tests N-Detect Tests I ddq MinV DD Tests VLV Tests Tests System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

20 Reliability Stress Concept of Infant Mortality Methods to screen infant mortality Method I - Burn-in ttf = c E A e kt Where ttf is time to failure, C is a constant, is the activation energy (ev), k is the boltzman s constant, and T is an absolute temperature. E A Method II - Elevated Voltage Stress System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

21 Redundancy and Memory Repair Redundancy: Spare rows, columns, or blocks Repair schemes: Pellston Technology [Wuu 2005]: If repeated error are detected, disable cache line (set not to use bit) Perform memory BIST at new operating conditions; exclude failing cells and resize cache (cache size can vary larger or smaller, depending on whether new conditions are more favourable or worse) System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

22 Process Sensors and Adaptive design Compare traditional test structures put on the scribe lines and embed additional process sensors on-chip. On-Chip Process Sensors: Process Variation Sensor Thermal Sensor Dynamic Voltage Scaling System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

23 Process variation Sensor Ring oscillators: Many factors can affect the frequency of the ring oscillator such as process variation, temperature and voltage. Analog Process Variation Sensor: The analog circuit will be sensitive to different process parameters. Neither can report the process variation at the specific spot on the die and unlikely to extract and analyze the data in real time. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

24 Thermal Sensor On-chip thermal sensors are the last defence to prevent system crash or permanent damage to the chip. Thermal sensor example: Vref_diode Vb _ + Vref_diode V b I1 I2 I3 R1 vf Vref-1 R2 Vc Vref-n MUX Vref_TTLEVEL _ + Tx Detect N Vref_diode Figure 8.14:Thermal sensor example System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

25 Dynamic Voltage Scaling DVS Figure 8.15: Dynamic voltage scaling scheme System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

26 Dynamic Voltage Scaling (cont d) Use sleep transistors and dynamic biasing to save power Use the adaptive test method for smart binning System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

27 Soft Errors Introduction Sources of Soft Errors and SER Trends Coping with Soft Errors System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

28 Introduction Soft errors Soft errors are transient single-event upsets (SEUs) caused by various type of radiation Cosmic radiation is the major source of soft errors,especially in memories. Terrestrial radiation is another source of soft errors. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

29 Sources of Soft Errors and SER Trends If a glitch is induced at the junction (red label) in a memory element, its state can be reversed. Figure 8.16: Induced soft error on a SRAM cell System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

30 Sources of Soft Errors and SER Trends Logic circuits are less susceptible to these glitches than memories for the following reasons. The glitch must be of sufficient strength to propagate from the location of the strike. The glitch needs to have a functionally sensitized path to be latched. The glitch must arrive at a latch during its latching window. Figure 8.18: Masking factors of soft errors in combinational logic System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

31 Coping with Soft Errors As chips are susceptible to soft errors, many soft error protection schemes targeting chip designs have been proposed. Fault Tolerance Error-resilient microarchitectures soft errroe mitigation System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

32 Fault Tolerance Removing the source of soft errors to improve the reliability of a chip. Three fundamental fault tolerance schemes: Hardware (spatial) redundancy assumption that defects and radiation particles will only hit on a specific device and not another device Time (temporal) redundancy assumption that the radiation strike will not happen on the same circuitry against at a slightly later time Information redundancy using error-detecting code or error-correcting code to represent information contents System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

33 Fault Tolerance Common fault tolerance schemes used in high reliability system Duplicate and compare used in mainframes and high-end servers Triple modular redundancy used for systems that cannot fail Redundant multithreading using error-detecting code or error-correcting code to represent information contents System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

34 Error-Resilient Microarchitectures Two representative error-resilient processor microarchitectures DIVA Razor DIVA Dynamic Implementation Verification Architecture (DIVA) DIVA Checker a smaller and simpler shadow processor contain a functional checker stage (CHK), commit stage (CT), and a watchdog timer(wt) DIVA Core The main processor that fetches, decodes, and executes instructions, holding their speculative results in the reorder buffer (ROB) System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

35 Error-Resilient Microarchitectures Razor Dynamic voltage scaling (DVS) is one of the most effective and widely used methods for power-aware computing. The key idea of Razor is to tune the supply voltage by monitoring the error during circuit of operation; this is accomplished with a shadow unit, but this shadow unit has been pushed all the way down into a Razor flipflop. This Razor flip-flop is shown in Figure 8.21a. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

36 Error-Resilient Microarchitectures clk Logic Stage L1 D1 0 1 Main Flip-Flop Q1 Error_L Logic Stage L2 RAZOR FF Shadow Latch comparator Error clk_del Figure 8.21(a) Schematic of the Razor flip-flop System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

37 Error-Resilient Microarchitectures Razor A reduced overhead Razor flip-flop with the metastability detection circuit is illustrated in Figure 8.21b. D clk clk_b clk_del Error_L clk_del_b 0 1 clk_b clk Q Metastability Detector Inv_n Inv_p Error_L Shadow Latch Figure 8.21(b) Reduced overhead Razor flip-flop with metastability detection circuit System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

38 Soft Error Mitigation Soft error mitigation techniques are to provide partial immunity of a design to potential soft errors while significantly minimizing the required cost over fault tolerance schems. There are three soft error mitigation methods: (1) Built-In Soft-Error Resilience (BISER) BISER proposed in [Mitra 2005] can be used to allow scan design to protect a device from soft errors during normal operation. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

39 Soft Error Mitigation Figure 8.22 shows the BISER scan cell design that reduces the impact of soft errors affecting storage elements by more than 20 times. SCB SI SCA CAPTURE UPDATE D CLK TEST.... LA 1D C1 Q 2D C2 PH 2 C1 Q 1D Scan portion LB C1 1D Q PH 1 1D C1 Q 2D C2 System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 39 O2 O1 System flip-flop... C-element Figure 8.22: Built-in soft-error resilience (BISER) scan cell... Keeper SO Q 39

40 Soft Error Mitigation Circuit-level approaches (2) Gate resizing for soft error mitigation [Zhou 2006] is based on physical-level design modifications. Figure 8.23 illustrates the effect of gate resizing on the amplitude and width of a 0-to-1 transient at the output of a gate. Figure 8.23: Effect of gate resizing on the amplitude/width of SETs [Zhou 2006] System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

41 Soft Error Mitigation Circuit-level approaches (3) Netlist transformation for soft error mitigation [Almukhaizim 2006] is based on logic-level design modifications.. Figure 8.24: Example of rewiring to reduce the soft error failure rate System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

42 Defect and Error Tolerance Defect Tolerance Insert redundancy circuitry in a circuit under test The circuit can continue correct operation in the presence of defects. Error Tolerance Allow the circuit to continue acceptable operation in the presence of errors System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

43 Random Spot defects Assume a design consists N submodules. Each module has n unique positions where a defect would cause it to fail its tests. D defects uniformly distributed over the submodule. Number of defects in any submodule is independent of the number of defects in other submodules. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

44 Defect Probability Probability that an arbitrary position on a submodule is associated with a defect is: p = D / (nn) Probability of having d defects in a given submodule is: where P(d) = C(n,d)p d (1-p)n-d C(n,d) = n! / (d!(n-d)!) System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

45 Poisson Distribution P(d) is binomially distributed, the average number of defects in an arbitrary submodule is: E(d) = λ = np = D / N For large n and small p, the binomial distribution can be approximated by Poisson distribution P ( ) ( ) λ d d = e λ d! System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

46 Example Assume a submodule is equally likely to be defect-free or defective: Thus, λ = λ ( d = ) = ( 0 0 e λ /!) P 0 Effective yield can increase significantly if the system can accept some defective submodules. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

47 Probability of Having Exact d Defects at a Submodule as a Function of Yield (Y) for Various Values of Failure Rate λ d λ = Y = λ = Y = λ = Y = λ = λ = λ = Y = Y = Y = λ = Y = λ = Y = λ = Y = System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

48 Defect Tolerance M M M Switch Used to be called redundancy repair A typical defect-tolerant design is shown on the left Two spares (identical modules) A switch used to select one module System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

49 Error Tolerance The main Objective of error tolerance is to increase the effective yield of a process by identifying defective but acceptable chips This lies in the development of An accurate method to estimate error rate An effective method to predict yield System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

50 Fault-Oriented Test Methodology Enhance effective yield based on error-rate analysis Estimate error rate of each modeled fault A set of acceptable faults is identified based on their error rates IC Fabrication Fault Ranking Testing Acceptable Chips Unacceptable Chips System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

51 Error-Oriented Test Methodology IC Fabrication Testing Good Chips Focus on errors produced by defective chips rather than on modeled faults estimate the error rates of these chips determine the acceptability of the faulty chips by estimated results Bad Chips Error-Rate Estimation Estimated Error Rate Classification Based on Estimated Error Rate Acceptable Chip Set 1 Acceptable Chip Set 2 Unacceptable Chips System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P

52 Concluding Remarks Circuit Errors can be caused by manufacturing defects and soft errors. Design for Manufacturability (DFM) Fault avoidance schemes to cope with physical failures caused by signal integrity, defects, and process variations during manufacturing. Design for Reliability (DFR) Embedded error resilience and defect tolerance circuitry on-chip to tolerate soft errors and manufacturing defects. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P