Robust System Design with MPSoCs Unique Opportunities

Transcription

1 Robust System Design with MPSoCs Unique Opportunities Subhasish Mitra Robust Systems Group Departments of Electrical Eng. & Computer Sc. Stanford University Acknowledgment: Stanford Robust Systems Group Students & Collaborators Robust Systems in Scaled CMOS Failure rate Future: Burn-in difficult Soft errors, erratic bits, process variation Future: NBTI aging, etc. Past Infant mortality Normal lifetime Wearout Time Radiation, Erratic bits Aging, Infant mortality, Process variation 2 Burn-in & Test Socket Workshop Inputs Design errors, Software failures Robust System Malicious attacks, Human errors Acceptable outputs Performance Power Availability, Security 2 Page 3-2-

2 Globally Optimized Robust System Design + Traditional mainframes Globally optimized robust system App. Failure Prediction Recognition Mining Synthesis (RMS) Cost Handheld, mobile devices, ASICs Our Goal Runtime Arch. Failure-Awareness / Resilience + Circuit BISER On-line Self Test 3 Multi-Core Robust System Opportunities Multi-core massive redundancy (e.g., TMR) Reconfigurable reliability turn protection on / off Power expensive, LOCAL gates inexpensive On-line self test unique multi-core opportunities Required for Circuit Failure Prediction Essential for intelligent sparing Asymmetric core-level reliability Globally optimized performance vs. resilience 4 Page

3 Outline Introduction Built-In Soft Error Resilience (BISER) Circuit failure prediction Error Resilient System Architecture (ERSA) Conclusion 5 Key Takeaway Logic soft errors extremely important Classical error detection + recovery Expensive & complex Built-In Soft Error Resilience (BISER) Best of all Efficient & practical Latch erratic errors also corrected CORRECT Errors DON T Detect!! 6 Page

4 Who Cares About Soft Errors? Transient errors: α-particles, neutrons 2K processor server farm Comb. logic major error every 2 days Silent data corruption (SDC) $ 2K $ 3,66 deposit Latch Un protected memory $ 2K $ 52,768 deposit Detected but uncorrected (DUE) Soft error rate contributions Downtime cost: $K - $M / hour 7 BISER for Latch Errors A B C-element (A, B) Previous value Previous value IN Comb. logic OUT Latch D C Weak keeper OUT D Clock C C-element Redundant Latch (Scan Test & Debug reuse) 8 Page

5 BISER Latch Error Correction Principle System Latch D C C- element Weak Keeper D C Redundant Latch (Test & Debug Reuse) Error Blocked System Output Key Observation: Latches vulnerable only in Opaque state (CLK = ) 9 BISER Scan Flip-flop + Reconfigurable Protection Design Reuse Enabled Scan Clock B = Scan Data Scan Clock A Capture = + & Scan / Checking Flip-flop D C 2D C2 D C Scan Output Keeper Update System Data System Clock D C D C 2D C2 System Flip- flop System Output C-element Page

6 Architecture-Aware BISER Insertion cumulative error coverage % 8% 6% 4% 2% X chip-level protection 2X 2.5% power penalty % % 2% 4% 6% 8% % cumulative latch coverage Alpha 2264 Fault Injection 9% chip-level power penalty Ack: Prof. S.J. Patel, UIUC for fault injector Optimized BISER insertion [Seshia, Li & Mitra, DATE 7] Maximize protection, minimize power penalty BISER: Latch + Combinational Logic Errors IN Comb. logic OUT Delay (~ 2ps) OUT2 Incremental power cost over latch error correction: minimal τ Latch D C D C Latch Clock C C- element Weak keeper OUT Required for latch error correction 2 Page

7 BISER vs. Traditional Techniques BISER DICE Duplicate Multi-thread Latch SER > 25X 25X Detected Detected Comb. logic SER 2-64X Ineffective Detected Detected Chip energy 6 9% > 5% 4-% ~ 4 % (?) Speed penalty Latch: % % Minimal ~ 5% Comb: 5% Die size increase ~ None ~ None Yes Unclear Downtime None None Yes Yes Recovery None None Complex Complex Configurability Yes No Yes Yes Applicability Unlimited Unlimited Unlimited Processor 3 Outline Introduction Built-In Soft Error Resilience (BISER) Circuit failure prediction Error Resilient System Architecture (ERSA) Conclusion 4 Page

8 Key Takeaway Failure rate Solution: Circuit Failure Prediction Future: Burn-in difficult Infant mortality Superior to error detection Normal lifetime Practical test chip prototype Future: NBTI aging Wearout Past Time Effective up to 4x aging guardband reduction MPSoC opportunities: On-line self-test & adaptation 5 Circuit Failure Prediction Predict failures BEFORE errors appear Collect data over time: on-chip sensors Applicability: Transistor aging, infant mortality Failure Prediction Before errors appear Error Detection After errors appear + No corrupt data & states Corrupt data & states + Self-diagnosis possible Limited diagnosis A little fire is quickly trodden out; Which, being suffer'd, rivers cannot quench. William Shakespeare King Henry the Sixth, Part III 6 Page

9 Failure Prediction for Transistor Aging Small speed guardband Tg (e.g., for 5 days) Predict aging: Special Sensors + On-line Self-Test Guaranteed correct outputs No End of 5 days Analyze prediction results Enough aging? Yes Self-correct / Self-adapt Special flip-flops with Aging Resistant Built-In Aging Sensor OpenRISC core (65nm technology) Ring osc. / Temp. sensors inadequate Speed penalty Chip-level power penalty Die size increase Design flow impact Adjust V t (Forward body bias?) Adjust V dd (Runaway?) Adjust speed? Core sparing < % <.4% Not expected Minimal 7 Aging Sensor Principle Clock Comb. logic Clock Delayed Clock OUT Clock D Tg Flip-Flop with Built-in Aging Sensor Delay Element Stability Checker Sticky Latch Stability Output OUT (Today) OUT (5 days later) clock D Flip-Flop Output Detect transitions during Tg No additional hold time constraint 8 Page

10 Circuit Failure Prediction Benefits Reduced guardband: close to best-case performance Clock Clock 7 yr. worst-case guardband Reduced initial guardband (Tg) Combinational logic output stable at time Clock speed GHz 3 GHz % Guardband Reduction 7-yr worst guardband (% clock period) Initial guardband (Tg) day None days None 2 48 CORRECT OUTPUTS GUARANTEED 9 Built-In Aging Sensor: Test Chip Prototype Clock Stability checker Test Chip Waveforms (Measured) Signal transition outside Tg, Stability checker output = Signal transition inside Tg, Stability checker output = voltage (au) voltage (au) time (au) time (au) 2 Page 3-2-

11 Outline Introduction Built-In Soft Error Resilience (BISER) Circuit failure prediction Error Resilient System Architecture (ERSA) Conclusion 2 Emerging Probabilistic Killer Applications Recognition, Mining, Synthesis (RMS) Cognitive, computational genomics, vision, Large data sets Highly parallel Core algorithms Probabilistic belief propagation, K-means clustering, Bayesian networks Our society is creating massive amounts of complex data There is a critical need to recognize, mine and synthesize all of this digital data. Pat Gelsinger Intel, Feb Page 3-2-

12 RMS Error Resilience Opportunities Algorithmic resilience probabilistic & iterative Low order bit-errors minimal effects Known for decades Cognitive resilience Acceptable results OK BAD NEWS RMS + unreliable H/W Doesn t work Control errors, High-order bit-errors 23 ERSA Hardware Prototype Results No ERSA: RMS + unreliable H/W Doesn t work Avg. GP + SP + BP errors to crash: FP errors: highly inaccurate results RMS + ERSA at 6 FITs (3, errors / sec.): No crashes, highly accurate results Useful throughput maintained Linear speedup 24 Page

13 ERSA: Asymmetric Reliability is Key Relaxed Reliability Cores (RRCs) Sequestered from OS I$ () Fetch & Decode Issue Logic FPU ALU D$ () Ld/St MMU Reliable Interconnect Strictly Reliable Core (SRC) OS visible 25 ERSA: Error Resilient System Architecture Relaxed Reliability Cores (RRCs) Sequestered from OS SRC specification Highly reliable (expensive) I$ () Fetch & Decode Issue Logic Execute OS + system calls Execute main thread FPU ALU D$ () Ld/St Assign worker threads to RRCs MMU RRC memory bounds spec. RRC Timeout Handle RRC exceptions Reliable Interconnect Strictly Reliable Core (SRC) OS visible 26 Page

14 ERSA: Error Resilient System Architecture Relaxed Reliability Cores (RRCs) Sequestered from OS I$ () Fetch & Decode Issue Logic FPU ALU D$ () Ld/St MMU RRC specification Cheap & unreliable Configurable reliability: general apps Execute worker threads Reliable Reliable Interconnect Memory bounds check Cache Context save & restore Strictly Reliable Core (SRC) Suspend & resume OS visible 27 RMS on ERSA Main Thread (SRC) Setup Work Assignment (Work, Memory bounds, Timeout) Worker thread + bounds check (RRC) Worker thread + bounds check (RRC) Barrier Iterations Timeout check Handle Calculate Calculate exceptions Data Reduction Done? Ignore diverging iteration Error handling on SRC Terminate erroneous thread Continue to next iteration 28 Page

15 ERSA Prototype Application Program Many-Core Runtime Error Injection into Hardware (Virtualization technology used) MISP Emulation Firmware SRC RRC RRC RRC RRC RRC RRC RRC 4-socket, 2.6 GHz, Dual-core IA-32 processors 2 GB main memory Multiple Instruction Stream Processor (MISP) infrastructure [Hankins ISCA 6] 29 ERSA Work Throughput Results Valid Codes Per Sec. (Measured) Correct Bayesian Graph Edge Manipulations Per Sec. (Measured) LDPC Decoder (Error-free: 6 / s.) Error rate (FITs) Bayesian Network (Error-free: 4 / s.) Correct Clustering 3 Runs Per 2 Sec. (Measured) K-Means (Error-free: 32 / s.) Error Rate (FITs) Conservative correctness criteria! Error rate (FITs) 3 Page

16 ERSA Results: High-order Bit Errors LDPC Decoder K-means Clustering % % Increase No ERSA Correctly 8 In Mean ERSA ( 6 FITs) Decoded 6 Point- ( Blocks 6 FITs) 4 Cluster No ERSA Centroid 2 ( 6 FITs) ERSA Distance (. 6 FITs) Error Bit Bayesian Network Error Bit % Degradation No ERSA 3 FITs: 98% accuracy, In Score ( 6 FITs).5% more iterations Of Learned Network 6 FITs: 96% accuracy, ERSA % more iterations. ( 6 FITs) Error Bit 3 ERSA Speedup Results Speedup over Optimized Single Core (Measured) 6 4 LDPC Decoder No ERSA (No Errors Allowed) 2 ERSA ( 3 FITs) No. of Cores Speedup over Optimized Single Core (Measured) 3 2 Speedup over Optimized Single Core (Measured) Bayesian Network No ERSA (No Errors Allowed) ERSA ( 3 FITs) K-Means Clustering No ERSA (No Errors Allowed) ERSA ( 3 FITs) No. of Cores 6 FITs measured results similar No. of Cores 32 Page

17 Outline Introduction Built-In Soft Error Resilience (BISER) Circuit failure prediction Error Resilient System Architecture (ERSA) Conclusion 33 Conclusion Robust system design Global Optimization Unique opportunities: New thinking required BISER unique soft error properties Cost-effective correction Circuit failure prediction unique failure modes Effective prediction possible ERSA unique future killer apps Resilient to extremely high error rates 34 Page

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