A Novel Approach to a High Speed, Large Memory Spacecraft Data Storage Unit

Transcription

1 A Novel Approach to a High Speed, Large Memory Spacecraft Data Storage Unit L. Piché, B. Gordon - Routes AstroEngineering L. Laba, K. Magnussen - MDA 1

2 Presentation Outline Description of Cascade System Outline of data storage requirements for Cascade Overview memory technologies available Outline Routes proposed Data Storage Unit solution Overview of the DSU architecture Results of technology risk reduction testing Conclusions Acknowledgements 2

3 Introduction to Cascade System conceived by MacDonald Dettwiler & Assoc. Ltd. (MDA) of Richmond, BC, Canada Commercial data service, to transfer large quantities of data anywhere in the world Analogous to Fed-Ex in the Sky Delivery of data from remote locations on land or ocean to head office End users are expected to be from the exploration and defense sectors 3

4 Key Characteristics of Cascade System Multiple Low-Earth-Orbiting Satellites Ka-band RF links Multiple data channels, crosspolarized, 350 MHz data rates Beacon-based rain fade mgmt Multiple Ground Terminals 1.2 to 2.4 m, high bandwidth Data storage, data management, & full user interface Service Control Centre Scheduling & tasking activities Cascade Program Plan Technology Demonstration satellite (CX) for validation & risk reduction Followed by Production satellites (CP) 4

5 Demod 1 A n t e n n a RHC LHC LHC RHC LNA LNA Payload Control Computer HPA HPA D/C D/C U/C U/C Demod 2 Demod 3 Demod 4 Mod 4 Mod 3 Mod 2 Mod 1 Data Storage Key: LNA Low Noise Amplifier HPA High Power Amplifier D/C Down Converter U/C Up Converter Demod Demodulator Mod Modulator RHC Right Hand Circular (Polarization) LHC Left Hand Circular (Polarization) The payload channels will be operated in a half-duplex mode. That is, a channel will be either transmitting or it will be receiving, but not both simultaneously. 5

6 Cascade On-Board Data Storage Requirements Requirement Tech Demo-CX Production-CP Comments Number of Channels 2+1+1= = 6 Active + b/u + test Channel Speed 350 Mbps 350 Mbps LVDS (I+Q+Clock) EOL 1.2 T-bit 6.2 T-bit Random Access Power (nom/max) 27W / 29 W 49W / 54W Power Conservation No loss of data No loss of data Volume 33x33x15 cm 33x33x15 cm Same enclosure Mass 18.7 kg 26 kg Radiation Dose (TID) 3 krad 15 krad 6mm eq aluminum Availability /500 datasets Mission Life 2 years 5 years 6

7 Comparison of Available Memory Technologies Candidate storage technologies: Solid State Recorders based on Dynamic Random Access Memory (DRAM) technology Redundant Arrays of Inexpensive Drives (RAIDs) based on commercial hard disk drives, subsequently adapted & qualified for space Technology limitations: DRAM Solid State Recorders: Are not well suited to T-bit memory volumes due to low memory densities (unit gets large & heavy) Requires power to retain data in memory RAIDs: Are more complex than Solid State Recorders Require a hermetically sealed, pressurized environment Must configure to null the torques caused by the drives spinning up Have moving parts 7

8 Flash Memory An Alternative? This technology is being embraced in the commercial world for non-volatile storage of large volumes of data Advantages of Flash: Very high memory density available (1GByte & 2GByte per chip) Very fast read/write times Reasonable power consumption Retains data when powered off No moving parts No pressure vessels No magnetic fields 8

9 Routes Value Proposal for Mass Memory High Speed, T-Bit sized Data Storage Unit (DSU) based on Flash technology Modular, scalable memory solutions up to 20T-bit Utilizing mainly Commercial-Off-The-Shelf (COTS) technology, subsequently adapted & qualified by Routes for use in space Fault tolerant & scalable architecture, allowing customers to specify the degree of redundancy required to meet mission reliability requirements Positioned to take advantage of projections that Flash memory costs will improve year over year 9

10 Routes Data Storage Unit (DSU) - Architecture (1) PC104 Bus Control Interface Assembly Spacecraft C&DH Interface Dual-redundant PC104 Bus PC104 Bus Control Processor Assembly Control Electronics Module DSU Test Interface +5 VDC (CEM) +3.3 VDC (CEM) PC104 Bus +3.3 VDC (STA Bypass) +3.3 VDC (STA#1-6) Power Supply Module Power Control Assembly Input Diodes Current-Limit FETs Prime +5 V DC/DC Prime +3.3 V DC/DC Thermal Wall Assembly Prime EMC Filter +5 VDC (DSA#1-6) Second +5 V DC/DC Second +3.3 V DC/DC Secnd EMC Filter 10

11 Routes Data Storage Unit (DSU) - Architecture (2) Storage Transfer Module I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk I, Q & Clk Storage Transfer Assembly Storage Transfer Assembly Storage Transfer Assembly Storage Transfer Assembly Storage Transfer Assembly Storage Transfer Assembly PC104 Bus PC104 Bus PC104 Bus PC104 Bus PC104 Bus PC104 Bus Mass Memory Module PC104 Bus to CEM Data Storage Assembly Memory 155GB Data Storage Assembly Memory 155GB Data Storage Assembly Memory 155GB Data Storage Assembly Memory 155GB Data Storage Assembly Memory 155GB Data Storage Assembly Memory 155GB 11

12 Routes DSU (CASCADE Configuration) 15 cm 35 cm 35 cm 12

13 Summary of DSU Implementation (1) Power Supply Assembly Based on Commercial-Off-The-Shelf (COTS) DC-DC converters Routes designed pcb to implement power management features Control Interface Assembly Mil-Std-1553 is available COTS in PC104 form factor RS422 or CANBus will require adapting previously flown designs to a PC104 form factor Control Processor Assembly Two COTS solutions available in PC104 form factor Routes has subjected both COTS assemblies to radiation testing 13

14 Summary of DSU Implementation (2) Data Storage & Transfer Assembly New Routes design To be implemented in FPGA, using Xilinx Vertex II Pro High speed, high density & rad-tolerant to 100krad Mass Memory Modules Objective is to secure a COTS solution (2 manufacturers) The most likely configuration is a memory controller with banks of flash memory modules (allowing scalability) The baseline storage size: Cascade CX: 70 Gbyte memory modules Cascade CP: 155 Gbyte memory modules Fibre Channel interface for data I/O Routes has conducted radiation tests 14

15 Routes Data Storage Unit (DSU) for Cascade Requirement Tech Demo-CX Production-CP Routes DSU Number of Channels = = (7 max) Channel Speed 350 Mbps 350 Mbps EOL 1.2 T-bit 6.2 T-bit Power (nom/max) 27W / 29W 49W / 54W Power Conservation No loss of data No loss of data Volume 33x33x15 cm 33x33x15 cm Mass 18.7 kg 26 kg Radiation Dose (TID) 3 krad 15 krad Availability >350 Mbps 3x70GB=1.7Tbit 6x155GB=6.2Tbit 20Tbit max 36.6W / 55W-CP Power mgmt dsn 35x35x15cm 25.7 kg (6.2Tbit) 27.5 krad (4mm).9987 Mission Life 2 years 5 years 5 years 15

16 Technology Risk Mitigation Activities Single Event Effects (SEE) & Total Ionizing Dose (TID) tests Flash Memory Modules (2 manufacturers) COTS Command Processors (2 manufacturers) COTS Command Interface Assembly (RS422 version) Accelerated thermal cycling tests Flash Memory Modules COTS Command Processors Ceramic packaged FPGA with Ball-Grid-Array attachments 16

17 Flash Memory SEE Radiation Susceptibility Tests SEE tests conducted at TRIUMF, Vancouver Canada Tested 2 different memory module assemblies Subjected articles to 57.7 MeV proton flux Performed Write/Read cycles & kept tally of data errors during test Monitored voltage, current, & temperature during test Results: No latchup conditions were observed Some upsets occurred resulting in resets & subsequent data loss (this was expected), software resets corrected most occurances The Flash memory modules were fairly robust, SEEs occurred mainly in the memory controller 17

18 Flash Memory TID Radiation Susceptibility Tests TID tests at TRIUMF Two units tested. Proton beam. No shielding was used Both units failed after accumulation of between 5 & 10 krad dose There were no failures in Flash memory In both cases, failures were due to susceptibility of FPGA chips used to address the Flash memory banks TID tests at Defense Research and Development Canada facility, Ottawa Canada (DRDC) Source used was Cobalt 60. No shielding was used Only one unit was available for test Device failed at between 27.5 & 30 krad 18

19 Our Conclusions SEE & TID SEE Susceptibility Both memory modules behaved similarly The Flash memory banks were fairly robust The memory controller electronics showed the highest susceptibility Soft failures, which could be cleared via resets Unit availability was calculated as for the worst case article, exceeding Cascade requirement of.9980 Total Ionizing Dose Susceptibility The memory module was able to withstand greater than 27.5 krad for a Cobalt 60 source (1.7 times the 15 krad dose predicted over a 5 year Cascade mission) One soft chip. We believe we have a solution to resolve the susceptibility issue in the FPGA memory address devices 19

20 Other Risk Mitigation Tests & Results Radiation Testing of Command Processors One COTS assembly tested at TRIUMF for SEE & TID (protons) SEE: Observed occasional software resets, no latchups TID : Device failed between 20 & 22.5 krad Two COTS assemblies tested at DRDC in Ottawa TID : Both units failed between 40 & 42.5 krad (gamma) Radiation testing of COTS RS422 at TRIUMF SEE: No issues TID : Device failed at 5 krad (protons) 20

21 Other Risk Mitigation Tests & Results Accelerated life tests Routes is currently performing rapid temperature cycling tests Memory modules, command processors, and ceramic BGA devices on Storage Transfer Assembly will be tested Tests are being conducted in air 600+ cycles planned, units will be periodically power cycled 21

22 Cascade DSU Development Plan Phase 0/A: Technology Feasibility & Risk Mitigation Tested radiation susceptibility of drives Performed critical timing analyses & reliability trade studies Developed architecture and redundancy configuration Phase B: Preliminary Design Complete technology risk mitigation tests Finalize baseline suppliers PDR in mid-sept 2004 Phase C: Detailed Design (for CX Mission) CDR in Mar 2005 Phase D: Cascade CX Flight Model DSU Flight Model delivery to Payload Integration Dec

23 Conclusion Routes is developing a Flash-based, high speed, large capacity mass memory solution for T-bit applications Our COTS-based modular architecture allows scalability for: Number of channels Number & size of individual memory modules Redundancy options for different reliability requirements Radiation test results give us confidence that Flash memory is sufficiently robust to both SEE & TID We believe that our solution offers high performance and flexibility for future high-data-volume smallsats 23

24 Acknowledgements Routes AstroEngineering wishes to acknowledge the support of: MacDonald Dettwiler & Associates Ltd. and the Canadian Space Agency Thank you for your attention 24