SpaceWire, a Backbone for Humanoid Robotic Systems. Mathias Nickl, Stefan Jörg, Thomas Bahls, Alexander Nothhelfer, Stefan Strasser

Transcription

1 SpaceWire, a Backbone for Humanoid Robotic Systems Mathias Nickl, Stefan Jörg, Thomas Bahls, Alexander Nothhelfer, Stefan Strasser Robotic and Mechatronics Center, German Aerospace Center (DLR) International SpaceWire Conference >

2 Robotics and Mechatronics Center: Competences Physics Usability engineering Industrial design Psychology Medical engineering Folie 2

3 Robotics and Mechatronics Center: Competences to build highly-integrated robots Physics Folie 3

4 Robotics and Mechatronics Center: Systems with SpaceWire DLR Hand II 2001 (IEEE1355) DLR Krabbler 2006 Medical Robots and Tools: Kinemedic 2005, Miro 2008, MICA 2009 DLR Hand Arm System 2010 Folie 4

5 DLR Hand Arm System - A novel humanoid design 26 Degrees of Freedom Variable Stiffness Actuation 52 s, 430 Sensors Folie 6

6 DLR Hand Arm System Hand + Wrist (19 +2 DOF) SpaceWire 1Gbit 4x 19x 19x 42 Hall Sensors SpaceWire 1Gbit 3 Potentiometers 19x 19x 4x 42 MiniServos Folie 7

7 DLR Hand Arm System The Arm (5 DOF) 5x3 Potentiometers 4x Ilm50 Shoulder 2 Shoulder 1 UpperArm Forearm Elbow 2x 6x MiniServo Shoulder-Elbow FSJ Mechanism [Wolf et al., ICRA 2011] Forearm Mechanism [Friedl et al., IROS 2011] Folie 8

8 DLR Hand Arm System Communication Shoulder 2 Shoulder 1 UpperArm Forearm Elbow BiSS 10 MBit SpaceWire 1Gbit Folie 9

9 DLR Hand Arm System Rapid Prototyping Shoulder 2 Shoulder 1 Forearm BiSS 10 MBit SpaceWire 1Gbit 3 khz Host Control Loop Folie 10

10 The Hierarchical Architecture - Computing nodes Computing Bandwidth General Purpose, COTS [Joerg et al., IROS 2011] Linux UI Host QNX Real - Time PC Hosts 40 x 40 mm Composition 10 x 10 mm Modules High integration, Dedicated Electronics Physical Interfaces Folie 11

11 The Hierarchical Architecture Computing Bandwidth General Purpose, COTS [Joerg et al., IROS 2011] Linux UI Host TCP/UDP 1GBit QNX Real - Time PC Hosts 40 x 40 mm SpaceWire 1Gbit Composition 10 x 10 mm BiSS 10 MBit Modules High integration, Dedicated Electronics SPI, I 2 C, PWM, Physical Interfaces Folie 12

12 The Hierarchical Architecture - Physical Interfaces Computing Bandwidth General Purpose, COTS Linux UI Host TCP/UDP 1GBit QNX Real - Time PC Hosts 40 x 40 mm SpaceWire 1Gbit Composition 10 x 10 mm BiSS 10 MBit Modules Arm Main High integration, Dedicated Electronics SPI, I 2 C, PWM, Physical Interfaces Folie 13

13 The Hierarchical Architecture - Modules Computing Bandwidth General Purpose, COTS Linux UI Host TCP/UDP 1GBit Potentiometer Module QNX Real - Time PC Hosts 40 x 40 mm Spacewire 1Gbit Angular Hall Module Composition MiniServo Module 25x25x25 mm 10 x 10 mm BiSS 10 MBit Modules High integration, Dedicated Electronics SPI, I 2 C, PWM, Physical Interfaces Folie 14

14 The Hierarchical Architecture - Composition Computing Bandwidth General Purpose, COTS Linux UI Host TCP/UDP 1GBit SpaceWire PCIe Forearm Node QNX Real - Time PC Hosts 40 x 40 mm Spacewire 1Gbit Composition Arm Node 10 x 10 mm BiSS 10 MBit Modules High integration, Dedicated Electronics SPI, I 2 C, PWM, Physical Interfaces Folie 15

15 The Hierarchical Architecture The HAL Computing Bandwidth General Purpose, COTS Hardware Abstraction Layer Linux UI Host TCP/UDP 1GBit QNX Real - Time PC Hosts 40 x 40 mm Spacewire 1Gbit Composition 10 x 10 mm BiSS 10 MBit Modules High integration, Dedicated Electronics SPI, I 2 C, PWM, Physical Interfaces Folie 16

16 The Virtual Path From Sensor to Actuator Computing Bandwidth General Purpose, COTS Linux UI Host TCP/UDP 1GBit [Nickl et al. 2009] Controller QNX Real - Time PC Hosts 40 x 40 mm Computation and Communication Path Spacewire 1Gbit Composition 10 x 10 mm BiSS 10 MBit Modules Sensor High integration, Dedicated Electronics Actuator SPI, I 2 C, PWM, Physical Interfaces Folie 17

17 The Virtual Path From Sensor to Actuator The Application is synchronized by the sensor hardware (The Virtual Path [Nickl et al. 2009]) Synchronisation Clock t Physical t n Sensor Controller Actuator Clock t n t Latency = t Physical - t n t Physical Error Detection And Handling Computation and Communication Path Folie 18

18 The Virtual Path From Sensor to Actuator Computing Bandwidth General Purpose, COTS Linux UI Host TCP/UDP 1GBit [Nickl et al. 2009] Controller QNX Real - Time PC Hosts 40 x 40 mm Computation and Communication Path Spacewire 1Gbit Composition 10 x 10 mm BiSS 10 MBit Modules Sensor High integration, Dedicated Electronics Actuator SPI, I 2 C, PWM, Physical Interfaces Folie 19

19 SpaceWire-Implementation: Requirements for Robotics Deterministic Defined Topology Packet length limited to 1024 bytes Clock with Time Codes Low latency up to 1 Gbit/s implementation PCIx Host adapter with drivers for QNX/VxWorks High integration Own electronics (cables, connectors) Manageable Configuration from file Test Suite PCIx host adapter Folie 20

20 SpaceWire-Implementation: Physical, Character, Link Layers LVDS and Fiber Up to 1 GBit/s 8b10b encoding () Links with CRC Kinemedic 2005 ESC KChar IDLE K28.5 TC K28.1 FCT K28.2 EEP K28.3 EOP K28.4 NULL K28.6 Copper Link with 8b10b ESC to Kchar mapping Folie 21

21 SpaceWire-Implementation: Standard Network Layer Implemented on Router Configuration Protocol (for runtime configuration of address tables) Kinemedic 2005 FIFO Links with CRC FIFO FIFO 1 3 FIFO 1 3 FIFO Router Router Router FIFO FIFO FIFO FIFO Network Packet 32 payload eop Logic/Physical LUT Folie 22

22 SpaceWire-Implementation: Our Transport Layer Connection-oriented proctocols CRC protected payload Peer Address is configured at runtime MICA 2008 Source Datagram Sink Datagram Protocol Request Source Response Sink RequestResponse Protocol Logic. Addr. Packet ID payload crc eop Transport Packet Folie 23

23 Hand Results: DLR Hand Arm System SpaceWire Topology Arm Upper Side Lower Side Host Shoulder 1 Forearm Shoulder 2 Triple Joint Stack Double Joint Stack Host Router Nodes Hand 4 52 Arm 5 45 Hosts 4 4 Total Folie 25

24 Results: Arm Control Application SpaceWire Packets Triple Joint Stack Double Joint Stack Shoulder 2 Shoulder 1 Host 3 khz Host Control Loop, Signals by Datagram Protocol Triple Double Total Bytes Actual Packets / cycle / sec k Desired Packets / cycle / sec k Total / cycle / sec k Folie 26

25 Results: Arm Control Application - Latency of 3kHz Loop Empty Simulink Damping Control Application Shoulder1 Shoulder2 Upper Arm Elbow mean HAL only mean [μs] (empty Simulink model) std [μs] Damping Control mean [μs] [Petit et al., ICRA 2011] std [μs] deadline: 2 cycles = 667μs Folie 27

26 Conclusions & Outlook Experiments prove stability and determinism (Latency < 667us) Hierarchical architecture enables high integration at manageable effort SpaceWire has been succesfully utilized as communication backbone for robotic systems of increasing complexity Further work: Complete humanoid robot Experiment with highly distributed algorithms (safety, reflex actions) Folie 28

27 Thank you! Folie 29