Expression of Interest (EoI) for Transfer of Technology

Transcription

1 Expression of Interest (EoI) for Transfer of Technology 10G Ethernet MAC IP core (IEEE802.3 compliant 10Gbps 64-bit Ethernet Media Access Control [MAC] IP core) Issued by Centre for Development of Advanced Computing (A Scientific Society of the Ministry of Communications and Information Technology, Govt. of India) C-DAC Knowledge Park, Opp. HAL Aeroengine Division, Old Madras Road Byappanahalli, Bengaluru Karnataka (India) Phones: /01/02/03, / / Fax:

2 Table of Contents 1 Introduction 2 About C-DAC 3 About 10Gbps Ethernet MAC IP Core 4 Application Areas 5 Technology Transfer 6 General terms and conditions 7 Who can apply? 8 How to apply? 9 Contact Person Annexure I - Template for the EoI for Technology Transfer Annexure II Product Brochure 2

3 List of Abbreviations Abbreviation C-DAC DeitY EoI ICT IP MCIT MAC R & D RTL ToT XGMII Description Centre for Development of Advanced Computing Department of Electronics and Information Technology Expression of Interest Information and Communications Technology Intellectual Property Ministry of Communications & Information Technology Media Access Control Research and Development Register Transfer Logic Transfer of Technology 10 Gigabit Media Independent Interface 3

4 1. Introduction The Department of Electronics & Information Technology (DeitY) under Ministry of Communications & Information Technology, Government of India initiated the Design and Development of 10Gbps Ethernet MAC IP core for R&D purpose in project Design and Development of a Cooperative High Performance Traffic GENErator for Time-Sensitive Network AnalYSis (GENESYS) with C-DAC, Bangalore as the implementing agency. The project conceptualizes the indigenous development of High-speed network system with suitable new generation FPGA (Virtex 6), along with the associated Media Access Control (MAC) IP cores for next generation. Secure Hardware and VLSI Design Group (SHVD) of C-DAC, Bangalore has developed the 10Gbps Ethernet MAC IP core and the technology is available for transfer to interested establishments. C-DAC, Bangalore would like to invite competent industrial partners for commercialization of the 10Gbps Ethernet MAC IP core through transfer of technology. 2. About C-DAC Centre for Development of Advanced Computing (C-DAC) is the premier R&D organization of the Department of Electronics and Information Technology (DeitY), Ministry of Communications & Information Technology (MCIT) for carrying out R&D in IT, Electronics and associated areas. Different areas of C-DAC, had originated at different times, many of which came out as a result of identification of opportunities. More details about C-DAC can be found at 4

5 3. About 10Gbps Ethernet MAC IP core Description The 10GbE MAC core designed by C-DAC-Bangalore is compliant with IEEE (802.3ae) specifications. The core is designed to support different configuration modes controlled by core's register file. The 10GbE MAC core has a data-path of 64-bits. The core has AXI-4 Streaming user application interface. The application interface is designed as a 64-bit bus operating at MHz. The core also provides AXI-4 Lite interface to read/ write configuration registers for control and configuration of the 10GbE MAC. The Key features of 10Gbps Ethernet MAC IP core are: Complaint with IEEE 802.3ae specification with preamble/ SFD generation, frame padding, CRC generation and checking on transmit and receive respectively. XGMII interface operating at MHz. Implements reconciliation layer functionality with start and terminal control character alignment, error control character and fault sequence insertion and detection. Supports IEEE XON-XOFF Pause Frame generation and termination for traffic flow control. Supports Deficit Idle Count (DIC) mechanism to maintain average 12 byte IFG. Padding of frames if the size of frame is less than 64 bytes. Performs RS functionality by inserting proper control characters as specified by IEEE 802.3ae specifications. Automatic generation of FCS/ PAD during transmission on per frame basis. Optional Forwarding of CRC to the user application interface. Status signals available with each Frame on the user-interface providing information such as valid frame, address mismatch, CRC error, etc. Internal XGMII Loop-back (Optional). Supports Jumbo frames. 5

6 Configurable Transmit and Receive FIFOs. Provides AXI-4 streaming user application interface with 64-bit bus operating at MHz. Provides AXI-4 Lite interface to read/ write configuration registers for control and configuration of the 10GbE MAC. Statistics counters indicating total number of valid frames, CRC errors and address check errors etc. which can be reset by the user. 10GbE MAC IP core design has been tested and validated on Xilinx Virtex-6 HX380T FPGA device. The brochure of the product is attached in Annexure II 4. Application Areas + Benefits of the product The 10Gbps Ethernet MAC IP core could be used as a component in the following application scenarios: Network Interface Controller OTN fabric TCP/IP Offload Engine Layer-2 Network Tester Ethernet Switch Fabric Hardware based Firewall Ethernet to OTN mapper Network Packet analyzer / monitor / filter Since the IP core will be provided in source-code form, it ll enable the end-user with the flexibility to modify / enhance / customize RTL IP core for future needs based on the application scenarios. 6

7 5. Technology Transfer The technology will be transferred on non-exclusive basis. The technology fee will be finalized at a later stage. The ToT package contains the following: 1. User-Reference Guide for 10Gbps Ethernet MAC IP core with block-level and low-level description of the IP core, interfacing details, memory-map, etc. 2. RTL source-code (in VHDL) of the IP core, along with the test benches. 3. Scripts for synthesis. 4. Scripts for simulation. 5. Handholding support for a period of 6 months 6. General terms and conditions i. An expert committee will scrutinize the applications for follow-up action. ii. The applicants may be called for a presentation regarding their strengths and business proposals. iii. All incidental expenditure incurred in preparation/ submission or presentation of the EoI shall be borne by the participating agency iv. Participation in this EoI does not guarantee any association with C-DAC unless notified by C-DAC in writing. v. The design of the IP, shared by C-DAC at the time of ToT to the establishment receiving the ToT, will be final. No further changes / revisions / enhancements by C-DAC will be considered. vi. C-DAC reserves the right of rejecting any offer without assigning reasons. vii. Last date for submission of EoI is 45 days from issue of the first advertisement. Any offer received after due date and time will not be accepted. 7

8 viii. There is neither a business guarantee nor any commitment for funding support from C-DAC to the appointed / empaneled agencies. ix. A Committee of experts constituted by C-DAC will assess capabilities and strengths of the industry before finalizing the technology partners. x. The industry willing to take technology for commercial exploitation will be required to enter into a ToT agreement with C-DAC as per the terms and conditions approved by the competent authority in the DeitY in the prescribed format. 8

9 7. Who can apply? Establishments working on design and development of FPGA based designs for high speed data and communication networks, high speed network applications etc. Establishments offering FPGA based design solutions / services / products in high-speed data and communication networks, high speed network applications etc. Establishments with interest in Electronics or Information and Communications Technology (ICT) Agencies willing to take up the production, proliferation of 10Gbps Ethernet MAC IP core and integrating 10Gbps MAC IP into their products, application developments on 10Gbps MAC IP etc. as per the ToT guideline agreement of C-DAC. Establishments having years of design and development expertise in areas related to: telecommunications systems, communication and network protocols, test & measurement equipment, networking equipment, network monitoring equipment, high performance hardware systems, security hardware systems for high speed networks etc. having good experience in design and development of complex FPGA based digital design / FPGA based system design / FPGA based SoC design can apply. Expected capabilities of the establishments are captured in the table below: Expected Capabilities Expertise in HDL languages and EDA tools, RTL design etc. Expected & related Skillsets/ Technologies Verilog, VHDL, Xilinx XST Design Flow. Data Communication interface expertise Programmable Device Expertise Ethernet, PCIe, I2C, etc. FPGA Device Internals and development on FPGAs 9

10 8. How to apply? Interested companies may send expression of interest with their details by filling the questionnaire as per Annexure I along with supporting documents to: Executive Director Centre for Development of Advanced Computing C-DAC Knowledge Park, Opp. HAL Aeroengine Division, Old Madras Road Byappanahalli, Bengaluru Karnataka (India) Phones: /01/02/03, / / Fax: Contact Person for queries Shri. Vivian Desalphine Senior Technical Officer, SHVD Land Line: viviand@cdac.in 10

11 The below needs to be given A. Company Profile 1. Name of the Organization: Annexure-I Website 2. Details of the Contact Person: Name: Address Telephone: Fax: 3. Year of Incorporation 4. Type of Organization Public Sector/ Limited/Private Limited/ Partnership/ Propritery/ Society/ Any other Whether Foreign Equity Participation (Please give name of foreign equity participant and percentage thereof) Names of Directors of the Board/ Proprietors Name and address of NRI(s), if any 5. Category of the firm: Large/Medium/Small scale unit 11

12 6. Address of the Registered Office: 7. Number of Offices with addresses (Excluding Registered Office: India Abroad 8. Certificate of registration as a manufacturing unit 9. Permanent Account Number 10. Sales Tax Number/ VAT 11. Status of ISO9001/ISO13485 Certification The following documents need to be attached along with EoI: 1. Organization Brochure 2. Certificate of Registration / Incorporation 3. Certified copies of turn over for last three financial years (For start-up companies, instead of three years turnover, future business plan for three years should be mentioned). 4. Three year business plan (For start-up companies same as above point i.e business plan for three years should be mentioned). 4. Permanent Account Number. 5. Write up on technical capabilities. 7. The list of machine tools /equipment s/software s/facilities available related with work to be furnished. 8. The manpower strength (Technical: Mechanical, Electrical, Electronics, Software & Non-Technical etc.) at various levels to be furnished 12

13 Technical: a. B.E./ B.Tech/Ph.D b. Diploma c. Skilled Technicians Non-technical: Note: Expression of interest should be stamped and signed by authorized signatory with a formal declaration note. 13

14 Annexure II: 10GbE MAC IP brochure 14