THE NEW ERA ON LOW POWER DESIGN AND VERIFICATION METHODOLOGY

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1 THE NEW ERA ON LOW POWER DESIGN AND VERIFICATION METHODOLOGY 1 NAVEEN KUMAR CHALLA, 2 USHA RANI NELAKUDITI 1,2 Department of Electronics and Communications Engineering, Vignan s Foundation for Science, Technology and Research University, Guntur, Andhra Pradesh, India 1 ch.naveen108@gmail.com, 2 usharani.nsai@gmail.com Abstract In earlier days, after IC is fabricated the main objective is to verify the functionality. Since overlook of errors at this level causes big loss in terms of money and time, if errors occurs during design/coding level according to the law of ten..but current day paradigm has been shifted to power instead of functionality due to demand of high speed VLSI structures together with network processors in networking or SOCs in communication. Keep this in view this paper deals with the review of various power aware designs like clock gating, power gating, dynamic voltage scaling and frequency scaling. It also explains recent popular IEEE 1801Unified power format (UPF) used for design and verification of low power Integrated Circuits.UPF translated energy design into an executable hierarchical parallel system design. This method is a systematic approach and paves the solution to many critical designs. Index Terms Low Power Verification, Unified Power Format, Register Transfer Level, Power-Aware design, Clock gating, Power gating, Frequency scaling. I. INTRODUCTION In semiconductor industries power aware verification is an important aspect. Shrinking geometries have led designers to appoint numerous power aware verification solutions to minimize static and dynamic power dissipation. The increasing demand for highoverall performance computing interest has been changed from conventional constraints to power intake in case of battery-operated system-on-chips (SoC). System nodes under a 100 nm, power consumption is mainly due to leakage which constitutes 40 percent in case of65nm node. The quadratic dependency of power leakage on the total transistor count qualifies leakage optimization as a key design objective. Therefore,designers have redirected their efforts towards exploring numerous techniques that reduce leakage and, thereby enhancing the battery life of products.there are numerous strategies which have been developed during the last decade to deal with the power requirements of ASIC and SoC designs [5]. They include clock gating, multi-switching (multi- Vt) threshold transistors, dynamic voltage and frequency scaling (DVFS), substrate biasing and unified power format.[2]. A. Basics of Power Optimization As a primary order approximation, the power consumption of CMOS gate can be approximated as in eqn(1). P = 0.5 CLV2f + VI (1) Where V is the supply voltage, CL is the load capacitance, f is the switching frequency. The frequency f of this equation describes the dynamic power of the design and the second term describes the static power. To reduce the total power, it is vital to reduce both additives of this equation, or at the least make sure that there may be a cumulative reduction. To optimize energy, it's important to make sure each level of the design right from set of design rules to transistor size is to be optimized by retaining any terrible impact on the subsequent stage to be minimal. Though at geometries of 32 nm or underneath, dynamic power constitutes a major component of the entire power dissipation, dynamic power designs mainly concentrate on switching activity. Clock gating is a popular design technique used to optimize dynamic power. The granularity of clock gating and the effect it has on average power consumption depends at the segment of the design cycle. B. Low Power Design The low power design requires proper power control essentially at 90nm and 65nm. The power dissipation with respect to technology is shown in Fig.1. Fig.1.Total power Vs Technology From the figure, leakage power increases as technology scales down. The growing of leakage with geometries due to the thin silicon partition. Conventional low power design techniques include reduction of Vdd and clock gating. To preserve performance and stability Vdd is more optimal. 160

2 C. Need for low power design Now-a-days semiconductor designs like cell phones and networking or garage gadgets decrease power for longer battery life. power handling in complicated system-on-chips (SoC) and custom processors is rising. Shutting down the blocks can be accomplished either by software program or hardware.hardware timers can be utilized.[6]. D. Need of Verification Verification isn't the same as design, but it calls for whole understanding of the design. A primary purpose of functional verification is ready finding disasters, figuring out insects and correcting earlier than they're mapped into the IC. As electronics marketplace is converting hastily and its increase being large it induces designers to head for complicated IC design and packing them into small areas. So system on chip (SOC) are advanced. 70 % of design attempt goes to verification. Checking of complex design, keeping high brow belongings (IP), trying out of SOC makes verification a tough mission. So in an enterprise the range of verification engineers is lots extra than RTL designers. II. LOW POWER DESIGN TECHNIQUES IN VLSI Though Voltage reduction up to sub one volt is the important low power method some other design based methods are explained in this session. Some of the RTL degree strategies used mainly to lessen the dynamic power of the design are mentioned underneath. A. Clock gating Generally used at RTL and gate-level abstractions as shown in fig.2..it is a dynamic power control technique uses a gated clock presents a way to selectively stop the clock, forces the original circuit to make no transition at the subsequent redundant clock cycle. For reactive circuits, the range of clock cycles in which the design is idle is large.[6]. Fig.3. Power Gating C. Multi-Voltage design Multi-Threshold CMOS (MTCMOS) is a variant of CMOS chip generation, which has transistors with multiple threshold voltages (Vth) as shown in Fig.4 in an effort to optimize power. Low Vth devices switch faster, and are therefore beneficial for essential delay paths to minimize clock intervals. The disadvantage with low Vth devices has substantially higher static leakage power. Excessive Vth devices are used for non-critical paths to reduce static leakage power without incurring a delay penalty. Typical excessive Vth gadgets lessen static leakage by way of 10 times in comparison with low Vth gadgets. Fig.4.Multi-Voltage Design D. Voltage/ Frequency scaling Dynamic frequency scaling as shown in Fig.5 is also referred to as CPU throttling is a technique in laptop structure wherein the frequency of a microprocessor may be automatically adjusted "at the fly," either to conserve power or to reduce the quantity of warmth generated by using the chip. Dynamic frequency scaling is typically utilized in laptops and different cell gadgets, in which power comes from a battery and as a result is restrained.[6]. Fig.2. Clock Gating B. Power gating Power gating as shown in Fig.3 is utilized in integrated circuit design to lessen power consumption, by way of shutting off the contemporary blocks of the circuit that are not in use. It also influences design, architecture more than clock gating. It will increase time delays, as power gated modes have to be correctly entered and exited. Fig.5.Voltage/Frequency Scaling 161

3 III. IEEE 1801 OR UPF Hardware Description Language (HDL) semantics do not take power into account. Consequently the traditional flows lack the ability to include the power motive of a design and also power aware verification. In 2007, Accellera added a Tcl -based way of defining the power motive of a design, named Unified Power Format (UPF.) Later, IEEE , [1] a trendy format for outlining power reason, become added to the ASIC enterprise. Nowadays, IEEE 1801 (UPF) makes it possible to design low power integrated circuits, trap the purposeful mistakes that would have been prompted by powercontrol strategies, and verify a low power operation in the course of simulation and/or emulation. The position of IEEE 1801 (UPF) is to include the power control constructs including power switches, isolation cells, retention registers, etc. inside the design as early as feasible, so that verification and debug of the SoC can be started out earlier in the timeline and doubtlessly save it from errors, massive or small. Doing so permits the verification engineers to check the SoC with power-control considerations.[1]. IV. EVOLUTION OF UPF As of now, there are three versions, specifically UPF 1.0, UPF 2.0 [5] and UPF 2.1 evolved by using Accellera. UPF 1.0 centered on adding power cause to the existing HDL. It changed into based on incredibly simple concepts and instructions.upf 2.0 changed into authorized in March 2009 and was backward well matched with UPF 1.0.It turned into mainly targeted on IP improvement and refinement. And the last and present UPF 2.1 model become permitted in March 2013.UPF 2.1 became also based on UPF 1.0 and except new abstractions have been added which turned into completely supported in any complicated SoC designs. UPF 2.1 clarifies and enhances UPF 2.0 residences. The evolution of all the 3 variations has been proven in the parent under in Fig.6.[1]. chip. Three UPF files have been provided to us via the implementation crew as they are also used by them in the implementation go with the flow. those UPF documents have been generated supplying one UPF file for each cluster and a top degree UPF record. The cluster degree UPF files were hierarchically scoped into the top stage UPF in preference to the usage of just one UPF file defining the full chip. A unmarried UPF file is hard to read and to debug. Defining separate UPFs as approach is a clean way to hold the gadget stage power rationale approach and i would suggest doing it this way. on this phase we can speak briefly the various sections of a UPF record. One analogy to give an explanation for the UPF record would be the power wiring in your property. there's a power deliver that is connected to specific sections (domain names) of the house thru switches the usage of wires. The following section briefly describes the various additives of a UPF file, and we ll comply with this analogy via as we describe the important thing features of UPF[5]. A. Create Power Domains Power domain names are like the rooms in the house with all of their exceptional components like lighting fixtures, outlets to power TV s, stereos, and many others. Power domains are used to outline a collection of layout components so that it will be controlled through a power supply. In this situation, we needed to define 3 such power domains. The code beneath indicates how to outline a power domain. create_power_domain PD_TOP create_power_domain PD_cluster0 -elements {CLUSTER0} create_power_domain PD_cluster1 -elements {CLUSTER1} B. Create supply ports The deliver ports are just like the major deliver to the house that feeds into the circuit breaker. There may be more than one supply port defined for a design. create_supply_port VDD_0d99 -domain PD_TOP create_supply_port VDD_0d81 -domain PD_TOP create_supply_port VSS -domain PD_TOP Fig.6. Evolution of UPF V.BUILDING THE UNIFIED POWER FORMAT FILE (UPF) A UPF record is defined by way of the IEEE popular to describe the power motive of the C. Create supply nets The supply nets are like the wiring between the breakers within the house and the primary electricity deliver In the example beneath we're growing a internet named net_vdd_0d99_n and this can deliver electricity to the CLUSTER0 power area. create_supply_net vdd_0d99_n -domain PD_cluster0 create_supply_net vdd_0d81_n -domain PD_cluster1 create_supply_netvss_n -domain PD_cluster0 create_supply_netvss_n -domain PD_cluster1 D. Connecting supply ports to supply nets The deliver nets want to be related to the deliver ports as shown under. connect_supply_net vdd_0d99_n -ports VDD_0d99 162

4 connect_supply_net vdd_0d81_n -ports VDD_0d81 connect_supply_netvss_n -ports VSS E. Connecting supply nets to power domains In the end the deliver nets need to connect with a particular power domain. set_domain_supply_net PD_TOP \ -primary_power_net VDD_0d99 \ -primary_ground_netvss_n set_domain_supply_net PD_TOP \ -primary_power_net VDD_0d81 \ -primary_ground_netvss_n F. Creating power switches The power switches are just like the breakers that energy the rooms with the lights and retailers. create_power_switch cluster0_sw \ -output_supply_port \ {vout_pcluster_n} \ -input_supply_port \ {vin_p vdd_0d99_n} \ -control_port {cntrl_pcluster_sw_cntl} \ -on_state {on_statevin_p {cntrl_p}} \ -off_state {off_state {!cntrl_p}} G. Isolation once the cores are switched off, their outputs will now not be driven any more which motive troubles with X s propagating into other blocks. To restoration this hassle, isolation cells are added to the design using the instructions under inside the UPF file. persevering with with the analogy, we may want to think about doors in a room as Isolation, as they prevent darkness from moving into any other room while closed. set_isolationarith_iso -domain pd_cluster0 \ -isolation_power_net vdd_0d99_n \ -isolation_ground_netvss_n \ -clamp_value 1 \ -applies_to outputs \ -elements {CLUSTER0} set_isolation_control cluster0_iso -domain pd_cluster0 \ -isolation_signal cluster0_iso_en \ -isolation_sense high \ -location parent -domain PD_cluster0 \ -applies_to outputs \ -location parent I. Retention registers Retention registers are used to preserve the state of the circuit from before power-down to after the power domain is powered up. Any memory element that is not initialized/reset after a power-on, and does not retain its previous state, will have an unpredictable initial value. These unpredictable initial values are easily represented in the simulation as X as opposed to 0 or 1. However, in emulation, they must be randomly represented as 0 or 1 at each different run of the test. set_retention cluster0_ret \ -domain PD_cluster0 \ -retention_power_net vdd_0d99_n \ -retention_ground_netvss_n set_retention_control cluster0_ret \ -domain PD_cluster0 \ -save_signal {save_cluster0_out high} \ -restore_signal {restore_cluster0_out low} H. Creating Level Shifters The level shifters are used to vary the voltage ranges to the various devices within the house. There might be a few gadgets that want as 120V deliver even as others run at 220V. We did no longer need to use stage shifters in this assignment, because the requirement turned into most effective to test that the diverse domains will be powered up and down. set_level_shifter cluster0_cluster1_in -domain PD_cluster0 \ -applies_to inputs \ -location self set_level_shifter cluster0_cluster1_out \ Fig.7. Structure of UPF J. Power state domains As shown in Fig.7. the SoC became divided into three power domain names (Cluster 0, Cluster 1 and the rest of the SOC). The requirement become that Cluster 0 and 1 might be completely powered ON or OFF, whilst the SoC area will stay powered up whilst 163

5 both cluster is powered down and all manipulate registers reside inside the SoC domain. A specific collection of events desires to be accompanied at the same time as powering down or powering up a middle, which was furnished by way of the center group. Table 1 suggests the various power domain states for all of the cores. The most interesting instances to check were whilst either cluster was powered down while the alternative cluster became used to look ahead to power down after which generate an occasion to the outside energy controller. Once the power controller noticed the occasion, it followed the vital steps to program the registers inside the SoC area to begin the power up method. We decided this turned into best achieved with the aid of growing a power aware simulation strategy. TABLE. 1. Power state modes Low power specs are wanted at each step of the design go with the flow so that accurate power control additives can be carried out on the RTL, inferred efficiently at some point of synthesis, and located-and-routed effectively and accurately within the bodily design. This requires a single power format regularly occurring by means of all equipment inside the flow at any given abstraction level. A single power design eases implementation and validation and enables meet design schedules. It should also deal with reusability, allow early and thorough validation, and feature built-in extensibility. Accellera, an corporation focused on identifying and creating new standards and methodologies for the electronic design enterprise, lately accredited a standard for low power design motive specification is referred to as the UPF. Written in Tcl, UPF captures the low power design specification in a transportable form to be used in simulation, synthesis, and routing, lowering potential emissions throughout translation of HDL description and may be read by using all of the gear in the flow, the UPF facet document is as portable and interoperable because the good judgment design s HDL code. Fig.8. side file provides a consistent semantic for all tools throughout the design flow. 164 VI. THE POWER AWARE SIMULATION FLOW Power Aware Simulation (PA Simulation) solves the hassle of practical verification of power aware designs. It offers architects the capability to functionally verify their power control strategies on the RTL, decreasing costs appreciably both in effort and time. PA Simulation works with ordinary RTL coding patterns. RTL blocks are effortlessly reused without editing the RTL code, and new reusable blocks can be made independent of the power-aware environment. The simulator is able to Pick out all sequential elements inferred by the RTL design (registers, latches, and retentions). Overlay the RTL design with the PCN. Pull in the right retention-cell version behavior. Dynamically alter the conduct of the design to reflect the required low power design intent in power down and up situations. PA Simulation is broadly categorized into 4 steps: Check in/latch popularity from the RTL pattern. Identification of power elements and their power manage alerts. Elaboration of the power aware design. Power aware Simulation.[10]. Fig.9.Quasta simulation flow with Power Aware Modeling[8] CONCLUSIONS One viable way is specifying low power motive in a general format that is portable across a huge variety of EDA equipment Accellera created a single, standard low power design referred to as the Unified Power Design(UPD). beneath UPF transforms from RTL to netlist. A design, a UPF file is generated at each degree by means of the imposing tools to mirror the modifications in logical and physical hierarchy and the interaction among diverse factors inside each energy domain, in addition to between extraordinary domains. Interoperability between implementation and verification gear, ensuring better first-class of silicon and elimination of iterations for improved productiveness. no matter the reality that a few EDA vendors have tried to push proprietary low power codec s, maximum carriers large and small alike have followed this new low power fashionable for his or her low energy gear. with the aid of adopting UPF,

6 every EDA seller has retained proprietary control of its respective silicon-established gear, at the same time as allowing the fashion designer to maintain control over her design data. In contrast to unmarriedsupplier manage over the format and related tools, UPF is a standard format this is without a doubt open and available to the clothier community for destiny improvements. Dressmaker manage over low power design purpose statistics, and the freedom to use the nice gear at her disposal in place of being tied to a single supplier, is the real measure of improved productivity. For more facts on UPF and to down load the UPF specification, please visit Accellera s website: The power aware design advent via its dependence on numerous power domains launches extra probabilities for mistakes. On every occasion this occurs, corporations are asked to set equipped the units to facilitate accurate practical Verification with identification of flaws within the specification or implementation. The logically low electricity unfastened coupling along side functional design objective, allows separate specification, together supplying the independence to characterize a concise and advanced mechanism for low power design purpose specification. This device permits better IP reuse in diverse low power structural designs. REFERENCES [1] Unified Power Format, IEEE Draft Standard for Design and Verification of Low Power Integrated Circuits, IEEE P1801/D18, 23, October, [2] Freddy Bembaron, Rudra Mukherjee, Sachin kakkar and Amit Srivastava Low Power Methodology using UPF pp [3] M.Keating etl al, Low Power Methodology Manual, Springer [4] Stephen Bailey,Gabriel Chidolue,Allan Crone, of Mentor Graphics, "Low Power Design and Verification Techniques", white paper. [5] Accellera, "Accellera: Unified Power Format (UPF) 1.0 Standard,"pp , February 2009 [6] VLSI-Design.html [7] Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian Shi Low Power Methodology Manual For System-on- Chip Design, Springer, [8] Croft, M. ; Bailey, S," Is Your Low Power Design Switched On? ".International Symposium on System-on- Chip, 2007 pp: 1-4 [9] Rudra Mukerjee, Amit Srivastava and Stephen Bailey,"Static and Formal Verification of Power Aware Designs at the RTL Using UPF", Mentor Graphic white paper. [10] Stephen Bailey, Gabriel Chidolue,"Advanced verification of low power design", Mentor Graphics white paper [11] F. Bembaron, S. Kakkar, R. Mukherjee, and A. Srivastava, "Low Power Verification Methodology Using UPF," in Conference on Electronic Systems Design and Verification Solutions, DVCON,2009, pp [12] R. Lissel and J. Gerlach, "Introducing new verification methods into a company's design flow: an industrial user's point of view," in Design,Automation & Test in Europe, Conference & Exhibition DATE'07. [13] IEEE, April 2007, pp [13] H. Jian and S. Xubang, "The Design Methodology and Practice of Low Power SoC," in Embedded Software and Systems Symposia,2008. ICESS Symposia'08. International Conference on, 2008, pp [14] Kapoor, Bhanu ; Hemmady, S. ; Verma, S. ; Roy, K. ; D'Abreu, M.A.," Impact of SoC power management techniques on verification and testing"quality of Electronic Design, ISQED pp [15] Trummer, C. ; Kirchsteiger, C.M. ; Steger, C. ; Weiß, R. ; Pistauer, M.Dalton, D. Automated simulation-based verification of power requirements for Systems-on-Chips,IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 pp 8-11 [16] Mehta, S.,"Industry Standards from Accellera "21st International Conference on VLSI Design, VLSID 2008,pp 728 [17] Hazra, A. ; Mitra, S. ; Dasgupta, P. ; Pal, A. ; Bagchi, Debabrata; Guha, K.," Leveraging UPF-extracted assertions for modeling And formal verification of architectural power intent ",47 th ACM/IEEE Design Automation Conference (DAC), 2010,pp